WO2007142190A1

WO2007142190A1 - Display drive circuit and display

Info

Publication number: WO2007142190A1
Application number: PCT/JP2007/061291
Authority: WO
Inventors: Kouji Kumada
Original assignee: Sharp Kabushiki Kaisha
Priority date: 2006-06-09
Filing date: 2007-06-04
Publication date: 2007-12-13

Abstract

By commonly using signal lines except for the signal lines to common electrodes (6) out of the signal lines including control signal lines for driving first and second panels (1a, 1b), a display drive circuit comprises shared signal lines provided to the display panels. The shared signal lines include at least one panel common signal line (e.g., a video signal line) used common to the first and second panels (1a, 1b) and panel individual signal lines (e.g., an SSP signal line of a first shift register circuit (8)) used for separately control the first and second panels (1a, 1b). A SEL control signal line is provided to select one of the signals to the first and second panels (1a, 1b) supplied through the panel individual signal lines depending on the first and second panels (1a, 1b). With this, without much increasing the number of signal lines, degradation of the display definition is not invited, and signal lines to display panels are can be shared. A display is also disclosed.

Description

Specification

Display device drive circuit and display device

Technical field

The present invention relates to a drive circuit for an active matrix drive display device including a plurality of display panels, and a display device.

Background art

[0002] As TFT-LCD panels, there are mainly amorphous silicon TFT-L CD panels with low electron mobility and polysilicon TFT-LCD panels with relatively high electron mobility.

[0003] As a driving method suitable for each, line-sequential driving has been adopted for amorphous silicon TFT-LCD panels, while dot-sequential driving has been adopted for polysilicon TFT-LCD panels.

[0004] In the amorphous silicon TFT-LCD panel, signal lines corresponding to the display resolution are required for line sequential driving, so there is a concern that the cost of the driving circuit is increased and the reliability is lowered. On the other hand, polysilicon TFT-LCD with relatively high electron mobility effectively utilizes the performance and adopts dot-sequential driving where the number of signal lines does not depend much on the display resolution, thereby driving circuit costs. Down and improved reliability.

[0005] The drive circuit of the display device has, for example, the configuration shown in FIG. 10 and is driven by the driving method shown in FIG.

[0006] On the other hand, for mobile phones and game machines, there are an increasing number of cases where a plurality of display panels are used in one device. In this case, for example, a drive circuit for a display device having the configuration shown in FIG. 12 is used.

However, in order to use such a plurality of display panels in one device, it is desirable to share drive wiring among the plurality of display panels. As a technique for sharing this drive wiring, in line sequential driving, for example, it is disclosed in Patent Document 1 and Patent Document 2, and a method in which either a video signal line or a scanning signal line is shared is adopted. . However, the documents 1 and 2 do not particularly disclose dot sequential driving. actually In the dot sequential driving method, the number of signal lines is increased without sharing the signal lines, so that a configuration using a plurality of display panels can be supported.

Patent Document 1: Japanese Published Patent Publication “Japanese Patent Laid-Open No. 2004-117755 (Publication Date: April 15, 2004)”

Patent Document 2: Japanese Published Patent Publication “Japanese Unexamined Patent Publication No. 2004-177528 (Publication Date: June 24, 2004)”

Disclosure of the invention

[0008] However, in the conventional display device driving circuit and the display device, in the dot sequential driving method, which is advantageous in that the number of signal lines is small, the number of signal lines is reduced in order to drive a plurality of display panels. The increase will lead to the expansion of LSI packages and the associated cost increase.

[0009] Further, simply sharing signal lines for a plurality of display panels may cause a reduction in display quality, or may cause some of the plurality of display panels to be simultaneously used. If the display quality changes between the case of displaying and the case of displaying one display panel, there is a problem.

The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide signals to a plurality of display panels without causing an excessive increase in the number of signal lines and a reduction in display quality. Provided is a display device driving circuit capable of sharing a line and a display device.

In order to solve the above problems, the drive circuit of the display device according to the present invention turns on a video signal line, a scanning signal line, a pixel, a pixel switching element, a common electrode, and a video signal applied to the video signal line. A sampling switching element for Z-off, a first shift register circuit for generating a signal for controlling an on-Z-off period of the sampling switching element, and a second for generating an on-Z off signal for the pixel switching element to be applied to the scanning signal line A drive circuit for a display device that drives a plurality of display panels having a shift register circuit, and excludes signal lines to the common electrode from signal lines including control signal lines for driving each display panel. A common signal line provided on each display panel by sharing at least a part of the signal line, and the common signal line is shared by each display panel. For communication At least one panel common signal line and a panel individual signal line used to control each display panel individually, and signals supplied to each display panel by the panel individual signal line. Display panel selecting means for selecting according to each display panel is provided.

[0012] According to the above invention, among the signal lines including the control signal line for driving each display panel, at least a part of the signal lines excluding the signal line to the common electrode is shared, and each display is performed. A common signal line is provided for each panel.

Therefore, when driving a plurality of display panels, an increase in the number of signal lines can be suppressed as compared with the case where signal lines are individually arranged on the display panel. As a result, the expansion of the LSI package can be prevented and the associated cost increase can be avoided.

[0014] Note that the signal line to the common electrode cannot be shared, and thus is excluded from the target of the shared signal line.

[0015] By the way, when signal lines including control signal lines to each display panel are shared, signals having the same contents as those used individually for each display panel are commonly used for all display panels. There is a ruby.

Therefore, in the present invention, at least one panel common signal line that is used in common for each display panel and a panel individual signal that is used for individually controlling each display panel are used in the present invention. Categorize into lines! /

That is, when sharing a signal line including a control signal line, considering a plurality of signals supplied to each display panel by the signal line, considering the frequency of the signal and the load applied to the circuit by the signal, They are classified into signals that are separated by the circuit inside each display panel and supplied individually to each display panel, and signals that are directly supplied to multiple display panels without being separated.

In the present invention, among the classified panel common signal lines and panel individual signal lines, the panel individual signal lines used for individually controlling each display panel are provided with display panel selection means. The signal to each display panel supplied by the panel individual signal line is selected according to each display panel.

Therefore, even with the panel individual signal line, the display panel selecting means is provided to provide the display panel. By selecting according to the channel, sharing can be achieved without wiring each display panel individually.

[0020] As a result, it is possible to provide a display device drive circuit that can share signal lines to a plurality of display panels without significantly increasing the number of signal lines.

[0021] In addition, since there is no significant increase in the number of signal lines, there is no restriction on the positional relationship between the plurality of display panels, thereby enabling free product design.

[0022] Further, in order to solve the above problems, the drive circuit of the display device of the present invention provides a video signal line, a scanning signal line, a pixel, a pixel switching element, a common electrode, and a video signal applied to the video signal line. Sampling switching element for turning on and off Z, a first shift register circuit for generating a signal for controlling an on Z off period of the sampling switching element, and an on Z off signal for the pixel switching element to be applied to the scanning signal line A display device driving circuit for driving a plurality of display panels each having a second shift register circuit for generating a control circuit, comprising a control circuit and a shared signal line. Supply various signals to 1 shift register circuit, 2nd shift register circuit, sampling switching element, and common electrode. The use signal lines include the first shift register circuit, the second shift register circuit, and the sampling line except for the signal lines to the common electrode among signal lines including control signal lines for driving each display panel. At least part of the control signal line for the switching element, which is arranged to be branched from the control circuit to one display panel and another display panel, and the common signal line is provided for each display. The drive circuit further includes at least one panel common signal line commonly used in the panel and a panel individual signal line used to individually control each display panel. The drive circuit further includes the panel individual signal line. The display panel selection means is provided to select the signal to each display panel supplied by, according to each display panel.

[0023] According to the above invention, among the signal lines including the control signal line for driving each display panel, at least a part of the signal lines excluding the signal line to the common electrode is shared, and each display is performed. A common signal line is provided for each panel.

[0024] The shared signal line is connected to the first shift in each display panel from the control circuit. A signal line for supplying various signals to the register circuit, the second shift register circuit, the sampling switching element, and the common electrode.

[0025] The common signal line is first arranged from the control circuit to one display panel. The other display panel is branched from the shared signal line disposed on the one display panel.

[0026] Thereby, the first shift register circuit and the second shift register circuit in which the signal lines to the common electrode are excluded from the signal lines including the control signal lines for driving each display panel.

In addition, each control signal line to the sampling switching element can be specifically shared.

[0027] In the present invention, the shared signal line includes at least one panel common signal line that is commonly used in each display panel, and a panel individual signal line that is used to individually control each display panel. Classify into! /

[0029] Accordingly, by providing display panel selection means and selecting according to the display panel for the panel individual signal lines, it is possible to achieve common use without wiring each display panel individually. .

As a result, it is possible to provide a display device drive circuit that can share signal lines to a plurality of display panels without significantly increasing the number of signal lines.

[0031] In addition, since there is no significant increase in the number of signal lines, there is no restriction on the positional relationship between a plurality of display panels, thereby enabling free product design.

[0032] Further, in the drive circuit of the display device of the present invention, the display panel selecting means selects a signal supplied to each display panel through the panel individual signal line according to each display panel. A signal having a selection signal line and supplied by the display panel selection signal line includes a selection signal for time-dividing one horizontal period and assigning the display panel to each display panel. U ヽ who prefers to talk. [0033] With this, the display panel selection means uses the display panel selection signal line that supplies a selection signal for displaying each display panel by allocating the display panel to each display panel in a time-divided manner within one horizontal period. Can be configured. Therefore, the display panel selection means can be configured easily.

In the display device drive circuit of the present invention, when the selection signal is assigned to each display panel by dividing the time within one horizontal period to display each display panel, Preferably, it consists of signals that assign other display panels during the horizontal blanking period of the display panel.

[0035] Thereby, when another display panel is displayed, the other display panel is allocated during the horizontal blanking period of one display panel, so that the other display panel can be displayed. Will not be affected.

By the way, when the signal to the common electrode of each display panel changes, if the sampling switching element force video signal sampling operation of each display panel is performed, the display may be disturbed.

Therefore, in the driving circuit of the display device of the present invention, it is preferable that each sampling switching element does not perform the sampling operation of the video signal when the signal to the common electrode changes.

[0038] This allows signal lines to be shared while ensuring display quality by temporarily suspending the drive operation that is periodically performed during a period in which multiple display panels are affected by each other. It becomes. In addition, unnecessary time elements can be reduced by performing operations that may be performed simultaneously on a plurality of display panels, except during the affected period.

[0039] When the pixel switching elements in the display panels are turned on and off, the display may be disturbed if the sampling switching elements perform a video signal sampling operation.

Therefore, in the driving circuit of the display device of the present invention, when the pixel switching element is changed from on to off, each sampling switching element does not perform the sampling operation of the video signal, and the video signal is at a certain level. It is preferable to fix to. In addition When the video signal is fixed at a certain level, any gradation level may be selected as the above-mentioned constant level, and the video is always turned on when the pixel switching element is changed to on-off during display. There is no problem if the signal is fixed at a certain level.

[0041] In this way, signal lines can be shared while ensuring display quality by temporarily suspending the drive operation that is being performed periodically during the period that multiple display panels are affected by each other. It becomes. In particular, when voltage fluctuation occurs due to capacitive coupling, it can equally affect the voltage fluctuation of each pixel. That is, it is possible to prevent voltage fluctuations having different degrees of influence from occurring randomly.

[0042] In the display device drive circuit of the present invention, it is preferable that the front display panel selection unit performs control to turn off some of the display panels.

[0043] Thereby, some of the plurality of display panels can be turned off, so that power consumption can be suppressed. It is also possible to cope with various operations such as simultaneous display of a plurality of display panels and single display.

[0044] In the display device drive circuit of the present invention, it is preferable that each of the plurality of display panels is driven in a dot-sequential manner.

[0045] This helps to reduce the chip size and thus reduce the cost while inheriting the original merit of the dot sequential driving method. In addition, for example, a portable device having a plurality of display panels can be provided with a low-cost and highly reliable point sequential driving method, and a plurality of disadvantages associated with the common use of signal lines in the line sequential driving method. By eliminating the restrictions on the position of the display panels, it is possible to design products freely.

In addition, the display device of the present invention includes the drive circuit in order to solve the above problems.

[0047] Thus, it is possible to provide a display device including a display device drive circuit capable of sharing signal lines to a plurality of display panels without causing a decrease in display quality without excessively increasing the number of signal lines. it can.

[0048] Other objects, features, and advantages of the present invention will be fully understood from the following description. The advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. Brief Description of Drawings

FIG. 1 is a block diagram showing an embodiment of a drive circuit for a display device according to the present invention.

FIG. 2 is a timing chart showing a driving method in the driving circuit of the display device.

FIG. 3 is a timing chart showing sampling pulses generated by a first shift register circuit which is a shift register for generating an on-Z-off signal of a sampling switching element in the driving circuit of the display device.

FIG. 4 is a timing chart showing a scanning line signal created by a second shift register circuit that is a scanning line signal creation shift register in the driving circuit of the display device.

FIG. 5 shows a driving operation in which the sampling switching element of each display panel does not perform the sampling operation of the video signal during the period when the signal to the common electrode of each display panel changes in the driving circuit of the display device. It is a timing chart.

FIG. 6 is a timing chart showing sampling pulses generated at the timing shown in FIG.

[FIG. 7] In the driving circuit of the above display device, when the pixel switching element changes to on-off, the sampling switching element of each display panel does not perform the sampling operation of the video signal, and the video signal is at a certain level. 6 is a timing chart showing a driving operation fixed to the position.

FIG. 8 is a timing chart showing sampling pulses created at the timing shown in FIG.

FIG. 9 is a block diagram showing still another embodiment of a drive circuit for a display device according to the present invention.

FIG. 10 is a block diagram showing a configuration of a driving circuit of a conventional display device.

FIG. 11 is a timing chart showing a driving operation of the driving circuit of the conventional display device.

FIG. 12 is a block diagram showing a configuration of a drive circuit of another conventional display device.

FIG. 13 is a timing chart showing various signals in the case where display is performed on two display panels in the drive circuit shown in FIG. 9.

[FIG. 14] In the drive circuit shown in FIG. 9, one of the two display panels is in a non-display state. It is a timing chart which shows the various signals in the case.

Explanation of symbols

la 1st panel (display panel)

lb Second panel (display panel)

2 Video signal line

3 Scanning signal line

4 pixels

5 TFT (pixel switching element)

6 Common electrode

7 Sampling switching element

8 First shift register circuit

9 Second shift register circuit

10 Drive circuit

11 Gate circuit (display panel selection method)

12 Panel drive circuit (control circuit)

SEL panel selection signal (selection signal)

BEST MODE FOR CARRYING OUT THE INVENTION

[0051] An embodiment of the present invention will be described below with reference to Figs.

A drive circuit 10 (hereinafter simply referred to as “drive circuit 10”) of a liquid crystal display device as a display device of the present embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of the drive circuit 10, and FIG. 2 is a timing chart showing the drive method of the drive circuit 10.

As shown in FIG. 1, the drive circuit 10 includes a first panel la and a second panel lb as a plurality of display panels. In the present embodiment, there are two display panels. However, the present invention is not limited to this, and a plurality of display panels can be used.

[0054] The first panel la and the second panel lb have a video signal line 2, a scanning signal line 3, a pixel 4, and a TFT (Thin Film Transistor) as a pixel switching element, respectively. 5) Sampling switching element 7 that turns on and off the video signal applied to the common electrode 6 and the video signal line 2, and a first shift register circuit 8 that creates a signal that controls the on / off period of the sampling switching element 7 8 In addition, a second shift register circuit 9 and a gate circuit 11 for generating an on-Z off signal of the TFT 5 to be applied to the scanning signal line 3 are provided.

The drive circuit 10 is provided with a panel drive circuit 12 as one control circuit, for example, for driving the first panel la and the second panel lb. In the present embodiment, since the two first panels la and the second panel lb are provided, one panel drive circuit 12 is provided. If the display panel is provided, the panel drive circuit 12 may be plural.

[0056] From the panel drive circuit 12, for each of the first panel la and the second panel lb, a video signal, a scanning line signal pulse width control signal GOE, a start signal GSP of the second shift register circuit 9, Common to the clock signal GCK of the second shift register circuit 9, the start signal SSP of the first shift register circuit 8, the clock signal SCK of the first shift register circuit 8, the panel selection signal SEL as the selection signal, and the first panel la The common electrode signal COM1 to the electrode 6 and the common electrode signal COM2 to the common electrode 6 of the second panel lb are output.

[0057] The video signal has three types of signal strengths of red (R) 'green (G) · blue (B).

Further, the scanning line signal pulse width control signal GOE, the start signal GSP of the second shift register circuit 9, the clock signal GCK of the second shift register circuit 9, and the start signal SSP of the first shift register circuit 8, The clock signal SCK of the first shift register circuit 8 is supplied to each of the first panel la and the second panel lb by a control signal line.

[0059] In the drive circuit 10 of the present embodiment, among the signal lines necessary for driving the first panel la and the second panel lb, the signal lines excluding the common electrode signal line are shared. Furthermore, by using the panel selection signal SEL, a part of the shared signal line is separated as a panel individual signal line for individually driving the first panel la and the second panel lb. On the other hand, at least one of the shared signal lines is used as a panel common signal line in a plurality of first panels la and second panels lb. That is, the shared signal line is separated into a panel individual signal line and a panel common signal line by using the panel selection signal SEL.

That is, in the present embodiment, among the signal lines including the control signal lines for driving the first panel la and the second panel lb, the COM 1 signal line 'COM2 signal line to the common electrode 6 is used. The control signal lines, video signal lines, and panel selection signals for supplying the panel selection signal SEL to the first shift register circuit 8, the second shift register circuit 9, and the sampling switching element 7 are removed. The panel drive circuit 12 branches from the first panel la and the second panel lb to a common signal line.

[0062] In addition, the common signal line includes at least one common panel signal line commonly used for each first panel la and second panel lb, and each first panel la and second panel lb. It consists of panel individual signal lines used for control.

[0063] The panel common signal line includes, for example, a video signal line for supplying a video signal to the sampling switching elements 7 of the first panel la and the second panel lb, and each of the first panel la and the second panel lb. GSP control signal that supplies the start signal GSP to the second shift register circuit 9 GSP control signal line that supplies the clock signal GCK for the scanning line signal line to each second shift register circuit 9 of the first panel la and the second panel lb This corresponds to at least one of the SCK control signal lines for supplying the video signal line clock signal SCK to the first shift register circuits 8 of the first panel la and the second panel lb.

Note that the video signal, the start signal GSP, the scanning line signal line clock signal GCK, and the video signal line clock signal SCK are common signals supplied to a plurality of panels at the same time. Of the various signals output by the circuit 12, the signal belongs to the first signal described in “Claims”.

The panel individual signal lines include, for example, a GOE control signal line that supplies a scanning line signal pulse width control signal GOE to the gate circuits 11 of the first panel la and the second panel lb, and the first panel la. The SSP control signal line for supplying the start signal SSP to the gate circuits 11 of the second panel lb and the SEL control signal line for supplying the panel selection signal SEL to the gate circuits 11 of the first panel la and the second panel lb. Is applicable.

Note that the scanning line signal pulse width control signal GOE and the start signal SSP Of the various signals output by the drive circuit 12, it belongs to the second signal described in “Claims”.

[0067] Also, one of the two gate circuits 11 includes a first NAND gate configured to input an inverted signal of the scanning line signal pulse width control signal GOE and a panel selection signal SEL, and a start signal SSP. A second NAND gate configured to receive the inversion signal and the panel selection signal SEL; Further, the other of the two gate circuits 11 inputs the lOR gate configured to input the scanning line signal pulse width control signal GOE and the panel selection signal SEL, the start signal SSP, and the panel selection signal SEL. And a second OR gate configured to do so.

[0068] Thus, the two gate circuits 11 are display panel selection means provided with individual panel signal lines (SEL control signal lines) on the signal input side for simultaneously receiving the second signals. Thus, the second signal supplied to each of the plurality of display panels functions as a display panel selecting means for selecting according to the display panel to be driven.

In FIG. 1, the force gate circuit 11 showing the circuit layout as if the gate circuit 11 was built in each panel may be provided corresponding to each panel. You can change the layout freely.

A driving method in the driving circuit 10 of the liquid crystal display device having the above configuration will be described with reference to FIGS. FIG. 2 shows a scanning line signal pulse width control signal GOE and a start signal SSP output from the panel drive circuit 12, and a scanning line signal pulse width control signal GOE1 'GOE2 after being separated using the panel selection signal SEL, and 3 is a timing chart showing start signals SSP1 to SSP2 of the first shift register circuit 8. FIG. Note that the start signal GSP of the second shift register circuit 9 is not shown.

[0071] As shown in FIG. 2, the scanning line signal pulse width control signal GOE simultaneously output to the gate circuits 11 of the first panel la and the second panel lb by the GOE control signal line is the panel selection signal SEL. It is divided into two types of scanning line signal pulse width control signals GOE1 and GOE2 with different pulse edge timings.

More specifically, the operation of the first NAND gate causes the scan for the first panel la from the inverted signal of the scanning line signal pulse width control signal GOE and the panel selection signal SEL. The winding signal pulse width control signal GOE 1 is generated. Further, by the operation of the first OR gate, the scanning line signal pulse width control signal GOE2 is generated for the second panel lb from the scanning line signal pulse width control signal GOE and the panel selection signal SEL. The scanning line signal pulse width control signals GOE1 and GOE2 are supplied to the second shift register circuit 9 of the first panel la and the second panel lb, respectively. The frequency of the scanning line signal pulse width control signals GOE1 and GOE2 is equal to the horizontal frequency.

[0073] Similarly, as shown in FIG. 2, the start signal SSP simultaneously output to the gate circuits 11 of the first panel la and the second panel lb by the SSP control signal line is generated by the panel selection signal SEL. By using this, two types of start signals SSP1 and SSP2 with different pulse edge timing can be separated.

More specifically, by the operation of the second NAND gate, the start signal SSP1 is generated for the first panel la from the inverted signal of the start signal SSP and the panel selection signal SEL. Further, the start signal SSP2 is generated for the second panel lb by the operation of the 20th R gate for the start signal SSP, the panel selection signal SEL, and the force. The start signals SSP1 and SSP2 are supplied to the first shift register circuit 8 of the first panel la and the second panel lb, respectively. The frequency of the start signals SSP1 and SSP2 is equal to the horizontal frequency.

FIG. 3 is a diagram showing each signal of the first shift register circuit 8 which is a shift register for generating an on-Z-off signal of the sampling switching element 7, and FIG. 4 shows each signal of the second shift register circuit 9. FIG.

For example, when the start signal SSP1 is input to the first shift register circuit 8 of the first panel la, as shown in FIG. 3, the first shift register circuit 8 generates a clock signal as the shared signal. The first panel sampling nors synchronized with SCK are output one after another. By this first panel sampling pulse, the sampling switching element 7 provided in the first panel la is turned on in order, and the video signals (R, G, B) are sequentially sent to the video signal line 2 of the first panel la. It is captured.

[0077] In exactly the same manner, video signals (R, G, B) are sequentially taken into the video signal line 2 of the second panel lb. However, the start signal SSP2 is different from the start signal SSP1. Since the video signal is output, the timing at which the video signal is taken into the video signal line 2 is different between the first panel la and the second panel lb. More specifically, the period during which the video signal is taken into the video signal line 2 in the second panel lb is included in the horizontal blanking period of the first panel 1a, as shown in FIGS.

That is, in FIG. 2, the period during which the video signal for the first panel la is not captured in one horizontal period (one horizontal period) is the horizontal blanking period of the first panel la. The period during which the video signal for 2 panel lb is not captured is the horizontal blanking period for 2 panel lb. Therefore, the panel selection signal SEL functions as a selection signal for displaying each display panel la ′ lb by assigning it to each display panel la ′ lb in a time division manner within one horizontal period. In other words, when the panel selection signal SEL is time-divided within one horizontal period and assigned to each display panel la ′ lb to display each display panel la ′ 1 b, the horizontal selection of one display panel is performed. Functions as a signal to assign the other display panel during the ranking period.

On the other hand, for example, when the start signal GSP as the shared signal is input to the second shift register circuit 9 of the first panel la, as shown in FIG. 4, the second shift register circuit 9 The first shift pulse 1, the first shift pulse 2, etc. synchronized with the clock signal GCK as the common signal are output one after another. The first panel scan line signal is generated by the second shift register circuit 9 as the logical product of the first shift pulse 1, the first shift pulse 2 and the like and the scan line signal pulse width control signal GOE1, and the scan signal Output to line 3.

In exactly the same manner, the second panel scanning line signal is output to the scanning signal line 3 of the second panel lb. However, since the scanning line signal pulse width control signal GOE2 is output at a timing different from that of the scanning line signal pulse width control signal GOE1, the first panel scanning line signal and the second panel scanning line signal are sent to each scanning signal line 3. The output timing differs between the first panel la and the second panel lb.

[0081] As shown in FIGS. 2 to 4, the signals (GOE and SSP) individually supplied to the first panel la and the second panel lb using the panel selection signal SEL have a relatively low frequency. Since few circuits are connected, the load on the circuit is light. Accordingly, the circuit for separating the first panel la and the second panel lb, that is, the gate circuit 11 can be made small. On the other hand, there are many circuits in which signals (clock signal GCK and clock signal SCK, etc.) used directly in both the first panel la and the second panel lb are connected with relatively high frequencies. For this reason, it is difficult to separate the first panel la and the second panel lb.

[0083] Note that the start signal GSP of the second shift register circuit 9 is not separated. If the start signal GSP is separated, the display system sends various signals to the other panel during the vertical blanking period. . In this case, since the cycle of refreshing the display screen becomes longer, the display quality is lowered.

Therefore, in the present embodiment, the start signal SSP1′SSP2 of the first shift register circuit 8 and the scanning line signal pulse width control signals GOE1 and GOE2 of the second shift register circuit 9 are separated. On the basis of the same video signal line clock signal SCK and scanning line signal line clock signal GCK, the plurality of first shift register circuits 8 and second shift register circuits 9 can be operated at different timings.

Note that the number of clocks included in the pulse interval of the start signal SSP before the separation needs to be equal to or greater than the number of stages of the first shift register circuit 8. More specifically, as shown in FIG. 2, the number of clocks included in the pulse interval T1 of the start signal SSP corresponding to the supply period of the video signal to the first panel la is provided in the first panel la. The number of stages of the first shift register circuit 8 must be greater than or equal to. In addition, the number of clocks included in the noise interval T2 of the start signal SSP corresponding to the video signal supply period to the second panel lb is equal to or greater than the number of stages of the first shift register circuit 8 provided in the second panel lb. There is a need. This is because the video signal line is shared, for example, the first shift register circuit 8 provided in the second panel lb is shifted in the first shift register circuit 8 provided in the first panel la. Because it must start after reaching the last stage of force.

FIG. 5 is a timing chart when the SCK signal is made discontinuous at the COM signal change timing and the operation of the first shift register circuit 8 is temporarily stopped, and FIG. 6 shows the sampling pulse at that time. It is an example of a production | generation state.

[0087] The COM signal change timing is a timing at which the reference level of many loads changes, and generally a large current flows. If the sampling operation is continued at this timing, the internal state of the first panel la and the second panel lb will change to other timing due to the large current flowing. May be different. Display quality can be maintained by temporarily suspending sampling at the timing when a large current flows, and restarting the power after the current has ended.

[0088] When a single panel is driven, in general, the COM signal is not changed during the sampling period. However, when driving multiple panels, for example, it is inevitable that a change in the COM signal of another panel will occur during the sampling operation of one panel, so the operation is temporarily suspended to maintain the quality.

[0089] Figure 7 shows that the video signal is kept at a constant level in accordance with the change (falling) of the scan line signal pulse width control signal GOE that determines the pulse width of the scan line signal that controls the on / off of TFT5. FIG. 8 is a timing chart showing the control for stopping the sampling operation by discontinuating the video signal line clock signal SCK while maintaining A ”, and FIG. 8 shows the scanning line signal pulse width control signal GOE1 supplied to each panel la 'lb. · An example showing the relationship between GOE2 and sampling norms.

[0090] The time when the scanning line signal pulse width control signal GOE changes is an important time when the pixel charging voltage is determined. On the other hand, inside the panels of the first panel la and the second panel lb, various signal voltage changes influence each other due to various capacitive couplings.

[0091] The video signal line shared for each panel of the first panel la and the second panel lb is, for example, a video of another second panel lb when the video signal sampling operation of the first panel la is completed. A signal is being supplied. On the other hand, for example, the TFT5 off timing of the first panel la after the sampling operation is completed is set after a certain time has elapsed since the completion of the sampling. This is a force that depends on the on-resistance of TFT5, and is generally set after a sampling force of several microseconds. During this period, video signals from multiple panels cannot be transmitted efficiently through a common video signal line unless another 2nd panel lb video signal is supplied.

Therefore, as described above, the video signal of another second panel lb is supplied to the video signal line at the TFT 5 off timing.

[0093] The above point will be described more specifically below. When the sampling operation is completed, for example, the TFT5 off timing of the first panel la coincides with the falling edge of the first panel scanning line signal as shown in FIG. 4, for example, and as described above, the scanning line signal pulse width control is performed. Signal GO It coincides with the fall of El. As shown in FIG. 8, the TFT5 OFF timing is after a certain time has elapsed from the output timing of the last first panel sampling nors in one horizontal period. Further, at the TFT5 off timing, as shown in FIG. 8, the second panel sampling pulse is output, so that the video signal of the second panel lb is supplied to the video signal line.

[0094] The video signal line and the video signal line are connected and disconnected by turning on and off the sampling switching element 7. However, since the video signal line and the video signal line are capacitively coupled to the sampling switching element 7, the video signal line is affected by a change in the voltage of the video signal line even during the interruption. The voltage applied to the pixel is determined by the video signal line voltage when TFT5 is off-timing. If the video signal line voltage is constant, the effect of capacitive coupling is constant. However, if the video signal voltage is not constant and indefinite, the effects of capacitive coupling are inconsistent! The pixel applied voltage is not stable.

[0095] Therefore, the video signal line is efficiently shared by keeping the voltage of the video signal line constant (the above level "A") and stopping the sampling operation only at the timing when TFT5 is turned off. It becomes possible to do.

[0096] In the present embodiment, the drive circuit 10 selects! Or shift between the first panel la and the second panel lb by the panel selection signal SEL! It is not limited to this.

[0097] For example, FIG. 9 shows a configuration example in which the start signal GSP of the second shift register circuit 9 is divided and supplied separately to the start signal GSP1 for the first panel la and the start signal GSP2 for the second panel lb. It is. In addition to displaying all the panels in the first panel la and the second panel lb at the same time by having a means for supplying the start signal GSP for each panel, only one first panel la, for example, is displayed. can do. Further, it is possible to hide only one, for example, the first panel la, thereby reducing power consumption.

[0098] Timing charts in that case are shown in FIGS. FIG. 13 shows a case where the panel driving circuit 12 outputs the start signal GSP1 and the start signal GSP2 separately to cause both the first panel la and the second panel lb to perform display. 1st panel scan The operation for generating the line signal and the second panel scanning line signal is the same as the operation already described with reference to FIG. However, in FIG. 13, the output timings of the forces shown in the example in which the output timings of the start signal GSP1 and the start signal GSP2 are shifted as in FIG. 4 may be aligned at the same time. This is because the start signal GSP1 and the start signal GSP2 are output separately, so that the video signal writing to the first panel la and the second panel lb can be made independent.

On the other hand, FIG. 14 shows a case where the panel driving circuit 12 outputs only the start signal GSP1, thereby causing only the first panel la to perform display. As described above, if the panel drive circuit 12 does not output the start signal GSP2, the second shift pulse is not generated in the second shift register circuit 9, so that the second panel scanning line signal is not generated. As a result, the display of the second panel lb can be paused.

[0100] When the first panel la and the second panel lb are not displayed at the same time, for example, the pulse to be supplied to the non-display second panel lb is deleted in the signal separated by the panel selection signal SEL. As a result, the power consumption of the non-display panel can be further reduced. Even in this configuration, when a plurality of first panels la and second panels lb are displayed simultaneously, it is effective to ensure display quality by operating at the timings shown in FIGS.

[0101] It is to be noted that the force required to synchronize the video signals for the first panel la and the second panel lb in creating these timings is not particularly defined.

As described above, the drive circuit 10 according to the present embodiment includes the COM 1 signal to the common electrode 6 among the signal lines including the control signal lines for driving the first panel la and the second panel lb. Lines · Each signal line excluding the COM2 signal line is shared, and each shared signal line is provided in the first panel la and the second panel lb, respectively. In the present invention, it is not always necessary to use all of these as common signal lines!

[0103] Therefore, when driving the plurality of first panels la and second panels lb, the shared signal lines that share the respective signal lines are arranged on the respective display panels. The increase in the number of signal lines can be minimized as compared with the case where the number of signal lines is individually provided. This also prevents the expansion of LSI packages and avoids the associated cost increase. can do.

[0104] Note that the COM1 signal line 'COM2 signal line to the common electrode 6 cannot be shared, so it is excluded from the target of each shared signal line.

[0105] By the way, when signal lines including control signal lines to the first panel la and the second panel lb are shared, the same contents as those used individually for the first panel la and the second panel lb. There are some signals that are commonly used by all first panel la and second panel lb.

Therefore, in the present embodiment, each shared signal line includes at least one panel common signal line used in common for the first panel la and the second panel lb, and the first panel la and the second panel. It is classified into the panel individual signal line used to control lb individually.

[0107] That is, when sharing the signal line including the control signal line, considering the frequency of the signal and the load of the signal, the signal separated by the circuits inside the first panel la and the second panel lb (panel individual Signal) and signals that are supplied directly to multiple display panels without being separated (panel common signals).

In this embodiment, among the classified panel common signal line and panel individual signal line, the panel individual signal line is provided with the SEL control signal line and supplied by the panel individual signal line. Each signal to the first panel la and the second panel lb is selected according to the first panel la and the second panel lb.

Therefore, the panel individual signal lines can also be shared without being individually wired to the first panel la and the second panel lb.

As a result, it is possible to provide the drive circuit 10 that can share the signal lines to the plurality of first panels la and the second panel 1 b without excessively increasing the number of signal lines.

[0111] In addition, since there is no significant increase in the number of signal lines, there is no restriction on the positional relationship between the multiple first panels la and the second panel lb, enabling free product design. Become.

Further, in the present embodiment, each shared signal line is specifically connected from the panel drive circuit 12 to the first shift register circuit 8 and the second shift register in the first panel la and the second panel lb. This is a signal line that supplies various signals to the star circuit 9, the sampling switching element 7, and the common electrode 6. Each of the shared signal lines is first arranged from the panel drive circuit 12 to one, for example, the first panel la. The second panel lb is branched from each shared signal line disposed on the first panel la.

[0114] Thus, the first shift register excluding the COM1 signal line 'COM2 signal line to the common electrode 6 among the signal lines including the control signal line for driving the first panel la and the second panel lb. The control signal lines to the circuit 8, the second shift register circuit 9, and the sampling switching element 7 can be shared.

In the drive circuit 10 of the present embodiment, each shared signal line has at least one panel common signal line that is commonly used in each display panel. This panel common communication line includes, for example, a video signal line, a GSP start signal line for the second shift register circuit 9, a clock signal line for the GCK scanning line signal line, and an SSP start signal for the first shift register circuit 8. Is a line.

[0116] This makes it possible to share at least one panel common signal line that is used in common by the first panel la and the second panel lb.

[0117] Also, in the driving circuit 10 of the present embodiment, for example, when displaying the second panel lb, the second panel lb is assigned to the horizontal blanking period of the first panel la, so that the second panel lb When displaying, the display on the display panel of the first panel la is not affected.

[0118] When the signal applied to the common electrode 6 of the first panel la and the second panel lb changes, the display may be disturbed if the sampling switching element 7 performs the sampling operation of the video signal.

[0119] Therefore, in the drive circuit 10 of the present embodiment, when the signal applied to the common electrode 6 of the first panel la and the second panel lb changes, the sampling switching element 7 performs the video signal sampling operation. U, who likes to be done.

[0120] As a result, the timing that is affected by the mutual effects of the plurality of the first panel la and the second panel lb can ensure the display quality by temporarily stopping the drive operation that is periodically performed. However, the signal lines can be shared. In addition to the affected timing, perform operations that may be performed simultaneously on multiple first panel la and second panel lb. As a result, a wasteful time factor can be reduced.

[0121] At the time when the TFT 5 in the first panel la and the second panel lb is turned on, the sampling switching element 7 in the first panel la and the second panel lb performs the sampling operation of the video signal. The display may be distorted.

Therefore, in the present embodiment, it is preferable that the sampling switching element 7 does not perform the sampling operation of the video signal and fixes the video signal at a certain level at the above time. Note that when fixing the video signal to a certain level, it does not matter which gradation level is selected as the above-mentioned constant level, and the video signal is always fixed at a certain level at the above-mentioned time point during display. Then there will be no problem.

[0123] As a result, the timing that is affected by the mutual effects of the plurality of first panels la and the second panel lb ensures the display quality by temporarily stopping the driving operation that is periodically performed. However, the signal lines can be shared. In particular, in the present embodiment, when the TFT 5 is turned on, the sampling switching element 7 does not perform the video signal sampling operation and keeps the video signal fixed at a certain level. Thus, for example, when voltage fluctuations due to capacitive coupling occur, the voltage fluctuations of each pixel can be equally affected. That is, it is possible to prevent voltage fluctuations having different degrees of influence from occurring randomly.

[0124] Also, in the drive circuit 10 of the present embodiment, some of the first panel la and the second panel lb, for example, the first panel la can be turned off by the panel selection signal SEL. Power consumption can be reduced. It is also possible to cope with various operations such as simultaneous display or single display of a plurality of first panels la and second panels lb.

[0125] Further, it is preferable that the driving circuit 10 of the present embodiment is driven in a dot sequential manner.

[0126] This is useful for reducing the chip size and thus reducing the cost while inheriting the original merit of the dot sequential driving method. In addition, for example, portable devices equipped with a plurality of first panels la and second panels lb enable a low-cost, high-reliability point-sequential drive system, and the disadvantages of using a line-sequential drive system for signal lines in common. This eliminates the restrictions on the positional relationship of multiple display panels, which enables free product design.

In addition, the liquid crystal display device of the present embodiment includes the drive circuit 10 described above. This As a result, a drive circuit 10 that can share signal lines to a plurality of first panel la and second panel lb without causing a decrease in display quality without excessively increasing the number of signal lines, and a display having the same An apparatus can be provided.

[0128] The specific embodiments or examples made in the detailed description section of the invention are to clarify the technical contents of the present invention, and are limited only to such specific examples. Therefore, the present invention should not be construed in a narrow sense, and can be implemented within the spirit of the present invention and the scope of the following claims!

Industrial applicability

The present invention can be applied to a drive circuit for a display device driven by an active matrix having a plurality of display panels, and a display device. Specifically, as a display device, for example, it can be used in an active matrix type liquid crystal display device used for a mobile phone, and an electrophoretic display, a twist ball display, a reflective type using a fine prism film. In addition to displays using light modulation elements such as displays and digital mirror devices, as light-emitting elements, organic EL light-emitting elements, inorganic EL light-emitting elements, and LEDs (Light Emitting Diodes) and other elements with variable emission luminance were used It can also be used for displays.

Claims

The scope of the claims

[1] Video signal line, scanning signal line, pixel, pixel switching element, common electrode, sampling switching element for turning on / off the video signal applied to the video signal line, and controlling on / off period of the sampling switching element A drive circuit for a display device that drives a plurality of display panels including a first shift register circuit that generates a signal and a second shift register circuit that generates an on-Z-off signal of the pixel switching element to be applied to the scanning signal line; There,

Among the signal lines including the control signal lines for driving each display panel, at least a part of the signal lines excluding the signal lines to the common electrode are shared, and the common signal is arranged in each display panel. With lines,

The common signal line is composed of at least one panel common signal line commonly used in each display panel and a panel individual signal line used for individually controlling each display panel.

A drive circuit of a display device provided with display panel selection means for selecting a signal supplied to each display panel through the panel individual signal line according to each display panel.

[2] Video signal line, scanning signal line, pixel, pixel switching element, common electrode, sampling switching element for turning on / off the video signal applied to the video signal line, and controlling on / off period of the sampling switching element A drive circuit for a display device that drives a plurality of display panels including a first shift register circuit that generates a signal and a second shift register circuit that generates an on-Z-off signal of the pixel switching element to be applied to the scanning signal line; There,

A control circuit;

With a common signal line,

The control circuit supplies various signals to the first shift register circuit, the second shift register circuit, the sampling switching element, and the common electrode in each display panel, and

The common signal line includes the first shift register circuit and the second shift register signal lines including the control signal line for driving each display panel, excluding the signal line to the common electrode. At least part of the control signal line for the register circuit and the sampling switching element, and is branched from the control circuit to one display panel and another display panel,

Further, the common signal line is composed of at least one panel common signal line commonly used for each display panel and a panel individual signal line used for individually controlling each display panel.

The drive circuit further includes display panel selection means for selecting a signal for each display panel supplied by the panel individual signal line according to each display panel. Driving circuit.

[3] The display panel selection means has a display panel selection signal line for selecting a signal supplied to each display panel through the panel individual signal line according to each display panel, and the display panel selection signal line 3. The display according to claim 1, wherein the supplied signal includes a selection signal for allocating to each display panel in a time-divided manner within one horizontal period and displaying each display panel individually. Device drive circuit.

[4] The selection signal assigns another display panel to the horizontal blanking period of one display panel when time-divided within one horizontal period and assigned to each display panel to display each display panel. 4. The display device drive circuit according to claim 3, wherein the display device drive circuit comprises a signal.

5. The sampling switching element of each display panel does not perform a video signal sampling operation when a signal applied to the common electrode of each display panel changes. The drive circuit for the display device according to item 1.

[6] When the pixel switching element is changed to the off-state, the sampling switching element of each display panel does not perform the sampling operation of the video signal and fixes the video signal to a certain level. A drive circuit for a display device according to any one of claims 1 to 5.

[7] The display device according to any one of [1] to [6], wherein the front display panel selection unit performs control to turn off some of the plurality of display panels. Drive circuit.

8. Each of the plurality of display panels is dot-sequentially driven.

8. The display device driving circuit according to any one of 7 above.

[9] A display device driving circuit for controlling a display state of a display device including a plurality of display panels having a plurality of pixels by controlling supply of signals to the pixels, A panel communication line for simultaneously supplying one signal to the plurality of display panels;

Of the above signals, display panel selection means provided on the signal input side with panel individual signal lines for simultaneously receiving the second signal, and driving the second signal supplied to each of the plurality of display panels. Display panel selection means for selecting according to the display panel to be displayed, and a display device drive circuit comprising:

10. The drive circuit according to claim 9, wherein the drive circuit causes the display panel selection unit to select a display panel that supplies the second signal by supplying a panel selection signal to the display panel selection unit. A driving circuit of the display device.

[11] A display device comprising the drive circuit for the display device according to any one of claims 1 to 10.