JPH113270A - Flash memory unit and method for writing data to flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably write data to a flash memory at a high speed. SOLUTION: Data are written to respective physical sector numbers of a flash memory 6 corresponding to plural logical sector numbers for which write is requested by a host computer. A controller 1 successively generates a data elimination instruction of the physical sector number corresponding to the logical sector number to be processed next to the logical sector number, and also generates a data write instruction to the physical sector number corresponding to the logical sector number for the respective plural logical sector numbers with the write request. In response to the above, the flash memory 6 parallelly executes the data elimination of the physical sector number corresponding to the logical sector number to be processed next to the logical sector number and also executes the data write to the physical sector number corresponding to the logical sector number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash memory device, and more particularly, to a flash memory device having a plurality of flash memory chips.

[0002]

2. Description of the Related Art As a conventional flash memory device, for example, there is one disclosed in Japanese Patent Application Laid-Open No. Hei 5-27924.

Hereinafter, a conventional flash memory device will be described.

FIG. 18 is a schematic configuration diagram of a conventional flash memory device.

Here, reference numeral 2 denotes an address conversion table storage unit, reference numeral 3 denotes a sector management table storage unit, reference numeral 4 denotes an address decoder, reference numeral 5 denotes a data control unit, reference numeral 7 denotes a controller, and reference numeral 8 denotes a flash memory.

The address conversion table storage unit 2 stores an address of a sector data requested to be written by the host computer (hereinafter referred to as a logical sector number) and a write destination address of the sector data to the flash memory 8 (hereinafter referred to as a physical address). (Referred to as a sector number).

[0007] For each physical sector of the flash memory 5, the sector management table storage section 3 is "unused" when data is not written in the sector, "valid" when necessary data is written, If data is written but the data is not necessary, a table indicating the use status of each physical sector is stored, such as "invalid".

[0008] The controller 7 controls the components of the flash memory device shown in FIG.

FIG. 19 is a schematic functional block diagram of the controller shown in FIG.

[0010] As shown in FIG.
Physical sector number search / decision unit 71 and table change unit 7
2, an instruction generation unit 73, and a data transmission / reception unit 74.

The physical sector number search / determination section 71 refers to the tables stored in the address conversion table storage section 2 and the sector management table storage section 3 and writes the physical data as the write destination of the sector data requested to be written. Determine the sector number.

The table change unit 72 updates the contents of the tables stored in the address conversion table storage unit 2 and the sector management table storage unit 3 according to the result of the physical sector number search / determination unit 71.

The instruction generation unit 73 searches for a physical sector number.
A predetermined command is generated according to the usage status of the physical sector number determined by the determining unit 71.

The data transmission / reception unit 74 receives a write request sent from the host computer and sector data requested by the request. Then, the received data and the command generated by the command generation unit 73 are sent to the data control unit 5. The address signal including the physical sector number determined by the physical sector number search / determination section 71 is sent to the address decoder 4.

The address decoder 4 decodes an address signal sent from the controller 7 and generates an address / memory selection signal including an address in each chip constituting the flash memory 8 and a chip selection signal.

The data control unit 5 transfers commands and sector data sent from the controller to the flash memory 8.

The flash memory 8 is composed of a plurality of memory chips.

Next, the operation of the conventional flash memory device shown in FIG. 18 will be described.

FIG. 20 is a flow chart for explaining the operation of the flash memory device shown in FIG.

First, when the host computer issues a write request to the flash memory device, the controller 7 transmits the logical start sector number transmitted from the host computer by the data transmitting / receiving section 74 and data indicating the number of write sectors. Receiving (step 2001).

Here, the logical start sector number is the logical sector number of the sector data to be written first among the logical sector numbers of the sector data for which the host computer has made a write request.

Next, the controller 7 causes the physical sector number search / determination section 71 to select, from among the logical sector numbers of the sector data for which the host
The physical sector number associated with the logical sector number of interest (initial logical start sector number) is obtained from the table stored in the address conversion table storage unit 2 (step 2002).

Then, the usage status of the obtained physical sector number is obtained from the table stored in the sector management table storage unit 3 (step 2003).

Next, the controller 7 uses the physical sector number search / determination section 71 to determine whether or not the use status obtained in step 2003 is "unused" (step 20).
04).

In the case of "unused", the sector specified by this physical sector number is determined as a physical sector in which sector data is to be written, and the process proceeds to step 2009.

On the other hand, if it is not “unused”, the process proceeds to step 2005, and a physical sector number whose use status is “unused” is searched from the table stored in the sector management table storage unit 3.

If a physical sector number whose use status is "unused" can be detected, the sector specified by the physical sector number is determined as a physical sector in which sector data is to be written, and the process proceeds to step 2009. I do.

On the other hand, if the physical sector number whose use status is “unused” cannot be detected, step 2002
The physical sector number obtained in (1) is determined as the physical sector in which the sector data is to be written, and the process proceeds to step 2007 (step 2006).

In steps 2007 and 2008, the data written to the physical sector number determined by the physical sector number search / determination section 71 is erased.

First, the controller 7 executes step 200
An address signal including the physical sector number determined in step 6 is transmitted from the data transmitting / receiving section 74 to the address decoder 4.

In response to this, the address decoder 4 sends an address / memory selection signal to the flash memory 8 to make the flash memory 8 select a sector of the chip specified by the physical sector number.

Next, the controller 7 includes an instruction generation unit 73
Generates an erase instruction. The generated erase command is sent from the data transmission / reception unit 74 to the flash memory 8 via the data control unit 5.

In response, the flash memory 8 erases the data written in the selected sector.

In steps 2009 and 2010, after the data erasure by the flash memory 8 is completed, data is written to the physical sector number determined by the physical sector number search / determination section 71.

First, the controller 7 executes step 200
An address signal including the physical sector number determined in step 6 is transmitted from the data transmitting / receiving section 74 to the address decoder 4.

In response to this, the address decoder 4 sends an address / memory selection signal to the flash memory 8 to make the flash memory 8 select a sector of the chip specified by the physical sector number.

Next, the controller 7 includes an instruction generation unit 73
Generates a write instruction. Further, it requests sector data to be written to the host computer.

Next, the data transmission / reception unit 74 sends the generated write command to the flash memory 8 via the data control unit 5 together with the sector data sent from the host computer.

In response, the flash memory 8 writes the received sector data in the selected sector.

After the data writing by the flash memory 8 is completed, the controller 7
Then, the contents of each table stored in the address conversion table storage unit 2 and the sector management table 3 are updated according to the processing contents in steps 2004 to 2010 (step 2011).

More specifically, steps 2009 and 2010
If the physical sector number in which the sector data has been written in step is the physical sector number obtained in step 2002, the use status of the physical sector number in the sector management table is set to "valid".
Change to

The physical sector number in which the sector data was written in steps 2009 and 2010 is
In the case other than the physical sector number obtained in step 002, the use state of the physical sector number in which the sector data is written is changed to “valid” in the sector management table, and the use state of the physical sector number obtained in step 2002 is changed. Change to "Invalid". At the same time, in the address conversion table, the physical sector number associated with the logical sector number of interest is changed to the physical sector number in which the sector data has been written.

Next, the controller 7 completes the write processing to the flash memory 8 for the sector data of all the logical sector numbers specified by the data indicating the logical start sector number and the write sector number received from the host computer. It is determined whether or not (Step 2012).

If writing has not been completed for the sector data of all the logical sector numbers, the logical sector number of interest is incremented by one (step 201).
3) Return to step 2002 and repeat the processing of steps 2002 to 2012.

On the other hand, when the writing is completed, this flow is completed.

FIG. 21 is a diagram for explaining how the physical sector number is determined and how the address translation table and the sector management table are updated in the flow shown in FIG.

The contents of the address conversion table and the sector management table before updating are indicated by reference numerals 23a and 3 respectively.
3a.

Logical sector number 1 from host computer
If there is a write request to the physical sector number 2, the physical sector number search / determination unit 71 determines from the address conversion table 23 a that the physical sector number 2
Is detected, and the use status of the detected physical sector number 2 is checked using the sector management table 33a.

In the example shown in FIG. 21, since the use status of the physical sector number 2 is "valid", the physical sector number search /
The determining unit 71 searches the sector management table 33a for a physical sector number whose use status is "unused", and obtains a physical sector number 5.

The sector data of the logical block 1 is written to the sector specified by the physical sector number 5 of the flash memory 8.

Next, the table change unit 72 changes the use status of the physical sector number 5 in which the sector data is written to “valid” and the use status of the physical sector number 2 to “invalid” in the sector management table 33a. Sector management table 33
Update to b.

The address conversion table 23a is updated to an address conversion table 23b in which the logical sector number 1 is associated with the physical sector number 5.

[0053]

In the above-mentioned conventional flash memory device, if data has already been written to the physical sector number associated with the logical sector number for which a write request has been made, no data is written. The physical sector number is searched, and data is written to the physical sector number.

As described above, in the above-mentioned conventional flash memory device, a process of searching for an unused physical address number may be required, and data cannot be stably written at a high speed to the flash memory. There is a problem.

In particular, if a search for an unused physical address number does not result in the detection of a physical sector number to which no data has been written, the physical sector number is associated with the logical sector number for which a write request was made. After erasing the data written to the physical address number, the data is written to the physical address number, so that the data write processing becomes extremely slow.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a flash memory device capable of writing data to a flash memory stably at a high speed, and a flash memory device capable of writing data to the flash memory. It is to provide a writing method.

[0057]

In order to solve the above-mentioned problems, a flash memory device of the present invention stores data in each of a plurality of physical sector numbers of a flash memory corresponding to a plurality of logical sector numbers for which a write request has been made. A flash memory device for writing, comprising: an instruction generation unit that generates a data write instruction or an erase instruction to the flash memory; and a control unit that controls the instruction generation unit, wherein the control unit For each of a plurality of existing logical sector numbers, a data erase instruction of a physical sector number corresponding to a logical sector number to be processed next to the logical sector number, and a data write instruction of a physical sector number corresponding to the logical sector number And so as to be sequentially generated,
The flash memory controls the instruction generation unit, and stores the physical sector number corresponding to the logical sector number to be processed next to the logical sector number in accordance with the erase instruction and the write instruction sequentially generated by the instruction generation unit. It is characterized in that data erasure of a sector number and data writing to a physical sector number corresponding to the logical sector number are executed in parallel.

Further, according to the method for writing data to a flash memory of the present invention, data is written to the flash memory by writing data to each of a plurality of physical sector numbers of the flash memory corresponding to a plurality of logical sector numbers for which a write request has been made. Issuing a data erasure command of a physical sector number corresponding to a logical sector number to be processed next to the logical sector number for each of the plurality of logical sector numbers for which the write request has been issued; Issuing a command to issue a data write command to a physical sector number corresponding to the logical sector number after issuing the command.

According to the present invention, with the above configuration, for each of a plurality of logical sector numbers for which a write request has been made,
The data writing to the physical sector number corresponding to the logical sector number can be performed during the data erasing process of the physical sector number corresponding to the logical sector number to be processed next to the logical sector number.

Therefore, data writing to the flash memory can be performed stably and at high speed.

[0061]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described.

FIG. 1 is a schematic configuration diagram of a flash memory device according to a first embodiment of the present invention.

Here, reference numeral 1 denotes a controller, and reference numeral 6 denotes a flash memory.

The other structure is the same as that of the conventional flash memory device shown in FIG. Therefore, these are given the same reference numerals as those shown in FIG. 18 and their detailed description is omitted.

The controller 1 controls the components of the flash memory device shown in FIG. 1 in an integrated manner.

FIG. 2 is a schematic functional block diagram of the controller shown in FIG.

As shown in FIG. 2, the controller 1 includes a physical sector number acquiring unit 11, a sector management table changing unit 12, a write command generating unit 13, and an erasing command generating unit 14.
And a data transmission / reception unit 15 and a control unit 16.

The physical sector number obtaining section 11 refers to the table stored in the address conversion table storage section 2 and
The physical sector number associated with the logical sector number of the sector data requested to be written by the host computer is obtained.

Then, by referring to the table stored in the sector management table storage unit 3, the use status of the obtained physical sector number is checked.

The sector management table change unit 12 updates the contents of the sector management table according to the change in the usage status of the physical sector number.

The write command generator 13 generates a command for writing data to the flash memory 6.

The erasure command generator 14 generates an erasure command for the data written in the flash memory 6.

The data transmission / reception section 15 receives a write request sent from the host computer and sector data requested by the request. Then, it sends the received data and the commands generated by the command generators 13 and 14 to the data controller 5. The address signal including the physical sector number obtained by the physical sector number obtaining unit 11 is sent to the address decoder 4.

The control section 16 controls each section of the controller 1 in an integrated manner. Then, the output timing of data, instructions, and the like output from the data transmitting / receiving unit 15 is adjusted.

The output timing is adjusted in the following manner.

It is assumed that a write request is issued from the host computer for a plurality of logical sector numbers 1 to m.

The physical sector number acquisition unit 11 is controlled prior to generation of a write command for writing the sector data of the logical sector number n (1 <n <m) to the physical sector number associated with the logical sector number n. Then, the physical sector number associated with the logical sector number n + 1 and the usage status of the physical sector number are obtained.

Next, when the obtained physical sector number is “unused”, the write command generation unit 13 generates a write command for writing data to the physical sector number associated with the logical sector number n. ,Output.

On the other hand, when the obtained physical sector number is other than “unused”, the erase command generator 14 generates an erase command for the data and sends it to the flash memory 6.

Thereafter, the write command generation unit 13 generates and outputs a write command for writing data to the physical sector number associated with the logical sector number n.

In this manner, while the data written to the physical sector number associated with the logical sector number n + 1 is being erased in the flash memory 6, the flash memory 6 is associated with the logical sector number n. The data write process to the specified physical sector number is performed.

The controller 1 is, for example, a CPU
Executes a predetermined program to realize the function shown in FIG.

The flash memory 6 is composed of a plurality of memory chips. The flash memory 6 itself has substantially the same configuration as the conventional one.

However, in the present embodiment, in a flash memory in which writing and erasing cannot be performed simultaneously between different sectors in the same memory chip, the above-described processing, that is, the physical sector associated with the logical sector number n + 1 The physical sector number is set so that data can be written to the physical sector number associated with the logical sector number n while the data written to the sector number is being erased. Each time the memory sector is incremented by one, the memory chip to which the physical sector number is assigned is changed.

FIG. 3 is a diagram showing bit assignment of the address bus signal ADP output from the controller 1.

In this embodiment, as shown in FIG. 3, the address bus signal output from the controller 1
st Significant Bit) to LSB (Last Significant B)
It) is composed of a physical sector number and a word number in the physical sector in that order.

The physical sector number is composed of a sector number in a memory chip and a memory chip number in this order.

Here, the number of sectors in a memory chip is 2 ^M , the number of memory chips is 2 ^N , and the number of words in a physical sector is 2 ^Q.

As described above, by assigning the sector number in the memory chip to an address higher than the memory chip number, the memory chip number can be changed by incrementing the physical sector number by one.

FIG. 4 is a diagram showing a connection example of signal lines between the address decoder 4 shown in FIG. 1 and each memory chip constituting the flash memory 6.

Here, the address bus signal is M = 12
(Number of sectors in memory chip = 4096), N = 3 (number of memory chips = 8), and Q = 8 (number of words in physical sector = 256).

[0092] In FIG. 4, reference numeral 9 is the address bus signal lines for conveying the physical sector number sent from the controller 1, reference numeral 62 ₁ ~ code 62 ₈ is a memory chip constituting the flash memory 6.

In the example shown in FIG. 4, the address 23 bits P
Upper 12 bits PA12 to PA of A1 to PA23
23 is an upper address A of each of the memory chips 62 _{1 to} 62 _8.
1 to A8.

Further, the middle three bits PA9 to PA11 are
Is connected to the input side X1~X3 address decoder 4, the lower 8 bits PA1~PA8 each memory chip 62 _1-6
And it is connected to the lower address A9~A20 of 2 _8.

The output of the address decoder 4 is connected to the chip selection signal CS of the memory chips 62 _{1 to} 62 ₈ .

With the above connection, a flash memory access corresponding to the bit configuration shown in FIG. 3 can be realized.

In FIGS. 3 and 4, in a flash memory in which writing and erasing cannot be performed simultaneously between different sectors in the same memory chip, the above processing, that is, the logical sector number n + 1 is associated. A configuration for enabling data write processing to be performed on the physical sector number associated with the logical sector number n while the data written to the physical sector number is being erased is described. did.

However, if the flash memory can simultaneously perform writing and erasing between different sectors in the same memory chip, the above-described processing can be realized without being restricted by the bit configuration of the address bus.

Next, the operation of the flash memory device shown in FIG. 1 will be described.

FIGS. 5 and 6 are flowcharts for explaining the operation of the flash memory device shown in FIG.

In FIG. 5, first, when the host computer issues a write request to the flash memory device, the controller 1 stores the logical start sector number and the number of write sectors sent from the host computer by the data transmission / reception section 15. (Step 10)
01).

Next, in the controller 1, the physical sector number obtaining unit 11 obtains a logical sector number to be processed (step 1002).

In the first (first) processing in step 1002, the starting logical sector number is obtained as the logical sector number to be processed.

Step 100 after that (second and subsequent times)
In the process in 2, the logical sector number to be processed is obtained by incrementing the logical sector number obtained in the previous step 1002 by one.

Next, the controller 1 causes the physical sector number acquiring section 11 to enter the physical sector number associated with the logical sector number obtained in the immediately preceding step 1002,
It is obtained from the table stored in the address conversion table storage unit 2 (step 1003).

Then, the usage status of the obtained physical sector number is obtained from the table stored in the sector management table storage unit 3 (step 1004).

Next, the controller 1 causes the control unit 16 to determine whether or not the logical sector number obtained in the immediately preceding step 1002 is the starting logical sector number (step 1005).

When the immediately preceding step 1002 is the first processing, the logical sector number obtained in the processing is the starting logical sector number.

In this case, the control unit 16
Then, it is determined whether or not the use status of the physical sector number corresponding to the logical start sector number obtained in step 1004 is “unused”.

Then, if "unused", step 1
002, the logical sector number to be processed next to the starting logical sector number is obtained, and steps 1003, 100
Step 4 is repeated.

On the other hand, if it is not “unused”, the erase command generator 14 generates an erase command for erasing the sector data of the physical sector number corresponding to the start logical sector number obtained in step 1002, and The data is output from the transmission / reception unit 15 to the flash memory 6 (step 1007).

In response, flash memory 6 starts erasing the sector data of the physical sector number corresponding to the starting logical sector number.

The controller 1 waits for the flash memory 6 to complete the erasing process of the sector data written in the physical sector number corresponding to the starting logical sector number (step 1008), and then proceeds to step 1002. , The logical sector number to be processed next to the start logical sector number is obtained, and the processing of steps 1003 and 1004 is repeated.

In step 1005, if step 1002 executed immediately before is the second or later processing, the logical sector numbers obtained in the processing are logical sector numbers other than the starting logical sector number.

In this case, the process proceeds to step 1009,
The control unit 16 determines whether or not the use status of the physical sector number corresponding to the logical sector number obtained in step 1002 and obtained in step 1004 is “unused”.

If "unused", step 1
010, the logical sector number immediately before the logical sector number obtained in step 1002 executed immediately before, that is, the host computer, that is, step 1002
, The sector data corresponding to the logical sector number (hereinafter, this logical sector number is referred to as n) obtained in the processing immediately before the processing executed immediately before is requested.

The write command generator 13 generates a write command for writing the requested sector data in the physical sector number corresponding to the logical sector number n obtained in step 1004.

Then, the data transmission / reception section 15 outputs a write command and sector data to the flash memory 6.

In response to this, the flash memory 6 starts writing sector data of the logical sector number n to the physical sector number corresponding to the logical sector number n.

The controller 1 waits for the data write processing to the physical sector number corresponding to the logical sector number n by the flash memory 6 to be completed (step 10).
11) Then, the process proceeds to step 1016 shown in FIG.

On the other hand, if it is not “unused” in step 1009, the flow shifts to step 1012, and the erase command generation unit 14 executes step 1010 executed immediately before.
An erasing instruction is generated for the data written in the physical sector data corresponding to the logical sector number obtained in 02 (hereinafter, this logical sector number is referred to as n + 1).

Then, the data transmission / reception unit 15 sends an erasure command to the flash memory 6.

In response to this, flash memory 6 starts erasing the sector data of the physical sector number corresponding to logical sector number n + 1.

Next, the controller 1 causes the control unit 16 to transmit, to the host computer, the sector data corresponding to the logical sector number n immediately before the logical sector number obtained in step 1002 executed immediately before. Request.

The write command generator 13 generates a write command for writing the requested sector data to the physical sector number corresponding to the logical sector number n obtained in step 1004.

Then, the data transmission / reception section 15 outputs a write command and sector data to the flash memory 6.

In response to this, the flash memory 6 starts writing sector data of the logical sector number n to the physical sector number corresponding to the logical sector number n.

The controller 1 completes the data writing processing to the physical sector corresponding to the logical sector number n and the erasing processing of the data written to the physical sector corresponding to the logical sector number n + 1 by the flash memory 6. (Steps 1014 and 1015), and then the process proceeds to step 1016 shown in FIG.

In FIG. 6, in step 1016, the logical sector number n is
The table stored in the sector management table storage unit 3 is updated as necessary so that the use status of the physical sector number corresponding to the above becomes “valid”.

Next, the controller 1 uses the control unit 16 to determine whether or not the logical sector number n + 1 obtained in the immediately preceding step 1002 is the last sector number for which a write request has been made (step 1017). ).

If it is not the last sector number, the flow returns to step 1002 shown in FIG. 5 to repeat the above processing.

On the other hand, if it is the last sector number, the control unit 16 requests the host computer for sector data corresponding to the last sector number.

The write command generator 13 generates a write command for writing the requested sector data in the physical sector number corresponding to the last sector number obtained in step 1003.

Then, the data transmission / reception section 15 outputs a write command and sector data to the flash memory 6.

In response to this, the flash memory 6 starts writing sector data of the last sector number to the physical sector number corresponding to the last sector number.

The controller 1 waits for the data write processing by the flash memory 6 to the physical sector corresponding to the last sector number to be completed (step 101).
9) Then, this flow ends.

FIG. 7 is a diagram for explaining how the physical sector number is determined and how the sector management table is updated in the flows shown in FIGS. 5 and 6.

The contents of the address conversion table are indicated by reference numeral 21.
a, it is assumed that the contents of the sector management table before update are indicated by reference numeral 31a. It is also assumed that a write request is issued from the host computer to logical sector numbers 1 to 4.

Step B1 The controller 1 detects the physical sector number 2 associated with the logical sector number 1 from the address conversion table 21a, and checks the use status of the detected physical sector number 2 using the sector management table 31a. .

In the example shown in FIG. 7, the use status of the physical sector number 2 is “valid”.

In this case, the controller 1 issues an instruction to erase the data written in the physical sector number 2 and causes the flash memory 6 to erase the data.

Step B2 Next, the controller 1 sets the address conversion table 21a
, The physical sector number 10 associated with the logical sector number 2 is detected, and the use status of the detected physical sector number 10 is checked using the sector management table 31a.

In the example shown in FIG. 7, the use status of the physical sector number 10 is “valid”.

In this case, the controller 1 issues an instruction to erase the data written to the physical sector number 10 and then issues a write instruction to the physical sector number 2 so that the flash memory 6 has the physical sector number 10 The data is written to the physical sector number 2 while erasing the data written to the.

Steps B3 and B4 Processing is performed in the same manner as in step B2.

Therefore, in step B3, data is written to the physical sector number 10 while erasing the data written to the physical sector number 8 in the flash memory 6.

In step B4, data is written to physical sector number 8 while erasing the data written to physical sector number 20.

Step B5 The controller 1 issues a write instruction to the physical sector number 20, thereby writing the data of the physical sector number 20 to the flash memory 6.

FIG. 8 is a diagram showing an example of each signal timing when the flash memory device shown in FIG. 1 executes the flows shown in FIG. 5 and FIG.

Here, an example in which writing is performed in the order of physical sector number 1, physical sector number 2, and physical sector number 3 is shown. Also, physical sector number 1
Indicates that the data has already been erased, and physical sector number 2,
No. 3 is in a state where the previous data has been written.

In FIG. 8, AD is address data, DT is data, CS is a memory chip selection signal, WE
Is a write enable signal, and OE is an output enable signal.

Further, CMD is instruction data, WAD is a write destination address, WDT is write data, and S
T indicates an erase / write execution status.

First, prior to writing data to the physical sector number 1 to be written, the controller 1 issues an erase command CMD101 to the physical sector number 2.

When the flash memory 6 receives the erase command and shifts to the execution of data erase of the physical sector number 2, the controller 1 issues a write command CMD102 to the physical sector 1.

Flash memory 6 receiving write command
Shifts to execution of data writing to physical sector number 1.

When the data writing to the physical sector number 1 is completed, the controller 1 reads the data erase execution status ST103 of the physical sector number 2 output from the flash memory 6 until the data erase of the physical sector number 2 is completed.

When the erasure of the physical sector number 2 is completed, the controller 1 issues an erase command CM to the physical sector number 3.
Issue D104.

When the flash memory 6 receives the erase command and shifts to the execution of the data erase of the physical sector number 3, the controller 1 writes the write command CMD 105 to the physical sector number 2.
Issue

Flash memory 6 receiving write command
Shifts to execution of data writing to physical sector number 2.

When the data writing to the physical sector number 2 is completed, the controller 1 reads the data erase execution status ST106 of the physical sector number 3 output from the flash memory 6 until the data erase of the physical sector number 3 is completed.

The above operation is repeatedly executed until writing of the number of blocks requested by the host computer is completed.

In the first embodiment of the present invention, in the flash memory 6, while executing the data erasing process of the physical sector number associated with the logical sector number n + 1 to which data is to be written next, the logical sector to which data is to be written is written. Data writing processing is performed on the physical sector number associated with the number n.

Therefore, according to the first embodiment, FIG.
Unlike the conventional flash memory device shown in FIG. 8, there is no need to perform a process of searching for an unused physical address number. Further, there is no need to perform processing such as updating the contents of the address conversion table.

Further, since the data erasing process of the physical address number and the data writing process are performed in parallel in time, the processing time delay caused by the data erasing can be reduced.

As a result, data writing to the flash memory 6 can be performed stably and at high speed.

Here, the present inventors simulated the time required for writing and erasing with respect to the flash memory device of the present embodiment and the conventional flash memory device shown in FIG.

The flash memory is 16 Mbits,
The data bus width was assumed to be 16 bits.

The specifications of the flash memory are as follows: Write instruction cycle: 0.1 μs / word Write execution cycle: 6.0 μs / word Erase instruction cycle: 0.1 μs / sector Erase execution cycle: 300,000 s / sector , 1 word = 2 bytes, 1 sector = 64 kbytes.

16M bits = 1M (1024 × 102
4) Since words = 32 sectors, the time required for writing and erasing 16 Mbits is: writing time = (0.1 μs + 6.0 μs) × 1024
× 1024 = 6.4 s Erasure time = (0.1 μs + 300000 μs) × 32 =
9.6 s.

In the conventional flash memory device, writing is performed after erasing is completed. Therefore, the time required for erasing and writing is 6.4 s + 9.6 s = 16.0 s.

On the other hand, in the present embodiment, since the writing process is executed during the execution of the erasing process, it is possible to shorten the writing process. 1 sector = 64k bytes = 32k
Since it is (32 × 1024) words, the time required for writing for one sector is 6.1 μs × 32 × 1024 = 0.2 s. Since the erasing time is 0.3 s (300,000 μs), the writing is completed during the erasing. Since the sector write processing is performed in parallel with the erase processing except for the last sector, the time required for writing and erasing 16 Mbits in this embodiment is 9.6 s + 0.2 s = 9.8 s. Become.

Here, an example of the physical sector number acquiring unit 11 of the controller 1 described above will be described.

FIG. 22 is a schematic block diagram showing an example of the physical sector number obtaining section 11 shown in FIG.

As shown in FIG. 22, the logical sector storage 1
11, a + X storage unit 112 that outputs + X when the erase flag is valid, an adder 113, and a logical sector output unit 114
And a physical sector storage unit 115.

The logical sector storage section 111, the logical sector output section 114 and the physical sector storage section 115 are constituted by registers or buffers.

The + X storage unit 112 stores a relative value X (normally, a sector number for which a write request is issued from the host computer) to a sector number to be processed next (that is, a sector number to be erased). +1) is stored.

The logical sector number for which a write request has been made from the host computer is input to the logical sector storage unit 111.

At the time of writing, since the erase flag is invalid,
The + X storage unit does not output + X (actually, outputs 0). Therefore, the logical sector number received from the host computer is output from the logical sector output unit 114 via the adder 113 as it is.

At the time of erasing, the erasing flag becomes valid, and + X
Since the storage unit 112 outputs + X, the adder 113
A value obtained by adding + X to the logical sector number received from the host computer (the logical sector number storing the data to be erased) is output from the logical sector output unit 114.

The physical sector number output from the address conversion table storage unit 2 is stored in the physical sector number storage unit and sent to the data transmission / reception unit 15.

Next, a second embodiment of the present invention will be described.

FIG. 9 is a schematic configuration diagram of a flash memory device according to a second embodiment of the present invention.

The flash memory device of the second embodiment of the present invention shown in FIG. 9 is different from that of the first embodiment shown in FIG. 1 in that a controller 1a is provided instead of the controller 1 and that a sector management table is provided. That is, the storage unit 3 is not provided.

The other structure is the same as that of the first embodiment. Therefore, the other components are denoted by the same reference numerals as those shown in FIG. 1 and their detailed description is omitted.

FIG. 10 is a schematic functional block diagram of the controller 1a shown in FIG.

The controller 1a differs from the controller 1 of the first embodiment shown in FIG. 1 in that a controller 16a is provided instead of the controller 16 and that the sector management table changing unit 12 is not provided. is there.

The control section 16a controls each section of the controller 1a as a whole. Then, the output timing of data, instructions, and the like output from the data transmitting / receiving unit 15 is adjusted.

The output timing is adjusted in the following manner.

It is assumed that the host computer issues a write request for a plurality of logical sector numbers 1 to m.

Before generating the write command for writing the sector data of the logical sector number n (1 <n <m) to the physical sector number associated with the logical sector number n, the physical sector number acquiring unit 11 is controlled. Then, the physical sector number associated with the logical sector number n + 1 is obtained. Then, the erase command generator 14 generates a data erase command of the obtained physical sector number and sends it to the flash memory 6.

After that, the write command generator 13 generates and outputs a write command for writing data to the physical sector number associated with the logical sector number n.

In this way, while the data written in the physical sector number corresponding to the logical sector number n + 1 is being erased in the flash memory 6, the flash memory 6 is associated with the logical sector number n. The data write process to the specified physical sector number is performed.

Next, the operation of the flash memory device shown in FIG. 9 will be described.

FIGS. 11 and 12 are flow charts for explaining the operation of the flash memory device shown in FIG.

Here, reference numerals 1101 to 1103, 1105, 1112 to 1115, and 1117 to 1119 correspond to FIGS.
Step 1001 to Step 1003 of the flow shown in
Step 1005, Step 1012 to Step 101
5. This step performs the same processing as steps 1017 to 1019.

The flow showing the operation of the second embodiment of the present invention shown in FIGS. 11 and 12 is different from the flow showing the operation of the first embodiment of the present invention shown in FIGS. 5 and 6 in steps 1004 and 1006. Step 1011 and Step 1016 are removed, that is, the usage status of the physical sector number corresponding to the logical sector number n + 1 to be processed next is checked, and the logical sector n is determined according to the status.
The configuration is such that the process of determining whether to issue the data erase instruction of the physical sector number corresponding to +1 is eliminated.

Therefore, in this embodiment, prior to generation of a data write instruction to the physical sector number associated with the logical sector number n to be processed, the physical sector associated with the logical sector number n + 1 to be processed next The data erase command of the number is issued regardless of the use status of the physical sector number.

Then, the logical sector number n to be processed next
While the data of the physical sector number associated with +1 is being erased, data is written to the logical sector number n to be processed.

Thus, data can be stably written at a high speed to the flash memory 6 without providing a sector management table.

Next, a third embodiment of the present invention will be described.

FIG. 13 is a schematic configuration diagram of a flash memory device according to a third embodiment of the present invention.

The flash memory device according to the third embodiment of the present invention shown in FIG. 13 differs from that of the first embodiment shown in FIG. 1 in that a controller 1b is provided instead of the controller 1, and an address conversion table That is, the storage unit 2 is not provided.

The other structure is the same as that of the first embodiment. Therefore, the other components are denoted by the same reference numerals as those shown in FIG. 1 and their detailed description is omitted.

FIG. 14 is a schematic functional block diagram of the controller 1b shown in FIG.

The difference between the controller 1b and the controller 1 of the first embodiment shown in FIG. 1 is that the controller 1b is not provided with the physical sector number acquisition unit 11.

In this embodiment, the physical sector number acquisition unit 1
1 is not provided. The logical sector number for which the host computer requested to write data becomes the physical sector number of the flash memory 6 to which the data is to be written.

That is, the flow showing the operation of the present embodiment is different from the flow showing the operation of the first embodiment shown in FIGS. 5 and 6 in that a logical sector number is converted into a corresponding physical sector number using an address conversion table. 5 (step 1003 in FIG. 5).

In this manner, data can be stably written at a high speed to the flash memory 6 without providing an address conversion table.

Next, a fourth embodiment of the present invention will be described.

FIG. 15 is a schematic configuration diagram of a flash memory device according to a fourth embodiment of the present invention.

The flash memory device according to the fourth embodiment of the present invention shown in FIG. 15 is different from that of the first embodiment shown in FIG. 1 in that a controller 1c is provided instead of the controller 1, and That is, the table storage unit 2 and the sector management table 3 are not provided.

The other structure is the same as that of the first embodiment. Therefore, the other components are denoted by the same reference numerals as those shown in FIG. 1 and their detailed description is omitted.

FIG. 16 is a schematic functional block diagram of the controller 1b shown in FIG.

The controller 1c is different from the controller 1 of the first embodiment shown in FIG. 1 in that the physical sector number obtaining unit 11 and the sector management table changing unit 12 are not provided, and the control unit 1 That is, the unit 1c is provided.

In this embodiment, the physical sector number acquisition unit 1
1 is not provided. The logical sector number for which the host computer requested to write data becomes the physical sector number of the flash memory 6 to which the data is to be written.

The control section 16c controls each section of the controller 1c as a whole. Then, the output timing of data, instructions, and the like output from the data transmitting / receiving unit 15 is adjusted.

The output timing is adjusted in the following manner.

It is assumed that a write request has been issued from the host computer for a plurality of logical sector numbers 1 to m (in the present embodiment, these become the physical sector numbers as they are).

Prior to generating a write command for writing sector data to physical sector number n (1 <n <m), erase command generator 14 generates a data erase command for physical sector number n + 1 and writes it to flash memory 6. send.

Thereafter, the write command generator 13 generates and outputs a write command for writing data to the physical sector number n.

By doing so, in the flash memory 6, data is written to the physical sector number n while the data written to the physical sector number n + 1 is being erased. .

Next, the operation of the flash memory device shown in FIG. 15 will be described.

FIG. 17 is a flow chart for explaining the operation of the flash memory device shown in FIG.

Here, reference numerals 1201, 1202, 1205, 1212 to 1215, and 1217 to 1219 correspond to FIGS. 5 and 6, respectively.
Step 1001, Step 1002,
Step 1005, Step 1012 to Step 101
5. This step performs the same processing as steps 1017 to 1019.

The flow showing the operation of the fourth embodiment of the present invention shown in FIG. 17 is different from the flow showing the operation of the first embodiment of the present invention shown in FIGS. 5 and 6 in steps 1003, 1004, and 1006. ~ Step 101
1 and step 1016 are removed.

That is, the process of acquiring the physical sector number corresponding to the logical sector number from the address conversion table and the usage status of the physical sector number corresponding to the logical sector number n + 1 to be processed next are checked. The process of determining whether to issue a data erase instruction of a physical sector number corresponding to logical sector n + 1 is eliminated.

Therefore, in this embodiment, prior to generation of a data write instruction for the logical sector number n to be processed (this is the physical sector number n as it is), the logical sector number n + 1 to be processed next (this is the physical sector number as it is) (n + 1) is issued regardless of the use status of the physical sector number n + 1.

Then, the physical sector number n to be processed next
While +1 data is being erased, data is written to the physical sector number n to be processed.

In this way, data can be stably written at a high speed to the flash memory 6 without providing an address conversion table and a sector management table.

The present invention is not limited to the above embodiments, and various modifications are possible within the scope of the invention.

For example, in each of the above embodiments, the description has been given of the one which operates according to the starting logical sector number and the number of write sectors sent from the host computer.

However, the present invention is not limited to this.
The operation may be performed by receiving all logical sector numbers for which writing is requested. In such a case, the logical sector numbers requested to be written need not be serial numbers.

[0233]

As described above, according to the present invention,
Data can be stably written at a high speed to the flash memory.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a flash memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic functional block diagram of a controller shown in FIG. 1;

FIG. 3 is a diagram showing bit assignment of an address bus signal ADP output from the controller shown in FIG. 1;

4 is a diagram showing a connection example of signal lines between memory chips constituting the address decoder and the flash memory shown in FIG. 1;

FIG. 5 is a flowchart illustrating the operation of the flash memory device shown in FIG. 1;

FIG. 6 is a flowchart illustrating the operation of the flash memory device shown in FIG. 1;

7 is a diagram for explaining how a physical sector number is determined and how a sector management table is updated in the flows shown in FIGS. 5 and 6. FIG.

FIG. 8 is a diagram showing an example of each signal timing when the flash memory device shown in FIG. 1 executes the flows shown in FIGS. 5 and 6;

FIG. 9 is a schematic configuration diagram of a flash memory device according to a second embodiment of the present invention.

FIG. 10 is a schematic functional block diagram of the controller shown in FIG. 9;

FIG. 11 is a flowchart illustrating the operation of the flash memory device shown in FIG. 9;

FIG. 12 is a flowchart illustrating the operation of the flash memory device shown in FIG. 9;

FIG. 13 is a schematic configuration diagram of a flash memory device according to a third embodiment of the present invention.

14 is a schematic functional block diagram of the controller shown in FIG.

FIG. 15 is a schematic configuration diagram of a flash memory device according to a fourth embodiment of the present invention.

16 is a schematic functional block diagram of the controller shown in FIG.

17 is a flowchart illustrating the operation of the flash memory device shown in FIG.

FIG. 18 is a schematic configuration diagram of a conventional flash memory device.

FIG. 19 is a schematic functional block diagram of the controller shown in FIG. 18;

FIG. 20 is a flowchart illustrating the operation of the flash memory device shown in FIG. 18;

21 is a diagram illustrating how the physical sector number is determined and how the address translation table and the sector management table are updated in the flow shown in FIG.

FIG. 22 is a schematic block diagram illustrating an example of a physical sector number acquisition unit illustrated in FIG.

[Explanation of symbols]

1, 1a, 1b, 1c, 7 Controller 2 Address conversion table storage unit 3 Sector management table storage unit 4 Address decoder 5 Data control unit 6, 8 Flash memory 9 Address bus signal line 11 Physical sector number acquisition unit 12 Sector management table change Unit 13 write instruction generation unit 14 erase instruction generation unit 15 data transmission / reception unit 16, 16a, 16c control unit 21a address conversion table 31a sector management table 62 _{1 to} 62 ₈ memory chip 111 logical sector storage unit 112 + X storage unit 113 adder 114 Logical sector output unit 115 Physical sector storage unit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhisa Nishimoto 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information System Co., Ltd.

Claims (6)

[Claims] 1. A flash memory device for writing data to each of a plurality of physical sector numbers of a flash memory corresponding to a plurality of logical sector numbers for which a write request has been issued, comprising: An instruction generating unit that generates the instruction; and a control unit that controls the instruction generating unit. Controlling the instruction generation unit to sequentially generate a data erase instruction of a physical sector number corresponding to a logical sector number and a data write instruction to a physical sector number corresponding to the logical sector number; The flash memory stores the logical section according to an erase instruction and a write instruction sequentially generated by the instruction generation unit. Data erasing of a physical sector number corresponding to a logical sector number to be processed next to a number and data writing to a physical sector number corresponding to the logical sector number are executed in parallel. Flash memory device. 2. The flash memory device according to claim 1, further comprising: an address conversion table storage unit storing an address conversion table indicating a correspondence relationship between a logical sector number and a physical sector number. A flash memory device comprising means for acquiring each of physical sector numbers corresponding to a plurality of logical sector numbers for which a write request has been made from an address conversion table stored in said address conversion table storage means. 3. The flash memory device according to claim 1, further comprising: a sector management table storing means for storing a sector management table indicating a use status of a physical sector number; Means for obtaining, from each of the plurality of logical sector numbers, the use status of the physical sector number corresponding to the logical sector number to be processed next to the logical sector number from the sector management table stored in the sector management table storage means. If the acquired usage status indicates that data has been written, the data erasing instruction of the physical sector number corresponding to the logical sector number to be processed next to the logical sector number; And a data write instruction to the physical sector number corresponding to the logical sector number. If the usage state indicates that no data has been written, the instruction generation unit is controlled so as to generate a data write instruction to a physical sector number corresponding to the logical sector number. A flash memory device characterized by the above-mentioned. 4. The flash memory device according to claim 1, wherein an address conversion table storing means for storing an address conversion table indicating a correspondence relationship between a logical sector number and a physical sector number; And a sector management table storing means for storing a sector management table indicating the physical sector numbers corresponding to the plurality of logical sector numbers for which the write request has been made, in the address conversion table storing means. Means for acquiring from the stored address conversion table, and for each of the plurality of logical sector numbers for which the write request has been made, the use status of the physical sector number corresponding to the logical sector number to be processed next to the logical sector number, Means for acquiring from the sector management table stored in the sector management table storage means. If the obtained use status indicates that data has been written, a data erase instruction of the physical sector number corresponding to the logical sector number to be processed next to the logical sector number and the logical A command to sequentially write data to the physical sector number corresponding to the sector number is generated, and if the obtained usage state indicates that no data has been written, the logical sector number corresponds to the logical sector number. A flash memory device for controlling the instruction generation unit so as to generate a data write instruction to a physical sector number to be executed. 5. The flash memory device according to claim 1, wherein the flash memory includes a plurality of memory chips.
A flash memory device wherein two physical block numbers adjacent to each other are assigned to different memory chips, and the plurality of logical sector numbers for which the write request has been made are serial numbers. 6. A method of writing data to a flash memory in which data is written to each of a plurality of physical sector numbers of a flash memory corresponding to a plurality of logical sector numbers for which a write request has been made, the method comprising: Issuing a data erase command of a physical sector number corresponding to the logical sector number to be processed next to the logical sector number for each of the logical sector numbers of the logical sector numbers; Issuing a data write command to a sector number; and a method for writing data to a flash memory.