JPH11326949A - Active matrix type liquid crystal display element - Google Patents

Active matrix type liquid crystal display element

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Publication number
JPH11326949A
JPH11326949A JP13512598A JP13512598A JPH11326949A JP H11326949 A JPH11326949 A JP H11326949A JP 13512598 A JP13512598 A JP 13512598A JP 13512598 A JP13512598 A JP 13512598A JP H11326949 A JPH11326949 A JP H11326949A
Authority
JP
Japan
Prior art keywords
electrode
liquid crystal
insulating film
hole
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13512598A
Other languages
Japanese (ja)
Other versions
JP4031105B2 (en
Inventor
Kohei Nagayama
耕平 永山
Yasuyuki Hanazawa
康行 花澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13512598A priority Critical patent/JP4031105B2/en
Publication of JPH11326949A publication Critical patent/JPH11326949A/en
Application granted granted Critical
Publication of JP4031105B2 publication Critical patent/JP4031105B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To prevent a dot detect due to a defect in the conduction of a liquid crystal display element by securely forming a through hole for electrically connecting a pixel electrode, a source electrode, and a pixel electrode, and an auxiliary capacity electrode arranged across colored insulating films without any decrease in manufacture yield, and to obtain excellent display quality by preventing the aperture rate of the liquid crystal display element form decreasing owing to the through hole to improve the lightness and contrast. SOLUTION: A single through hole 47 which penetrates an organic resin insulating film 43 and a transparent protection insulating film 42 to reach the source electrode 37 and auxiliary capacity electrode 38 is formed above a gate line 33, and the pixel electrode 44a and a source electrode 37 of a precedent stage and the pixel electrode 44b and auxiliary capacity electrode 38 of te following stage are electrically connected to reduce the number of processes of the through hole 47 of the colored insulating layer 43 which is a thick film and hard to process to a half and also the light shield area in the pixel electrode 44 is reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電極基板間に液晶
組成物を保持して成る液晶表示素子において、マトリク
ス状に配列されたスイッチング素子にて画素電極を駆動
するアクティブマトリクス型液晶表示素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display in which pixel electrodes are driven by switching elements arranged in a matrix in a liquid crystal display having a liquid crystal composition held between electrode substrates. .

【0002】[0002]

【従来の技術】近年、薄型軽量且つ高密度大容量であり
ながら高機能更には高精細を得る液晶表示素子の開発が
図られ、特に高開口率化のために、透明な画素電極を、
薄膜トランジスタ(以下TFTと称する。)や金属・絶
縁膜・金属(MIM)素子等のスイッチング素子を覆う
ように配置して成る、画素上置き構造の液晶表示素子が
注目されている。更にカラーフィルタとのずれを考慮す
る必要が無く製造歩留まりの向上を得られるため、画素
電極下に有機樹脂絶縁膜を形成して成るカラーフィルタ
ー一体型のアレイ基板を用いて成るアクティブマトリク
ス型液晶表示素子の開発が成されていた。
2. Description of the Related Art In recent years, a liquid crystal display device which is thin, lightweight, high-density and large-capacity, yet has high performance and high definition has been developed. In order to increase the aperture ratio, a transparent pixel electrode is required.
Attention has been paid to a liquid crystal display element having a pixel-mounted structure, which is arranged so as to cover a switching element such as a thin film transistor (hereinafter referred to as a TFT) or a metal / insulating film / metal (MIM) element. Further, since it is not necessary to consider a deviation from a color filter and an improvement in manufacturing yield can be obtained, an active matrix type liquid crystal display using an array substrate of a color filter integrated type in which an organic resin insulating film is formed under a pixel electrode. A device was being developed.

【0003】このようなカラーフィルター一体型のアレ
イ基板を用いて成るアクティブマトリクス型液晶表示素
子は、従来図7及び図8に示す様に形成されていた。即
ち液晶表示素子1のアレイ基板2は、カラーフィルタで
ある有機樹脂絶縁膜11と一体的に形成され、アレイ基
板2上の信号線3とゲート線4の交差部には、画素電極
6のスイッチング素子であるTFT7が形成されてい
る。TFT7のソース電極8及び前段の画素電極6a
は、透明絶縁膜10と有機樹脂絶縁膜11を貫通する第
1のスルーホール12を介して電気的に接続され、ゲー
ト線4と補助容量を形成する補助容量電極13及び次段
の画素電極6bは、透明絶縁膜10と有機樹脂絶縁膜1
1を貫通する第2のスルーホール14を介して電気的に
接続されている。
An active matrix type liquid crystal display device using such an array substrate integrated with a color filter has conventionally been formed as shown in FIGS. That is, the array substrate 2 of the liquid crystal display element 1 is formed integrally with the organic resin insulating film 11 which is a color filter, and the switching of the pixel electrode 6 is provided at the intersection of the signal line 3 and the gate line 4 on the array substrate 2. A TFT 7 as an element is formed. The source electrode 8 of the TFT 7 and the previous pixel electrode 6a
Are electrically connected through a first through hole 12 penetrating the transparent insulating film 10 and the organic resin insulating film 11 to form an auxiliary capacitance electrode 13 forming an auxiliary capacitance with the gate line 4 and a next-stage pixel electrode 6b Are the transparent insulating film 10 and the organic resin insulating film 1
1 are electrically connected via a second through hole 14 penetrating through the first through hole 1.

【0004】又ー般的に、カラー表示を得るための十分
な色純度のカラーフィルターを得るためには、カラーフ
ィルタを構成する有機樹脂絶縁膜の膜厚を約3μmと厚
くする必要がある。
Generally, in order to obtain a color filter having sufficient color purity for obtaining a color display, it is necessary to increase the thickness of an organic resin insulating film constituting the color filter to about 3 μm.

【0005】[0005]

【発明が解決しようとする課題】従来画素電極上置きタ
イプのカラーフィルター一体型のアレイ基板にあって
は、有機樹脂絶縁膜を貫通する2個のスルーホールを介
して前段の画素電極及びソース電極或いは次段の画素電
極及び補助容量電極を夫々電気的に接続していた。一方
カラーフィルタを構成する有機樹脂絶縁膜の膜厚は、良
好なカラー表示を行うための十分な色純度のカラーフィ
ルターを得るためには、約3μmと厚くする必要があ
る。
In a conventional color filter-integrated array substrate on which a pixel electrode is placed, a preceding pixel electrode and a source electrode are provided through two through holes penetrating an organic resin insulating film. Alternatively, the pixel electrode and the auxiliary capacitance electrode at the next stage are electrically connected to each other. On the other hand, the thickness of the organic resin insulating film constituting the color filter needs to be as thick as about 3 μm in order to obtain a color filter having sufficient color purity for performing good color display.

【0006】このため厚膜の有機樹脂絶縁膜を貫通して
成るスルーホールは、その加工が難しく、貫通穴を完全
に形成できずに形成不良を発生し、点欠陥などの表示不
良を発生し易く、液晶表示素子の表示品位の低下を来た
すという問題を生じていた。しかも、従来のアレイ基板
にあっては加工の難しい厚膜の有機樹脂絶縁膜における
スルーホールを1画素電極当たり2個必要とすることか
ら、スルーホールの形成不良によるアレイ基板の歩留ま
りを一層低下していた。
For this reason, the through-hole formed through the thick organic resin insulating film is difficult to process, and the through-hole cannot be completely formed, resulting in defective formation and display defects such as point defects. This has caused a problem that the display quality of the liquid crystal display element is easily deteriorated. Moreover, since two through-holes per pixel electrode are required in a thick organic resin insulating film, which is difficult to process with the conventional array substrate, the yield of the array substrate due to defective formation of through-holes is further reduced. I was

【0007】又有機樹脂絶縁膜が厚膜であることからス
ルーホール径の最小加工寸法は10μm以上と大きく、
このようなアレイ基板を用いた液晶表示素子は開口率が
低下し、明るさ及びコントラストの低下により表示品位
が著しく低下するという問題も生じていた。
Further, since the organic resin insulating film is a thick film, the minimum processing size of the through hole diameter is as large as 10 μm or more.
The liquid crystal display device using such an array substrate has a problem that the aperture ratio is reduced and the display quality is significantly reduced due to the reduction in brightness and contrast.

【0008】このため本発明は上記課題を解決するもの
で、有機樹脂絶縁膜を貫通するスルーホールを介して前
段の画素電極とソース電極或いは次段の画素電極と補助
容量電極とを電気的に接続する際に、スルーホールの形
成不良を防止し、点欠陥などの表示不良による表示品位
の低下を防止しすると共に、スルーホールにより、液晶
表示領域の開口率が低下するのを防止し、表示画像の明
るさ及びコントラストの向上を図り高品位の表示を行う
事が出来るアクティブマトリクス型液晶表示素子を提供
する事を目的とする。
Therefore, the present invention solves the above-mentioned problems, and electrically connects a previous pixel electrode and a source electrode or a next pixel electrode and an auxiliary capacitor electrode through a through hole penetrating an organic resin insulating film. When connecting, prevent poor formation of through holes, prevent display quality degradation due to display defects such as point defects, and prevent through holes from lowering the aperture ratio of the liquid crystal display area. It is an object of the present invention to provide an active matrix liquid crystal display device capable of improving image brightness and contrast and performing high-quality display.

【0009】[0009]

【課題を解決するための手段】本発明は上記課題を解決
する為、絶縁基板上にゲート線と、このゲート線と交差
するよう配線される信号線と、前記ゲート線及び前記信
号線の交点に配列され少なくとも、チャネル領域を挟み
ソース領域及びドレイン領域を有する半導体層、前記ゲ
ート線と一体のゲート電極、前記ソース領域に接続され
るソース電極並びに前記ドレイン領域に接続されるドレ
イン電極を有するスイッチング素子と、前記ゲート線と
補助容量を形成する補助容量電極と、前記スイッチング
素子及び前記補助容量電極を被覆する有機樹脂絶縁膜
と、この有機樹脂絶縁膜上の前記ゲート線及び前記信号
線に囲まれる領域にマトリクス状に配置され前記有機樹
脂絶縁膜に形成されたスルーホールを介して前記ソース
電極に接続される複数の画素電極を有するアレイ基板
と、前記アレイ基板に間隙を隔てて対向配置される対向
基板と、前記アレイ基板及び前記対向基板間に封入され
る液晶組成物とを具備する液晶表示装置において、前記
補助容量電極が前記ソース電極と共通のスルーホールを
介して前記有機樹脂絶縁膜より露出され、かつ前記ソー
ス電極に接続された画素電極と前記ゲート線を挟んで隣
接する他の画素電極に対し前記スルーホールを介して接
続されているものである。
In order to solve the above-mentioned problems, the present invention provides a gate line on an insulating substrate, a signal line wired so as to intersect the gate line, and an intersection of the gate line and the signal line. A semiconductor layer having at least a source region and a drain region sandwiching a channel region, a gate electrode integral with the gate line, a source electrode connected to the source region, and a drain electrode connected to the drain region An element, an auxiliary capacitance electrode forming an auxiliary capacitance with the gate line, an organic resin insulating film covering the switching element and the auxiliary capacitance electrode, and being surrounded by the gate line and the signal line on the organic resin insulating film. Are arranged in a matrix in a region to be connected and connected to the source electrode via through holes formed in the organic resin insulating film. A liquid crystal display device comprising: an array substrate having pixel electrodes; a counter substrate disposed to face the array substrate with a gap therebetween; and a liquid crystal composition sealed between the array substrate and the counter substrate. An auxiliary capacitance electrode is exposed from the organic resin insulating film through a common through hole with the source electrode, and the pixel electrode connected to the source electrode and another pixel electrode adjacent to the pixel electrode with the gate line interposed therebetween. They are connected via through holes.

【0010】上記構成により本発明は、有機樹脂絶縁膜
を貫通してソース電極から補助容量電極に達する単一の
スルーホールを形成して、この単一スルーホールを介し
て前段の画素電極とソース電極或いは次段の画素電極と
補助容量電極との電気的な接続を行い、厚膜の有機樹脂
絶縁膜に形成する1画素電極当たりのスルーホールの数
を1個にして加工数を低減し、しかも単一のスルーホー
ルの加工寸法の拡大により加工性を良くする事により、
製造歩留まりの向上を図り、スルーホール形成不良によ
る点欠陥を防止して液晶表示素子の表示品位の向上を図
るものである。又スルーホールをゲート線上に配置する
事により、液晶表示素子の開口率を拡大し、表示画像の
明るさ及びコントラストを向上して表示品位の向上を図
るものである。
According to the present invention, according to the present invention, a single through-hole extending from a source electrode to an auxiliary capacitance electrode is formed through an organic resin insulating film, and a pixel electrode of a preceding stage is connected to a source through the single through-hole. The electrode or the next stage pixel electrode is electrically connected to the auxiliary capacitance electrode, the number of through holes per pixel electrode formed in the thick organic resin insulating film is reduced to one, and the number of processing is reduced. Moreover, by improving the workability by enlarging the processing size of a single through hole,
An object of the present invention is to improve the production yield, prevent point defects due to defective through-hole formation, and improve the display quality of a liquid crystal display device. Further, by arranging the through-holes on the gate lines, the aperture ratio of the liquid crystal display element is enlarged, and the brightness and contrast of the displayed image are improved to improve the display quality.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施の形態を図1
乃至図4を参照して説明する。17はアクティブマトリ
クス型の液晶表示素子であり、画素電極44のスイッチ
ング素子として画素TFT18を用いるアレイ基板20
と、対向基板21との間に、配向膜22、23を介して
液晶組成物であるネマティック液晶24を封入して成っ
ている。又、26、27は、アレイ基板20及び対向基
板21の外側に夫々貼着される偏光板である。
FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIGS. Reference numeral 17 denotes an active matrix type liquid crystal display element, and an array substrate 20 using the pixel TFT 18 as a switching element of the pixel electrode 44.
And a counter substrate 21, a nematic liquid crystal 24 as a liquid crystal composition is sealed through alignment films 22 and 23. Reference numerals 26 and 27 denote polarizing plates that are attached to the outside of the array substrate 20 and the opposing substrate 21, respectively.

【0012】アレイ基板20は、透明なガラス等からな
る透明絶縁基板28上に多結晶シリコンからなるチャネ
ル領域30a、多結晶シリコンを低抵抗化して成るソー
ス領域30b及びドレイン領域30cを有する半導体層
30がパターン形成され、その上に膜厚100nmの酸
化シリコン(SiOx)等からなるゲート絶縁膜31を
介し、厚さ400nmのタンタル(Ta)、クロム(C
r)、アルミニウム(Al)、モリブデン(Mo)、タ
ングステン(W)、銅(Cu)等金属あるいはこれ等金
属の単体又はその積層膜或いは合金膜からなりゲート電
極32を一体的に形成して成るゲート線33がパターン
形成されている。
The array substrate 20 has a semiconductor layer 30 having a channel region 30a made of polycrystalline silicon and a source region 30b and a drain region 30c made of polycrystalline silicon with low resistance on a transparent insulating substrate 28 made of transparent glass or the like. Is formed thereon, and a 400 nm-thick tantalum (Ta), chromium (C) film is formed thereon via a gate insulating film 31 made of silicon oxide (SiOx) having a thickness of 100 nm.
r), a metal such as aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), or a simple substance of these metals, a laminated film or an alloy film thereof, and the gate electrode 32 is integrally formed. A gate line 33 is patterned.

【0013】これ等の上に成膜される膜厚500nmの
酸化シリコン(SiOx)等の絶縁膜からなる層間絶縁
膜34上には、厚さ500nmのタンタル(Ta)、ク
ロム(Cr)、アルミニウム(Al)、モリブデン(M
o)、タングステン(W)、銅(Cu)等金属あるいは
これ等金属の単体又はその積層膜或いは合金膜からなる
ドレイン電極36aと一体の信号線36、ソース電極3
7、補助容量電極38がパターン形成されている。ドレ
イン電極36a及びソース電極37は、コンタクトホー
ル40、41を介しドレイン領域30c及びソース領域
30bに電気的に接続され、画素電極44を駆動する画
素TFT18を形成している。尚ソース電極37は、こ
のタクトホール41からゲート線33上方に達する様パ
ターン形成されている。
A 500 nm thick tantalum (Ta), chromium (Cr), aluminum, etc. is formed on an interlayer insulating film 34 made of an insulating film such as silicon oxide (SiOx) having a thickness of 500 nm. (Al), molybdenum (M
o), a signal line 36 integrated with a drain electrode 36a made of a metal such as tungsten (W), copper (Cu), or a single or a laminated film or alloy film of these metals, and a source electrode 3
7. The auxiliary capacitance electrode 38 is patterned. The drain electrode 36a and the source electrode 37 are electrically connected to the drain region 30c and the source region 30b via the contact holes 40 and 41, and form the pixel TFT 18 that drives the pixel electrode 44. The source electrode 37 is patterned so as to reach from the tact hole 41 to above the gate line 33.

【0014】これ等の上には、窒化シリコン(SiN
x)等の絶縁膜からなる無機絶縁膜である透明保護絶縁
膜42及び有機樹脂絶縁膜である膜厚3μmの緑
(G)、青(B)、赤(R)の着色絶縁層43が形成さ
れ、更に厚さ100nmのインジウム錫酸化物(以下I
TOと略称する。)からなる画素電極44がパターン形
成されている。そして前段の画素電極44aは、着色絶
縁層43及び透明保護絶縁膜42を貫通してソース電極
37及び補助容量電極38に達するスルーホール47を
介しソース電極37に接続し、次段の画素電極44b
も、スルーホール47を介し補助容量電極38に接続し
ている。
On top of these, silicon nitride (SiN
A transparent protective insulating film 42 which is an inorganic insulating film made of an insulating film such as x) and a colored insulating layer 43 of 3 μm thick green (G), blue (B) and red (R) which is an organic resin insulating film are formed. And a 100 nm-thick indium tin oxide (hereinafter I)
Abbreviated as TO. ) Is formed in a pattern. The previous pixel electrode 44a is connected to the source electrode 37 through a through hole 47 that reaches the source electrode 37 and the auxiliary capacitance electrode 38 through the colored insulating layer 43 and the transparent protective insulating film 42, and is connected to the next pixel electrode 44b.
Are also connected to the auxiliary capacitance electrode 38 through the through hole 47.

【0015】一方対向基板21は、透明なガラス等から
なる透明絶縁基板48上にITOからなる対向電極50
を有している。
On the other hand, a counter substrate 21 is formed by forming a counter electrode 50 made of ITO on a transparent insulating substrate 48 made of transparent glass or the like.
have.

【0016】次に図4を参照してアレイ基板20の製造
方法について述べる。先ず透明絶縁基板28上にCVD
法などによりアモルファスシリコン膜を50nm被着し
て450℃で1時間炉アニールを行った後、XeC1エ
キシマレーザを照射し、アモルファスシリコン膜を多結
晶化して多結晶シリコン膜を形成する。その後に、多結
晶シリコン膜をフォトエッチング法によりパターンニン
グして、表示領域内の画素TFT18の半導体層30を
パターン形成する。
Next, a method of manufacturing the array substrate 20 will be described with reference to FIG. First, the CVD is performed on the transparent insulating substrate 28.
After an amorphous silicon film is deposited to a thickness of 50 nm by a method or the like and annealed at 450 ° C. for 1 hour, XeC1 excimer laser is irradiated to polycrystallize the amorphous silicon film to form a polycrystalline silicon film. Thereafter, the polycrystalline silicon film is patterned by a photo-etching method to form a pattern on the semiconductor layer 30 of the pixel TFT 18 in the display region.

【0017】次に、図4(a)に示すようにCVD法に
より透明絶縁基板28の全面にゲート絶縁膜31となる
酸化シリコン(SiOx)膜を100nm成膜する。続
いて図4(b)に示すようにゲート絶縁膜31上にタン
タル(Ta)、クロム(Cr)、アルミニウム(A
l)、モリブデン(Mo)、タングステン(W)、銅
(Cu)等金属あるいはこれ等金属の単体又はその積層
膜或いは合金膜を成膜し、フォトエッチング法によりゲ
ート電極32及びゲート線33をパターン形成する。次
いでゲート電極32をマスクとして半導体層30のチャ
ネル領域30a両側にイオン注入やイオンドーピング法
により不純物を注入して、ソース領域30b及びドレイ
ン領域30cを形成する。不純物の注入は、例えば加速
電圧80keVで5×1015atoms /cm2 のドーズ量
で、PH3 /H2 (ホスフィン/水素)によりP(リ
ン)を高濃度注入する。その後、透明絶縁基板28をア
ニールすることにより不純物を活性化する。
Next, as shown in FIG. 4A, a silicon oxide (SiOx) film to be the gate insulating film 31 is formed to a thickness of 100 nm on the entire surface of the transparent insulating substrate 28 by the CVD method. Subsequently, as shown in FIG. 4B, tantalum (Ta), chromium (Cr), and aluminum (A) are formed on the gate insulating film 31.
l), a metal such as molybdenum (Mo), tungsten (W), copper (Cu) or a simple substance of these metals or a laminated film or an alloy film thereof is formed, and the gate electrode 32 and the gate line 33 are patterned by photoetching. Form. Next, using the gate electrode 32 as a mask, impurities are implanted into both sides of the channel region 30a of the semiconductor layer 30 by ion implantation or ion doping to form a source region 30b and a drain region 30c. For the impurity implantation, P (phosphorus) is implanted at a high concentration of PH 3 / H 2 (phosphine / hydrogen) at an acceleration voltage of 80 keV and a dose of 5 × 10 15 atoms / cm 2 . After that, impurities are activated by annealing the transparent insulating substrate 28.

【0018】更に図4(c)に示すように、例えばPE
CVD法を用いて透明絶縁基板28の全面に層間絶縁膜
34を成膜し、フォトエッチング法により、層間絶縁膜
34に画素TFT18のドレイン領域30cとソース領
域30bに至るコンタクトホール40、41を形成す
る。次に、タンタル(Ta)、クロム(Cr)、アルミ
ニウム(Al)、モリブデン(Mo)、タングステン
(W)、銅(Cu)等金属あるいはこれ等金属の単体又
はその積層膜或いは合金膜を500nm成膜し、図4
(d)に示すようにフォトエッチング法により所定の形
状にパターニングし、ドレイン電極36aと一体の信号
線36、ソース電極37、補助容量電極38を形成す
る。これにより、コンタクトホール40、41を介し信
号線36と一体のドレイン電極36aはドレイン領域3
0cに電気的に接続され、ソース電極37はソース領域
30bに電気的に接続される。
Further, as shown in FIG.
An interlayer insulating film 34 is formed on the entire surface of the transparent insulating substrate 28 by using the CVD method, and contact holes 40 and 41 reaching the drain region 30c and the source region 30b of the pixel TFT 18 are formed in the interlayer insulating film 34 by the photoetching method. I do. Next, a metal such as tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), a single element of these metals, or a laminated film or an alloy film thereof is formed to a thickness of 500 nm. Film and Figure 4
As shown in FIG. 3D, patterning is performed into a predetermined shape by a photoetching method to form a signal line 36, a source electrode 37, and an auxiliary capacitance electrode 38 integrated with the drain electrode 36a. As a result, the drain electrode 36a integrated with the signal line 36 via the contact holes 40 and 41 is
0c, and the source electrode 37 is electrically connected to the source region 30b.

【0019】次にPECVD法により図4(e)に示す
ように、透明絶縁基板28の全面に窒化シリコン(Si
Nx)からなる透明保護絶縁膜42を成膜し、図4
(f)に示すようにフォトエッチング法により透明保護
絶縁膜42に、ゲート線33上にてソース電極37から
補助容量電極38に達するスルーホール47の第1の部
分47aを形成する。更にPECVD法により図4
(g)に示すように着色絶縁層43を成膜し、図4
(h)に示すようにフォトエッチング法により着色絶縁
層43にソース電極37及び補助容量電極38に達する
スルーホール47の第2の部分47bを形成してスルー
ホール47を貫通する。これ等の上にITOをスパッタ
法により100nm成膜し、フォトエッチング法により
所定の形状にパターンニングして、図4(i)に示すよ
うに画素電極44を形成する。これにより、スルーホー
ル47を介し前段の画素電極44aはソース電極37に
電気的に接続し、次段の画素電極44bは補助容量電極
38に電気的に接続する。
Next, as shown in FIG. 4E, silicon nitride (Si) is formed on the entire surface of the transparent insulating substrate 28 by PECVD.
Nx) is formed on the transparent protective insulating film 42, and FIG.
As shown in (f), a first portion 47a of a through hole 47 extending from the source electrode 37 to the auxiliary capacitance electrode 38 on the gate line 33 is formed in the transparent protective insulating film 42 by photoetching. Further, FIG.
As shown in FIG. 4G, a colored insulating layer 43 is formed, and FIG.
As shown in (h), the second portion 47b of the through hole 47 reaching the source electrode 37 and the auxiliary capacitance electrode 38 is formed in the colored insulating layer 43 by photoetching and penetrates the through hole 47. A 100 nm ITO film is formed thereon by sputtering, and is patterned into a predetermined shape by photoetching to form a pixel electrode 44 as shown in FIG. As a result, the previous pixel electrode 44a is electrically connected to the source electrode 37 via the through hole 47, and the next pixel electrode 44b is electrically connected to the auxiliary capacitance electrode 38.

【0020】次に対向基板21にあっては、透明絶縁基
板48上にスパッタ法によりITOから成る対向電極5
0を全面に形成する。そしてアレイ基板20及び対向基
板21の対向面に、夫々低温キュア型のポリイミドから
なる配向膜22、23を印刷塗布し、両基板22、23
の対向時に配向軸が90゜となるようにラビング処理を
した後、両基板20、21を対向して組み立て、セル化
してその間隙にネマティック液晶24を注入し封止す
る。そして、両基板20、21の透明絶縁基板28、4
8側に偏光板26、27を貼り付けることにより液晶表
示素子17を形成する。
Next, in the counter substrate 21, the counter electrode 5 made of ITO is formed on the transparent insulating substrate 48 by a sputtering method.
0 is formed on the entire surface. Then, alignment films 22 and 23 made of a low-temperature cure type polyimide are printed and applied to the opposing surfaces of the array substrate 20 and the opposing substrate 21, respectively.
After the rubbing process is performed so that the alignment axis becomes 90 ° when the substrates are opposed to each other, the two substrates 20 and 21 are assembled facing each other, formed into cells, and a nematic liquid crystal 24 is injected into the gap therebetween and sealed. Then, the transparent insulating substrates 28, 4 of the two substrates 20, 21
The liquid crystal display element 17 is formed by attaching polarizing plates 26 and 27 to the 8 side.

【0021】この様に構成すれば、前段の画素電極44
aとソース電極37との接続及び、次段の画素電極44
bと補助容量電極38との接続のための1画素当たりの
スルーホール47が単一である事から、着色絶縁層43
が厚膜であり、スルーホール47の加工が難しくても、
その加工数を従来に比し半減する事により製造歩留まり
を向上出来る。しかもスルーホール47は、ソース電極
37及び補助容量電極38に共通であり、従来の様にソ
ース電極及び補助容量電極夫々に個別に形成するものに
比し加工寸法が拡大される事により加工性を向上出来る
事からも、形成不良による点欠陥などの表示不良を生じ
る事もなく、歩留まりの向上を図れる。
With this configuration, the pixel electrode 44 in the preceding stage
a and the source electrode 37 and the next stage pixel electrode 44
Since the single through hole 47 per pixel for connection between b and the auxiliary capacitance electrode 38 is single, the colored insulating layer 43
Is a thick film, and it is difficult to process the through hole 47,
The production yield can be improved by halving the number of processes compared to the conventional one. In addition, the through hole 47 is common to the source electrode 37 and the auxiliary capacitance electrode 38, and the processability is increased by increasing the processing size as compared with the conventional case where the source electrode and the auxiliary capacitance electrode are individually formed. Because of the improvement, the display yield such as a point defect due to the formation failure does not occur, and the yield can be improved.

【0022】更にソース電極37を画素電極44内のソ
ース領域30bからゲート線33上方に延在するよう配
線して、加工面積の大きいスルーホール47を、画素電
極44内では無くゲート線33上方に配置する事によ
り、ゲート線33がスルーホール47の遮光を兼ねるこ
ととなり、画素電極44内にスルーホール47のための
遮光領域を設ける必要が無い事から、液晶表示素子17
の開口率を向上出来、より明るくコントラストの良い表
示画像を得られ、表示品位を向上出来る。
Further, the source electrode 37 is wired so as to extend from the source region 30b in the pixel electrode 44 above the gate line 33, and a through hole 47 having a large processing area is formed not in the pixel electrode 44 but above the gate line 33. By arranging, the gate line 33 also serves as a light shield for the through hole 47, and there is no need to provide a light shield area for the through hole 47 in the pixel electrode 44.
Aperture ratio can be improved, a brighter and higher-contrast display image can be obtained, and display quality can be improved.

【0023】尚本発明は上記実施の形態に限られるもの
ではなく、その趣旨を変えない範囲での変更は可能であ
って、例えば、着色絶縁層及び透明保護絶縁膜を貫通し
て成る単一のスルーホールの配置位置はゲート線上方に
限られる事無く、画素電極内に配置されていても良い。
又、スルーホールの形状も厚膜で加工し難い着色絶縁層
の部分が単一であれば良く、図5及び図6に示す変形例
の様に、信号線36、ソース電極37、補助容量電極3
8上の透明保護絶縁膜42にあっては、ゲート線33上
方にてソース電極37に達する第1のスルーホール51
及び補助容量電極38に達する第2のスルーホール52
を夫々に形成する一方、着色絶縁層43にあっては、第
1のスルーホール51及び第2のスルーホール52上方
にてソース電極37及び補助容量電極38に達する単一
の第3のスルーホール53を形成する事により、第1の
スルーホール51及び第3のスルーホール53を介して
前段の画素電極44aをソース電極37に接続し、第2
のスルーホール52及び第3のスルーホール53を介し
て次段の画素電極44bを補助容量電極38に接続して
も良い。この様に形成すれば、厚膜の着色絶縁層43に
形成される第3のスルーホール53は1画素当たり1個
であることから、従来の装置に比し製造歩留まり向上を
図れる。
The present invention is not limited to the above-described embodiment, and can be modified without departing from the spirit of the invention. The arrangement position of the through-hole is not limited to the position above the gate line, and may be arranged in the pixel electrode.
Further, the shape of the through hole may be a thick film and the portion of the colored insulating layer, which is difficult to process, may be a single part. As in the modification shown in FIGS. 5 and 6, the signal line 36, the source electrode 37, the auxiliary capacitance electrode 3
8, the first through-hole 51 reaching the source electrode 37 above the gate line 33.
And second through hole 52 reaching auxiliary capacitance electrode 38
Are formed respectively, and in the colored insulating layer 43, a single third through hole reaching the source electrode 37 and the auxiliary capacitance electrode 38 above the first through hole 51 and the second through hole 52. By forming the pixel electrode 53, the pixel electrode 44 a in the preceding stage is connected to the source electrode 37 via the first through hole 51 and the third through hole 53, and the second
The pixel electrode 44b at the next stage may be connected to the auxiliary capacitance electrode 38 through the through hole 52 and the third through hole 53. With such a configuration, the number of the third through holes 53 formed in the thick colored insulating layer 43 is one per pixel, so that the production yield can be improved as compared with the conventional device.

【0024】又アレイ基板の構造も任意であり、画素T
FTの半導体層をアモルファスシリコンで形成しても良
いし、着色絶縁層が透明絶縁層を兼用し、ソース電極及
び補助容量電極を絶縁するため、透明絶縁層を介する事
無くソース電極及び補助容量電極上に着色絶縁層を直接
成膜する等しても良い。
The structure of the array substrate is also optional.
The FT semiconductor layer may be formed of amorphous silicon, or the colored insulating layer may also serve as the transparent insulating layer and insulate the source electrode and the auxiliary capacitance electrode. A colored insulating layer may be directly formed thereon.

【0025】[0025]

【発明の効果】以上説明したように本発明によれば、有
機樹脂絶縁膜のスルーホールを1画素当たり1個とし、
この単一のスルーホールを介して前段の画素電極とソー
ス電極との接続及び、次段の画素電極と補助容量電極と
の接続を行う事により、厚膜で加工の難しい有機樹脂絶
縁膜におけるスルーホールの加工数を従来に比し半減出
来、アレイ基板の製造歩留まりを従来に比し向上出来
る。更にスルーホールを個別に形成していた場合に比
し、スルーホールの加工寸法を拡大出来るので、加工性
が良くなり形成不良による点欠陥などの表示不良を低減
出来る事からも製造歩留まりの向上を図れる。
As described above, according to the present invention, the number of through holes in the organic resin insulating film is one per pixel,
By connecting the pixel electrode in the previous stage and the source electrode and connecting the pixel electrode in the next stage and the auxiliary capacitance electrode through this single through-hole, the through-hole in the organic resin insulating film which is thick and difficult to process is formed. The number of holes to be processed can be reduced by half compared with the conventional case, and the production yield of the array substrate can be improved as compared with the conventional case. Furthermore, as compared with the case where the through holes are individually formed, the processing dimensions of the through holes can be enlarged, so that the processability is improved and the display defects such as point defects due to the formation defects can be reduced, thereby improving the production yield. I can do it.

【0026】又ソース電極をゲート線上方迄延在して、
ゲート線上方にてソース電極に対するスルーホールを形
成する事により、画素電極内の遮光領域を縮小出来る。
これにより液晶表示素子の開口率を向上出来、より明る
くコントラストの良い表示画像を得られ、表示品位向上
を図れる。
The source electrode extends to above the gate line,
By forming a through-hole for the source electrode above the gate line, the light-shielding region in the pixel electrode can be reduced.
As a result, the aperture ratio of the liquid crystal display element can be improved, a brighter and higher-contrast display image can be obtained, and the display quality can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態のアレイ基板を示す一部概
略平面図である。
FIG. 1 is a partial schematic plan view showing an array substrate according to an embodiment of the present invention.

【図2】本発明の実施の形態のアレイ基板に形成される
スルーホール部分を示す概略平面図である。
FIG. 2 is a schematic plan view showing a through hole portion formed in the array substrate according to the embodiment of the present invention.

【図3】本発明の実施の形態の液晶表示素子を示す図2
のA−A‘線における概略断面図である。
FIG. 3 shows a liquid crystal display element according to an embodiment of the present invention.
3 is a schematic sectional view taken along line AA ′ of FIG.

【図4】本発明の実施の形態のアレイ基板の製造工程を
示し、(a)はそのゲート絶縁膜成膜時、(b)はその
ゲート線形成時、(c)はその層間絶縁膜成膜時、
(d)はそのソース電極、補助容量電極形成時、(e)
はその透明保護絶縁膜成膜時、(f)はそのスルーホー
ルの第1の部分形成時、(g)はその着色絶縁膜成膜
時、(h)はそのスルーホールの第2の部分形成時、
(i)はその画素電極形成時を示す概略説明図である。
4A to 4C show a manufacturing process of an array substrate according to an embodiment of the present invention, wherein FIG. 4A shows a process of forming a gate insulating film, FIG. 4B shows a process of forming a gate line, and FIG. At the time of membrane,
(D) shows the state when the source electrode and the auxiliary capacitance electrode are formed, and (e)
(F) shows the formation of the first portion of the through hole, (g) shows the formation of the colored insulating film, and (h) shows the formation of the second portion of the through hole. Time,
(I) is a schematic explanatory view showing the time when the pixel electrode is formed.

【図5】本発明の他の変形例のアレイ基板に形成される
スルーホール部分を示す概略平面図である。
FIG. 5 is a schematic plan view showing a through hole formed in an array substrate according to another modification of the present invention.

【図6】本発明の他の変形例の液晶表示素子を示す図5
B−B‘線における概略断面図である。
FIG. 6 shows a liquid crystal display device according to another modification of the present invention.
It is a schematic sectional drawing in the BB 'line.

【図7】従来のアレイ基板を示す一部概略平面図で有
る。
FIG. 7 is a partial schematic plan view showing a conventional array substrate.

【図8】従来の液晶表示素子を示す図7のC−C‘線に
おける概略断面図である。
FIG. 8 is a schematic cross-sectional view taken along line CC ′ of FIG. 7 showing a conventional liquid crystal display element.

【符号の説明】[Explanation of symbols]

17…液晶表示素子 18…画素TFT 20…アレイ基板 21…対向基板 22、23…配向膜 24…ネマティック液晶 26、27…偏光板 28…透明絶縁基板 30…半導体層 31…ゲート絶縁膜 32…ゲート電極 33…ゲート線 34…層間絶縁膜 36…信号線 37…ソース電極 38…補助容量電極 40、41…コンタクトホール 42…透明保護絶縁膜 43…着色絶縁膜 44…画素電極 47…スルーホール 48…透明絶縁基板 50…対向基板 DESCRIPTION OF SYMBOLS 17 ... Liquid crystal display element 18 ... Pixel TFT 20 ... Array substrate 21 ... Opposite substrate 22, 23 ... Alignment film 24 ... Nematic liquid crystal 26, 27 ... Polarizer 28 ... Transparent insulating substrate 30 ... Semiconductor layer 31 ... Gate insulating film 32 ... Gate Electrode 33 ... Gate line 34 ... Interlayer insulating film 36 ... Signal line 37 ... Source electrode 38 ... Auxiliary capacitance electrode 40, 41 ... Contact hole 42 ... Transparent protective insulating film 43 ... Colored insulating film 44 ... Pixel electrode 47 ... Through hole 48 ... Transparent insulating substrate 50: Counter substrate

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板上にゲート線と、このゲート線
と交差するよう配線される信号線と、前記ゲート線及び
前記信号線の交点に配列され少なくとも、チャネル領域
を挟みソース領域及びドレイン領域を有する半導体層、
前記ゲート線と一体のゲート電極、前記ソース領域に接
続されるソース電極並びに前記ドレイン領域に接続され
るドレイン電極を有するスイッチング素子と、前記ゲー
ト線と補助容量を形成する補助容量電極と、前記スイッ
チング素子及び前記補助容量電極を被覆する有機樹脂絶
縁膜と、この有機樹脂絶縁膜上の前記ゲート線及び前記
信号線に囲まれる領域にマトリクス状に配置され前記有
機樹脂絶縁膜に形成されたスルーホールを介して前記ソ
ース電極に接続される複数の画素電極を有するアレイ基
板と、 前記アレイ基板に間隙を隔てて対向配置される対向基板
と、 前記アレイ基板及び前記対向基板間に封入される液晶組
成物とを具備する液晶表示装置において、 前記補助容量電極が前記ソース電極と共通のスルーホー
ルを介して前記有機樹脂絶縁膜より露出され、かつ前記
ソース電極に接続された画素電極と前記ゲート線を挟ん
で隣接する他の画素電極に対し前記スルーホールを介し
て接続されている事を特徴とするアクティブマトリクス
型液晶表示素子。
1. A gate line on an insulating substrate, a signal line wired to cross the gate line, and a source region and a drain region arranged at an intersection of the gate line and the signal line with at least a channel region interposed therebetween. A semiconductor layer having
A switching element having a gate electrode integral with the gate line, a source electrode connected to the source region, and a drain electrode connected to the drain region; an auxiliary capacitance electrode forming an auxiliary capacitance with the gate line; An organic resin insulating film covering the element and the auxiliary capacitance electrode; and a through hole formed in the organic resin insulating film and arranged in a matrix on a region of the organic resin insulating film surrounded by the gate line and the signal line. An array substrate having a plurality of pixel electrodes connected to the source electrode via a counter electrode; a counter substrate disposed to face the array substrate with a gap therebetween; and a liquid crystal composition sealed between the array substrate and the counter substrate. In the liquid crystal display device, the auxiliary capacitance electrode is provided through a common through hole with the source electrode. An active matrix type wherein the pixel electrode is exposed from a resin insulating film and is connected to another pixel electrode adjacent to the pixel electrode connected to the source electrode with the gate line interposed therebetween through the through hole. Liquid crystal display element.
【請求項2】 ソース電極はゲート線と重畳する位置ま
で延在される事を特徴とする請求項1に記載のアクティ
ブマトリクス型液晶表示素子。
2. The active matrix type liquid crystal display device according to claim 1, wherein the source electrode extends to a position overlapping the gate line.
【請求項3】 スルーホールはゲート線の内側の領域上
に形成される事を特徴とする請求項2に記載のアクティ
ブマトリクス型液晶表示素子。
3. The active matrix liquid crystal display device according to claim 2, wherein the through hole is formed on a region inside the gate line.
【請求項4】 有機樹脂絶縁膜とソース電極及び補助容
量電極の層間には無機絶縁膜が形成され、前記ソース電
極及び前記補助容量電極はそれぞれに対応して形成され
たスルーホールを介して前記無機絶縁膜より露出される
事を特徴とする請求項1に記載のアクティブマトリクス
型液晶表示素子。
4. An inorganic insulating film is formed between the organic resin insulating film and the source electrode and the storage capacitor electrode, and the source electrode and the storage capacitor electrode are formed through correspondingly formed through holes. 2. The active matrix type liquid crystal display device according to claim 1, wherein the active matrix type liquid crystal display device is exposed from an inorganic insulating film.
【請求項5】 有機樹脂絶縁膜は着色層であることを特
徴とする請求項1乃至請求項4のいずれかに記載のアク
ティブマトリクス型液晶表示素子。
5. The active matrix liquid crystal display device according to claim 1, wherein the organic resin insulating film is a colored layer.
JP13512598A 1998-05-18 1998-05-18 Active matrix type liquid crystal display device Expired - Fee Related JP4031105B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13512598A JP4031105B2 (en) 1998-05-18 1998-05-18 Active matrix type liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13512598A JP4031105B2 (en) 1998-05-18 1998-05-18 Active matrix type liquid crystal display device

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656468B2 (en) 2005-06-30 2010-02-02 Hitachi Displays, Ltd. Display device and manufacturing method of the display device
US7839476B2 (en) 2006-05-31 2010-11-23 Hitachi Displays, Ltd. Display device
CN103616785A (en) * 2013-11-08 2014-03-05 友达光电股份有限公司 Pixel array
EP2933680A4 (en) * 2012-12-13 2016-08-17 Beijing Boe Optoelectronics Array substrate, liquid crystal display panel and driving method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656468B2 (en) 2005-06-30 2010-02-02 Hitachi Displays, Ltd. Display device and manufacturing method of the display device
US7839476B2 (en) 2006-05-31 2010-11-23 Hitachi Displays, Ltd. Display device
EP2933680A4 (en) * 2012-12-13 2016-08-17 Beijing Boe Optoelectronics Array substrate, liquid crystal display panel and driving method
CN103616785A (en) * 2013-11-08 2014-03-05 友达光电股份有限公司 Pixel array
CN103616785B (en) * 2013-11-08 2016-04-20 友达光电股份有限公司 Pixel array

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