JPH11326452A - Test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate a link with a logic simulator by giving an edge signal which a timing generator outputs to a plurality of pin electronics and carrying out a test of an object to be tested based on the edge signal and a pattern data. SOLUTION: A clock which a master clock generator OSC generates is counted by a time counter TC. Then, when the count value and a period time data are coincident in a control circuit, a time signal pulse is outputted. A timing generator TG delays the time signal pulse by a fraction time data and outputs an edge signal. The edge signal is given to a plurality of pin electronics PE1-PE512 and a test of an object to be tested is carried out. Thereby, since it is not necessary to provide a rate generator, it is not necessary to divide a test by a rate unit. Namely, a link with a logic simulator can be easily carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test system for testing a device under test, and more particularly to a test system which can be easily linked to a logic simulator.

[0002]

2. Description of the Related Art A test system is provided with a test object I
A test signal is output to C or the like, and a signal from the test object is compared with an expected value. The test system includes a per-pin generator method, a shared timing generator method, and a per-pin sequencer method.

[0003] The per-pin timing generator method is as follows.
In this system, a timing generator is provided for each pin of the IC. The shared timing generator method has several timing generators, selects an edge from among the pins of the IC, and performs a test using the edge. The per-pin sequencer method is a method having an event sequencer for each pin. Such a device is described in "Developing an LSI Tester that System Designers Can Handle", Nikkei Electronics, 1993.3.1 (No. 575), pp1.
57-180. The perpin sequencer method is shown in FIG. 7 and will be described.

In FIG. 1, a master clock generator OSC
Generates a clock. The rate generator RG receives a clock from the master clock generator OSC and outputs a rate signal. Event sequencer IS1-IS512
Is provided for each pin of the device under test (not shown), receives a rate signal from the rate generator RG and a function signal, stores an event sequence for each pin, and outputs a signal. The event sequence is the content of the event that occurs (rising and falling of the signal)
And a sequence of a set of the event occurrence time. Each of the pin electronics PE1 to PE512 has a driver (not shown) and a comparator (not shown), receives signals from the sequencers IS1 to IS512, respectively, and performs a test on a device under test.

Further, the event sequencer IS1 will be described in detail.
The specific configuration of IS512 is shown below. FIG. 8 is a diagram showing a specific configuration of the event sequencers IS1 to IS512. In the figure, an event memory 1 stores an event time and an event type, is selected by a function signal, and outputs it. The signal generator 2 receives the rate signal, and generates a signal based on the event time and the event type from the event memory 1.

The operation of such a device will be described below.
FIG. 9 is a timing chart showing the operation of the device of FIG. At time t0, the test system starts operating, and the master clock generator OSC generates a clock. The clock is input to the rate generator RG and a rate signal is output. At this time, the event memory 1 of the event sequencers IS1 and IS2 stores the event time “1.25” and the event type “
1 ”. Event sequencers IS3 and IS5
In the event memory 1, the event time “1.25”
And the event type “L”.

The signal generator 2 of the event sequencers IS1 and IS2 outputs "1.25" from the rise of the rate signal at time t0 due to the event time "1.25" and the event type "1". , Raise the signal. This signal is transmitted to pin electronics PE1 and PE2.
Output to the device under test through the driver.

The event sequencer IS3, IS
Due to the event time “1.25” and the event type “L”, the signal generator 2 of 512 transmits “1.25” from the rise of the rate signal at time t0, and then outputs the pin electronics PE3 and PE512. The comparator outputs a strobe signal and an expected value "L" to the comparator. The comparators of the pin electronics PE3 and PE512 are
Input a signal from the device under test, compare it with the expected value "L",
Latched by strobe signal.

At times t1 to t4, the master clock generator OSC outputs a clock to the rate generator RG in each case. Then, the rate generator RG causes the rate signal to fall at time t2, and causes it to rise again at time t4.

At time t4, the function signal changes, and the event memories 1 of the event sequencers IS1 and IS2 store event times "2.25" and "2."
0.75 "and the event types" 0 "and" 0 ". The event memories 1 of the event sequencers IS3 and IS512 store event times" 0.75 "and" 0.75 ", respectively.
0.75 ”and the event types“ H ”and“ L ”are output.

The signal generator 2 of the event sequencer IS2
Indicates the event time “0.75” and the event type “0”
From the rise of the rate signal at time t4,
After 0.75 "has elapsed, the signal falls. This signal is output to the device under test via the drivers of the pin electronics PE1 and PE2.

The event sequencers IS3 and IS
The 512 signal generators 2 respectively output event times “0.
75 ”,“ 0.75 ”and event type“ H ”,“ L ”
From the rise of the rate signal at time t4,
After 0.75 ", Pin Electronics PE
3. Outputs a strobe signal to the comparator of the PE 512 and expected values “H” and “L”. The comparators of the pin electronics PE3 and PE512 receive a signal from the device under test, compare it with expected values “H” and “L”, and latch the signal with a strobe signal.

At time t5, the function signal changes and the event memory 1 of the event sequencer IS2
Indicates the event time “2.25” and the event type “1”
Is output. Event sequencer IS3, IS512
The event memory 1 outputs the event time “2.25” and the event type “H”. At this time, the output of the event memory 1 of the event sequencer IS1 does not change.

The signal generator 2 of the event sequencer IS1
Indicates the event time “2.25” and the event type “0”
From the rise of the rate signal at time t4,
After 2.25 "has elapsed, the signal falls. This signal is output to the device under test via the driver of the pin electronics PE1.

The signal generator 2 of the event sequencer IS2
Indicates the event time “2.25” and the event type “1”
From the rise of the rate signal at time t4,
The signal rises after 2.25 ″ has elapsed. This signal is output to the device under test via the driver of the pin electronics PE2.

The event sequencers IS3 and IS
In response to the event time “2.25” and the event type “H”, the signal generator 2 of 512 generates “2.25” from the rise of the rate signal at time t4 and then outputs the pin electronics PE3 and PE512. The comparator outputs a strobe signal and an expected value “H” to the comparator. The comparators of the pin electronics PE3 and PE512 are
Input a signal from the device under test, compare it with the expected value "H",
Latched by strobe signal. Here, the comparator of the pin electronics PE3 has failed.

[0017]

In order to easily link with a logic simulator, a simple method of keeping all the patterns for each pin as is is conceivable. However, an enormous amount of memory is required. In particular, the data of the event occurrence time may exceed 32 bits, which is several tens of times larger than 1-3 bits of general tester pattern data.

In order to avoid this, the perpin sequencer type tester shown in FIG. 7 employs a means for dividing an event sequence at a rate of a certain length. An explosion of the event memory is avoided by adopting a form of repeatedly starting while selecting from a limited number of sequences for each rate by a function signal.

For this reason, for example, it is necessary to synchronize the rate signal every time an event sequence in units of 200 events occurs, and it is not completely released from the rate signal, and linking with an event-driven simulator is completely facilitated. I did not go until.

Also, if the sequence-per-pin tester is completely event driven in order to facilitate linking with the simulator, there is a problem that the amount of memory becomes enormous as described above.

An object of the present invention is to realize a test system that can be easily linked to a logic simulator and requires a small amount of memory.

[0022]

According to the present invention, in a test system for testing a device under test, a master clock generator for outputting a clock having a constant period, and at least one clock for counting the clock output from the master clock generator are provided. Two time counters, storing time data and pattern data of two or more pins for the device under test, comparing the count value of the time counter with time data, outputting a time signal pulse, and generating a fraction of the time data. At least one event sequencer that outputs time data and pattern data, and a time signal pulse and fractional time data that are provided for each event sequencer and output by the event sequencer are input, and the time signal pulse is delayed by the fractional time data. , A timing generator that outputs an edge signal, and this timing It has two or more pin electronics for inputting an edge signal from a creature and pattern data from the event sequencer and performing a test on the device under test based on the edge signal and the pattern data. Things.

According to the present invention, the clock generated by the master clock generator is counted by the time counter. Then, the event sequencer compares the count value of the time counter with the time data, outputs a time signal pulse, and outputs fractional time data and pattern data. A timing generator delays the time signal pulse by the fractional time data and outputs an edge signal. The pin electronics tests the device under test based on the edge signal and the pattern data.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the present invention.
In the figure, a master clock generator OSC outputs a clock having a constant period. The time counter TC counts the clock output from the master clock generator OSC. The event sequencer IS stores time data and pattern data of two or more pins for a device under test (not shown), compares the count value of the time counter with time data (periodic time data), and when they match, a time signal pulse. And outputs the fractional time data of the time data and the pattern data.

The event sequencer IS has an event memory M and a control circuit C. The event memory M stores pattern data and time data.

The pattern data is set for each pin, and includes a driver output value, a comparator expected value (high level, low level, mask (whatever), etc.)
This is a 3-bit information amount. The time data includes cycle time data that is a multiple of the cycle of the clock and fractional time data that is shorter than the cycle of the clock, and represents the time at which the event occurs. For example, even if the value on the 64-bit data bus changes slightly, even if there is a slight deviation, there is an error in the test timing due to the skew in the test system. Even if they are shifted, the same time can be set. That is,
If events at times within an error range that can be tolerated by the test system are put together, the event memory M consumption can be reduced by writing to the event memory M.

The control circuit C compares the count value of the time counter TC with the time data (periodic time data) of the event memory M, and outputs a time signal pulse when they match with each other. Control.

The timing generator TG receives the time signal pulse and the fraction time data output from the event sequencer IS, delays the time signal pulse by the fraction time data, and outputs an edge signal. Pin electronics PE1 to 51
2 is provided at each pin to be tested, receives an edge signal from the timing generator TG and pattern data from the event sequencer IS, and tests the test target based on the edge signal and the pattern data. I do.

An embodiment of the present invention will be described with reference to FIG. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, the event sequencer IS includes a time counter TC, an event memory M, an address counter 11, and a coincidence detector 12.

The address counter 11 increments each time signal pulse and designates an address in the event memory M. The coincidence detector 12 calculates the count value of the time counter TC and the time data (cycle time data) of the event memory M.
If coincides, a time signal pulse is output. That is, the address counter 11 and the coincidence detector 12 are the control circuit C of the embodiment shown in FIG.

The timing generator TG comprises a retiming register 13 and a variable delay generator 14. The retiming register 13 receives a time signal pulse and performs retiming with a clock from the master clock generator OSC. The variable delay generator 14 delays the pulse from the retiming register 13 by fractional time data and outputs an edge signal to the pin electronics PE1 to PE512.

Pin electronics PE1 to PE512
Are divided into a driver side and a comparator side, but an actual test system generally includes both.

The pin electronics PE1 and PE2 are
It comprises AND gates 15, 16, a set / reset latch 17, and a driver DRV. The AND gate 15 outputs a logical product of the pattern data from the event memory M and the edge signal from the timing generator TG. The AND gate 16 outputs the logical product of the negative logic of the pattern data from the event memory M and the edge signal from the timing generator TG. The set / reset latch 17
The output of the gate 15 is input to the set terminal, and the output of the AND gate 16 is input to the reset terminal. Driver DRV
Inputs the output of the set / reset latch 17 and adjusts and outputs the voltage to the DUT under test. AND gate 1
5, 16 and the set / reset latch 17 constitute a formatter.

Pin electronics PE3 to PE512
Comprises a digital comparator CMP and a D flip-flop 18. The digital comparator CMP compares the output of the DUT under test with the pattern data from the event memory M and outputs the result. D flip-flop 18
Latches the comparison result of the digital comparator CMP with an edge signal (strobe signal) from the timing generator TG. The digital comparator CMP and the D flip-flop 18 constitute a comparison unit.

The operation of such a device will be described below.
FIG. 3 is a timing chart showing the operation of the apparatus shown in FIG.

At time t0, the test system starts operating, the count value of the time counter TC is "0", and the address counter 11 indicates the first address. As a result, the event memory M stores the pattern data “
1 ”,“ 1 ”,“ L ”,...,“ L ”
The time data "1.25" is output. The time data is "
“1” is periodic time data, and “0.25” is fractional time data.

At time t1, the time counter TC inputs the clock of the master clock generator OSC and changes the count value to "1". Then, the coincidence detector 12
Outputs a time signal pulse because the cycle time data "1" matches the count value "1". With this time signal pulse, the address counter 11 increments the address.

Then, the retiming register 13 retiming the time signal pulse from the coincidence detector 12 by the clock from the master clock generator OSC. The variable delay generator 14 outputs the edge signal by delaying the output of the retiming register 13 by the fractional time data “0.25”.

The pin electronics PE1 and PE2 are
Since the pattern data (driver output value) is "1" and the same, the same operation is performed. This will be described below. AND gate 1
5 inputs an edge signal to the set terminal of the set / reset latch 17 based on the pattern data "1" and the edge signal, and causes the signal to rise. And AND gate 1
No. 6 does not output an edge signal because the negative logic of the pattern data “1” and the edge signal are input. Driver D
The RV adjusts the voltage of the signal from the set / reset latch 17 and outputs it to the DUT under test.

Pin electronics PE3, PE512
Performs the same operation because the pattern data (comparator expected value) is the same at "L". This will be described below. The digital comparator CMP compares the pattern data “L” with the output of the DUT under test, and outputs the comparison result (pass) because the output of the DUT under test is at a low level. The D flip-flop 18 latches the output of the digital comparator CMP with an edge signal (strobe signal).

At time t2, the time counter TC counts the clock output from the master clock generator OSC.
The count value is changed to “2”. At the same time, in the event memory M, since the address of the address counter 11 is changed by the time signal pulse, the pattern data “1”, “1”
0, “H”,..., “L” and time data “4.75”, where “4” is periodic time data and “0.75” is fractional time data. It is.

The coincidence detector 12 outputs the cycle time data “4”.
Is compared with the counter value "2". Since they do not match, nothing is performed. At time t3, nothing changes.

At time t4, the time counter TC inputs the clock of the master clock generator OSC and changes the count value to "4". Then, the coincidence detector 12
Outputs a time signal pulse because the cycle time data “4” matches the count value “4”. With this time signal pulse, the address counter 11 increments the address.

Then, the retiming register 13 retiming the time signal from the coincidence detector 12 by the clock from the master clock generator OSC. The variable delay generator 14 outputs the edge signal by delaying the output of the retiming register 13 by the fractional time data “0.75”.

First, the operation of the pin electronics PE1 will be described. The AND gate 15 outputs the pattern data "
1 ”and the edge signal, the set / reset latch 17
The edge signal is input to the set terminal of, and the signal rises. However, the signal output from the set / reset latch 17 remains unchanged, so that nothing is changed. The AND gate 16 outputs the pattern data "
Since the negative logic of 1 ″ and the edge signal are input, the edge signal is not output. The driver DRV adjusts the voltage of the signal from the set / reset latch 17 so that the DUT D
Output to UT.

Next, the operation of the pin electronics PE2 will be described. The AND gate 15 outputs the pattern data "
Since the edge signal is input to the AND gate 16, the edge signal is not output, and the AND gate 16 receives the negative logic of the pattern data "0" and the edge signal. The driver DRV adjusts the voltage of the signal from the set / reset latch 17 so that the signal falls,
Output to the DUT under test.

The pin electronics PE3 performs the following operation. The digital comparator CMP compares the pattern data “H” with the output of the DUT under test, and outputs the comparison result (pass) since the output of the DUT under test is at a high level. The D flip-flop 18 latches the output of the digital comparator CMP with an edge signal (strobe signal).

The pin electronics PE 512 performs the following operation. The digital comparator CMP compares the pattern data “L” with the output of the DUT under test,
Since the output of the DUT under test is at a low level, a comparison result (pass) is output. The D flip-flop 18
The output of the digital comparator CMP is latched by an edge signal (strobe signal).

At time t5, the time counter TC counts the clock output from the master clock generator OSC.
The count value “5” is changed. At the same time, in the event memory M, since the address of the address counter 11 is changed by the time signal pulse, the pattern data “0”, “
1 ”,“ H ”,...,“ H ”and time data“ 6.25 ”, where“ 6 ”is periodic time data and“ 0.25 ”is fractional time data. It is.

The coincidence detector 12 outputs the cycle time data “6”.
Is compared with the counter value "5", and since they do not match, nothing is performed.

At time t6, the time counter TC inputs the clock of the master clock generator OSC and changes the count value to "6". Then, the coincidence detector 12
Outputs a time signal pulse because the cycle time data “6” matches the count value “6”. With this time signal pulse, the address counter 11 increments the address.

Then, the retiming register 13 retiming the time signal from the coincidence detector 12 by the clock from the master clock generator OSC. The variable delay generator 14 outputs the edge signal by delaying the output of the retiming register 13 by the fractional time data “0.25”.

First, the operation of the pin electronics PE1 will be described. The AND gate 15 outputs the pattern data "
Since the edge signal is input to the AND gate 16, the edge signal is not output, and the AND gate 16 receives the negative logic of the pattern data "0" and the edge signal. The driver DRV adjusts the voltage of the signal from the set / reset latch 17 so that the signal falls,
Output to the DUT under test.

Next, the pin electronics PE2 performs the following operation. The AND gate 15 outputs the pattern data "
1 ”and the edge signal, the set / reset latch 17
The edge signal is input to the set terminal of, and the signal rises. The AND gate 16 outputs the pattern data "
Since the negative logic of 1 ″ and the edge signal are input, the edge signal is not output. The driver DRV adjusts the voltage of the signal from the set / reset latch 17 so that the DUT D
Output to UT.

The pin electronics PE3 performs the following operation. The digital comparator CMP compares the pattern data “H” with the output of the DUT under test, and outputs a comparison result (fail) because the output of the DUT under test is at a low level. The D flip-flop 18
The output of the digital comparator CMP is latched by an edge signal (strobe signal).

The pin electronics PE 512 performs the following operation. The digital comparator CMP compares the pattern data “H” with the output of the DUT under test,
Since the output of the DUT under test is at a high level, the comparison result (pass) is output. The D flip-flop 18
The output of the digital comparator CMP is latched by an edge signal (strobe signal).

As described above, the master clock generator OSC
Is generated by the time counter TC. When the count value matches the cycle time data, the control circuit outputs a time signal pulse, and the timing generator TG1 delays the time signal pulse by the fractional time data and outputs an edge signal. This edge signal is applied to the plurality of pin electronics PE1 to PE512 to perform a test on the device under test. As a result, there is no need to provide a rate generator, so there is no need to delimit the test in units of rate. That is, the link with the simulator can be easily performed.

Further, at least one event sequencer IS and a timing generator TG apply edge signals to a plurality of pin electronics PE1 to PE512,
Since the test of the device under test is performed, the event sequencer does not need to store the time data for each pin, so that the memory may be small.

Next, another embodiment will be described. FIG. 4 is a configuration diagram showing another embodiment of the present invention. In the figure, a master clock generator OSC outputs a clock having a constant period. The time counter TC counts the clock output from the master clock generator OSC. Each of the event sequencers IS1 and IS2 stores time data and pattern data of two or more pins for a device under test (not shown), compares the count value of the time counter with time data (cycle time data), If they match, a time signal pulse is output, and fractional time data of time data and pattern data are output.

Each of the event sequencers IS1 and IS2 has an event memory M and a control circuit C. The event memory M stores pattern data and time data. The control circuit C compares the count value of the time counter TC with the time data (cycle time data) of the event memory M,
When they match, a time signal pulse is output, and the pattern data and time data of the event memory M are controlled.

The timing generators TG1 and TG2 receive the time signal pulse and the fraction time data output from the event sequencers IS1 and IS2, respectively, delay the time signal pulse by the fraction time data, and output an edge signal. The selector section S selects an edge signal from the timing generators TG1 and TG2 and pattern data from the event sequencers IS1 and IS2.

The selector section S includes a pattern selector PS1.
To PS512 and edge selectors ES1 to ES512. The pattern selectors PS1 to PS512 select the pattern data of the event sequencers IS1 and IS2, and respectively select the pin electronics PE1 to PE512.
Output to The edge selectors ES1 to ES512 select edge signals of the timing generators TG1 and TG2,
Output to the pin electronics PE1 to PE512 respectively. The pin electronics PE1 to PE512 are
An edge signal and pattern data are provided from the selector section S, provided for each pin to be tested, and a test of the test target is performed based on the edge signal and the pattern data.

An embodiment of the present invention will be described with reference to FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, event sequencers IS1, IS2
Comprises a time counter TC, an event memory M, an address counter 11 and a coincidence detector 12.

The address counter 11 increments each time signal pulse and designates an address in the event memory M. The coincidence detector 12 calculates the count value of the time counter TC and the time data (cycle time data) of the event memory M.
If coincides, a time signal pulse is output. That is, the address counter 11 and the coincidence detector 12 are the control circuit C of the embodiment shown in FIG.

Each of the timing generators TG1 and TG2 comprises a retiming register 13 and a variable delay generator 14. Retiming registers 13 of the timing generators TG1 and TG2 receive the time signal pulses from the event sequencers IS1 and IS2, respectively, and perform retiming with the clock from the master clock generator OSC.
The variable delay generator 14 includes the retiming register 13
Is delayed by the fractional time data and an edge signal is output to the selector section S.

Pin Electronics PE1 to PE512
Are divided into a driver side and a comparator side, but an actual test system generally includes both.

The pin electronics PE1 and PE2 are
It comprises AND gates 15, 16, a set / reset latch 17, and a driver DRV. The AND gate 15 outputs a logical product of the pattern data and the edge signal from the selector section S (pattern selectors PS1, PS2, edge selectors ES1, ES2). The AND gate 16 outputs the logical product of the negative logic of the pattern data from the selector section S (pattern selectors PS1, PS2 and edge selectors ES1, ES2) and the edge signal. The set / reset latch 17 inputs the output of the AND gate 15 to a set terminal, and inputs the output of the AND gate 16 to a reset terminal. The driver DRV receives the output of the set / reset latch 17 and adjusts and outputs the voltage to the DUT under test. AND gates 15, 16 and set / reset latch 1
7 constitute a formatter.

Pin Electronics PE3 to PE512
Comprises a digital comparator CMP and a D flip-flop 18. The digital comparator CMP compares the output of the DUT under test with the pattern data from the selector section S (pattern selectors PS3 to PS512) and outputs the result. The D flip-flop 18 latches the comparison result of the digital comparator CMP with an edge signal (strobe signal) of the selector unit S (edge selectors ES3 to ES512). Digital comparator CMP and D
The flip-flop 18 forms a comparison unit.

The operation of such a device will be described below.
FIG. 6 is a timing chart showing the operation of the device of FIG. The selector section S (pattern selector PS1, edge selector ES1) supplies the pin electronics PE1 with the pattern data output from the event sequencer IS2 and the edge signal output from the timing generator TG2. Then, the selector section S (pattern selector PS)
2-PS512, edge selector ES2-ES512)
Means other pin electronics PE2, PE3
, PE512 are supplied with the pattern data output from the event sequencer IS1 and the edge signal output from the timing generator TG1.

At time t0, the test system starts operating. First, the operation of the event sequencer IS1 will be described. The count value of the time counter TC is “0”, and the address counter 11 indicates the first address. As a result, the event memory M stores the pattern data “
1 ”,“ L ”,...,“ L ”and time data“ 1.25 ”, where“ 1 ”is periodic time data and“ 0.25 ”is fractional time data. It is.

Next, the operation of the event sequencer IS2 will be described. The count value of the time counter TC is “0”, and the address counter 11 indicates the first address. As a result, the event memory M stores the pattern data “1”.
And the time data “0.5”.
In the time data, “0” is periodic time data and “0.5”
Is fraction time data.

The coincidence detector 12 outputs the cycle time data “0”.
And the count value “0” coincide with each other, so that a time signal pulse is output. This time signal pulse causes the address counter 11
Increments the address.

The timing generator TG2 performs the following operation. The retiming register 13 stores the match detector 1
2 is retimed by the clock from the master clock generator OSC. The variable delay generator 14 outputs the edge signal by delaying the output of the retiming register 13 by the fractional time data “0.5”.

The selector section S, that is, the edge selector ES1 passes the edge signal from the timing generator TG2 to the pin electronics PE1. Similarly, the pattern selector PS1 passes the pattern data from the event sequencer IS2 to the pin electronics PE1.

Hereinafter, the operation of the pin electronics PE1 will be described. The AND gate 15 inputs an edge signal to the set terminal of the set / reset latch 17 based on the pattern data “1” and the edge signal, and causes the signal to rise.
The AND gate 16 does not output the edge signal because the negative logic of the pattern data “1” and the edge signal are input. The driver DRV adjusts the voltage of the signal from the set / reset latch 17 and outputs it to the DUT under test.

At time t1, the event sequencer IS
1 and IS2, the time counter TC counts the count value by the clock output from the master clock generator OSC.
1 ”.

Then, the event sequencer IS1 performs the following operation. The coincidence detector 12 outputs the cycle time data “
Since the count value "1" matches the count value "1", a time signal pulse is output, and the address counter 11 increments the address by the time signal pulse.

Then, the timing generator TG1 performs the following operation. The retiming register 13 retiming of the time signal from the coincidence detector 12 is performed by the clock from the master clock generator OSC. The variable delay generator 14 outputs the edge signal by delaying the output of the retiming register 13 by the fractional time data “0.25”.

The selector section S, that is, the edge selector ES2 passes the edge signal from the timing generator TG1 to the pin electronics PE2. Similarly, the pattern selector PS2 passes the pattern data from the event sequencer IS1 to the pin electronics PE2.

Hereinafter, the operation of the pin electronics PE2 will be described. The AND gate 15 inputs an edge signal to the set terminal of the set / reset latch 17 based on the pattern data “1” and the edge signal, and causes the signal to rise.
The AND gate 16 does not output the edge signal because the negative logic of the pattern data “1” and the edge signal are input. The driver DRV adjusts the voltage of the signal from the set / reset latch 17 and outputs it to the DUT under test.

The selector section S, that is, the edge selectors ES3 and ES512 respectively convert the edge signals from the timing generator TG1 into the pin electronics PE3 and PE3.
Pass to PE512. Similarly, the pattern selector PS3
The PS 512 transfers the pattern data from the event sequencer IS1 to the pin electronics PE3, PE5, respectively.
Hand over to 12.

Pin Electronics PE3, PE512
Performs the same operation because the pattern data (comparator expected value) is the same at "L". Digital comparator C
The MP compares the pattern data “L” with the output of the DUT under test, and outputs the comparison result (pass) because the output of the DUT under test is at a low level. The D flip-flop 18 latches the output of the digital comparator CMP with an edge signal (strobe signal).

Next, the operation of the event sequencer IS2 will be described. The event memory M outputs the pattern data “0” and the time data “
As for the time data, "1" is cycle time data and "0.5" is fractional time data.

The coincidence detector 12 outputs the cycle time data “1”.
Since the count value matches the count value “1”, a time signal pulse is output. This time signal pulse causes the address counter 11
Increments the address.

Then, the timing generator TG1 performs the following operation. The retiming register 13 retiming of the time signal from the coincidence detector 12 is performed by the clock from the master clock generator OSC. The variable delay generator 14 outputs the edge signal by delaying the output of the retiming register 13 by the fractional time data “0.5”.

The selector section S, that is, the edge selector ES1 passes the edge signal from the timing generator TG2 to the pin electronics PE1. Similarly, the pattern selector PS1 passes the pattern data from the event sequencer IS2 to the pin electronics PE1.

Hereinafter, the operation of the pin electronics PE1 will be described. The AND gate 15 does not output an edge signal due to the pattern data “0” and the edge signal. The AND gate 16 receives the negative logic of the pattern data “0” and the edge signal, and inputs the edge signal to the reset terminal of the set / reset latch 17 to cause the signal to fall. The driver DRV adjusts the voltage of the signal from the set / reset latch 17 so that the DU under test
Output to T.

Similarly, from time t2 to time t6, the event sequencer IS1, the timing generator TG1, the selector S, the pin electronics PE2, PE3, PE5
12 repeats the same operation as the device of FIG.

Then, the event sequencer IS2, the timing generator TG2, the selector section S, and the pin electronics PE1 repeat the operation at times t0 and t1.

As described above, the event sequencers IS1,
IS2 and two or more timing generators TG1 and TG2 are provided, and an edge signal and pattern data are selected by the selector unit S and passed to the pin electronics PE1 to PE512. And pin electronics PE1
Signals at different timings can be freely supplied to the PE 512.

The present invention is not limited to this, but may be as follows. A configuration in which a plurality of event sequencers are provided and a time counter is provided for each event sequencer, or a configuration in which one time counter supports a plurality of event sequencers may be employed.

[0092]

According to the present invention, the following effects can be obtained. According to the first to fifth aspects, the time counter counts the clock generated by the master clock generator. Then, the event sequencer compares the count value with the time data, outputs a time signal pulse, and the timing generator delays the time signal pulse by the fractional time data, and outputs an edge signal. This edge signal is applied to a plurality of pin electronics to test the device under test. As a result, there is no need to provide a rate generator, so there is no need to delimit the test in units of rate. That is, the link with the simulator can be easily performed.

Further, at least one event sequencer and a timing generator apply an edge signal to a plurality of pin electronics to perform a test of a device under test, so that the event sequencer does not need to store time data for each pin. Good, so less memory is required.

According to the present invention, two or more event sequencers and two or more timing generators are provided.
Since the edge signal and the pattern data are selected and passed to the pin electronics, even if there are pins with completely different timings, it is possible to cope with the pins and freely provide signals with different timings to the pin electronics.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart showing an operation of the device of FIG. 2;

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

FIG. 5 is a configuration diagram showing another embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the device of FIG.

FIG. 7 is a diagram showing a configuration of a conventional test system.

FIG. 8 is a diagram showing a specific configuration of the event sequencers IS1 to IS512.

FIG. 9 is a timing chart showing the operation of the device of FIG. 7;

[Explanation of symbols]

 C control circuit CMP comparator DRV driver DUT device under test IS event sequencer M event memory OSC master clock PE1 to PE512 pin electronics S selector unit TC time counter TG, TG1, TG2 timing generator 13 retiming register 14 variable delay generator 15, variable delay generator 15, 16 AND gate 17 Set reset latch 18 D flip-flop

Claims (5)

[Claims] 1. A test system for testing a device under test, comprising: a master clock generator for outputting a clock of a fixed period; at least one time counter for counting clocks output by the master clock generator; It stores pattern data of two or more pins with respect to the test object, compares the count value of the time counter with time data, outputs a time signal pulse, and outputs fractional time data and pattern data of the time data. At least one event sequencer, which is provided for each event sequencer, receives a time signal pulse and fractional time data output by the event sequencer, delays the time signal pulse by the fractional time data, and generates an edge signal. And the edge signal from this timing generator Test system characterized by having said inputs the pattern data from the event sequencer, based on the edge signal and the pattern data, two or more pin electronics testing the device under test subject. 2. A test system for testing a device under test, comprising: a master clock generator for outputting a clock having a constant period; at least one time counter for counting clocks output by the master clock generator; It stores pattern data of two or more pins for the test object, compares the count value of the time counter with time data, outputs a time signal pulse, and outputs fractional time data of time data and pattern data. At least two or more event sequencers, and a timing signal which is provided for each event sequencer, receives a time signal pulse and fraction time data output from the event sequencer, delays the time signal pulse by the fraction time data, and outputs an edge signal. Generator and the edge signal from this timing generator. And a selector unit for inputting pattern data from the event sequencer and selecting an edge signal and pattern data. Performing a test of the device under test based on the edge signal and the pattern data from the selector unit. A test system comprising the above pin electronics. 3. An event sequencer comprising: an event memory for storing time data and pattern data for two or more pins of a device under test; a count value of a time counter and time data of the event memory; 3. The test system according to claim 1, further comprising a control circuit for outputting and controlling the pattern data and the time data of the event memory. 4. A timing generator, which receives a time signal pulse output from the event sequencer and retiming by a clock from the master clock generator, delays the pulse from the retiming register by fractional time data. 4. The test system according to claim 1, further comprising a variable delay generator for outputting an edge signal. 5. A pin electronics, comprising: a formatter for shaping a waveform based on pattern data and an edge signal; a driver for inputting a signal from the formatter and outputting the signal to a device under test; and a signal and pattern from the device under test. 5. The test system according to claim 1, further comprising: a comparison unit that compares the data with the data and holds a comparison result by an edge signal.