JPH1132258A - Solid-state image-pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image-pickup element provided with a charge- voltage converting section which can make resetting operations with respect to different driving power supply voltage VDD. SOLUTION: In a charge-voltage converting section of a solid-state image- pickup element, three terminals, a VDD terminal 21, a VDR terminal 22, and a GND terminal 23 are provided, and a resistor dividing circuit 24 composed of resistors R1 and R2 is connected between the VDD and VRD terminals 21 and 22, with the voltage-dividing point of the circuit 24 being connected to a reset drain RD. The image pickup element is constituted so that the element may cope with two kinds of power supply specifications in such a way that, when the image-pickup element is used corresponding to a low VDD, the VDR terminal 22 is short-circuited to the VDD terminal 21 and, when the element is used correspondingly to a high VDD, the VDR terminal 22 is short-circuited to the GND terminal 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a charge-to-voltage converter for converting signal charges obtained by photoelectric conversion in each pixel into a voltage.

[0002]

2. Description of the Related Art A solid-state image sensor called an area sensor or a linear sensor includes a floating diffusion (FD) for converting signal charges obtained by photoelectric conversion in each pixel into a voltage, and a floating diffusion (FD) after the voltage conversion. And a reset gate (RG) for controlling the discharge of the signal charge from the floating diffusion to the reset drain.

In the charge-to-voltage converter having the above-described structure, the reset gate needs to operate in such a manner that the required amount of charge in the floating diffusion is allowed and the signal charge is completely swept out to the reset drain. In a normal operation state, the reset drain voltage VRD for biasing the reset drain and the potential ΦRG under the reset gate have a certain relationship.

If one of the conditions (voltage or potential) changes, it is necessary to adjust the other to an optimum value in order to guarantee the operation. For example, considering the case where the reset drain voltage VRD is the same as the drive power supply voltage VDD of the device, if the VDD specification changes, the potential ΦRG is adjusted in accordance with each VDD specification, that is, the reset gate voltage (clock clamp) applied to the reset gate Level) VRG needs to be changed.

[0005]

However, in the conventional solid-state imaging device, when the power supply voltage VDD is changed after the reset gate voltage VRG is adjusted in accordance with a certain VDD specification, the potential ΦRG under the reset gate becomes the VDD.
Since the operation cannot be guaranteed without following the variation in the same manner as the D variation amount, when the reset gate voltage VRG is preadjusted in the manufacturing process, the VDD specification is different and the product is treated as a separate product from the manufacturing process. However, there was a problem that was reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a solid-state imaging device having a charge-voltage converter capable of performing a reset operation with respect to a different drive power supply voltage VDD. It is in.

[0007]

According to a first aspect of the present invention, there is provided a solid-state imaging device, wherein a charge-to-voltage converter for converting signal charges obtained by photoelectric conversion in each pixel into a voltage is connected to a reset drain of the charge-voltage converter. The configuration includes an offset circuit for offsetting the applied reset drain voltage in accordance with a change in the drive power supply voltage of the device.

In the solid-state imaging device having the above configuration, when the drive power supply voltage of the device changes, the reset drain voltage is offset by the action of the offset circuit.
The offset to the reset drain voltage compensates for the fact that the reset gate voltage does not follow the change in the drive power supply voltage. Therefore, even when the drive power supply voltage changes, the reset gate operates correctly. That is, a reset operation for different drive power supply voltages VDD can be performed.

According to a fourth aspect of the present invention, in a charge-voltage converter for converting signal charges obtained by photoelectric conversion in each pixel into a voltage, a reset gate clock applied to a reset gate of the charge-voltage converter is provided. The configuration includes an amplitude amplification circuit that amplifies the amplitude.

In the solid-state imaging device having the above configuration, when the drive power supply voltage of the device changes, the amplitude of the reset gate clock is amplified by the operation of the amplitude amplifier circuit.
The amplification of the amplitude of the reset gate clock compensates for the fact that the reset gate voltage does not follow the change in the drive power supply voltage. Therefore, even when the drive power supply voltage changes, the reset gate operates correctly. That is, a reset operation for different drive power supply voltages VDD can be performed.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows, for example, an interline transfer type CCD (Charge) to which the present invention is applied.
FIG. 2 is a schematic configuration diagram illustrating an example of an area sensor.

In FIG. 1, a plurality of sensor units (pixels) 11 arranged in a matrix and converting incident light into signal charges having a charge amount corresponding to the light amount and storing the signal charges,
The imaging area 14 is constituted by a plurality of vertical CCDs 13 provided for each of the vertical columns and vertically transferring the signal charges read from each sensor unit 11 via the read gate unit 12.

In this imaging area 14, the sensor unit 1
Reference numeral 1 denotes a PN junction photodiode, for example. The signal charges stored in the sensor unit 11 are read out to the vertical CCD 13 by the readout gate unit 12. The vertical CCD 13 outputs, for example, a four-phase vertical transfer pulse φ.
V1 to φV4, the signal charges read from each sensor unit 11 are sequentially transferred in the vertical direction by a portion corresponding to one scanning line (one line) in a part of the horizontal blanking period.

A horizontal CCD 15 is arranged below the imaging area 14 in the drawing. To this horizontal transfer CCD 15, signal charges corresponding to one line are sequentially transferred from each of the plurality of vertical CCDs 13. The horizontal CCD 15 is transferred and driven by, for example, two-phase horizontal transfer pulses φH1 and φH2, and sequentially transfers the signal charges for one line transferred from the plurality of vertical CCDs 13 in the horizontal direction in the horizontal scanning period after the horizontal blanking period. Forward. Horizontal CCD 15
A charge-to-voltage conversion unit 16 that converts signal charges sequentially and horizontally transferred by the horizontal CCD 15 into a voltage is provided at an end on the transfer destination side.

The charge-voltage converter 16 is provided with a horizontal CCD 1
5, a floating diffusion FD for converting signal charges sequentially injected through the horizontal output gate 17 into a voltage, a reset drain RD for discharging the signal charges in the floating diffusion FD after the voltage conversion,
It has a floating diffusion amplifier configuration including a reset gate RG for controlling discharge of signal charges from the floating diffusion FD to the reset drain RD.

In the charge-voltage converter 16 having the above configuration,
The reset gate RG needs an operation of allowing the required amount of charge in the floating diffusion FD and completely sweeping out the signal charge to the reset drain RD. A reset gate voltage VRG is applied to the reset gate RG in a signal charge detection cycle, and a reset operation is performed. The reset drain RD is biased to a certain potential by the reset drain voltage VRD.

Here, considering the case where the reset drain voltage VRD is the same as the drive power supply voltage VDD of the device, for example, for a certain VDD value, the reset drain voltage VR
If the VDD value changes after D is pre-adjusted during the manufacturing process, the reset gate voltage VRG and the potential ΦRG below the reset gate RG do not follow the fluctuation of the drive power supply voltage VDD and do not serve as the reset gate RG.

Although the reset gate voltage VRG is generated inside the device or given from the outside, in order for the reset gate RG to operate properly even if the drive power supply voltage VDD changes, the reset gate voltage VRG must be controlled with respect to the fluctuation of the drive power supply voltage VDD. The potential ΦRG below the reset gate RG needs to have a gain = 1. Normally, since the transistor has a gate and channel gain of less than 1, the reset gate voltage VRG requires a gain ≧ 1 (see FIG. 2).

The present invention has been made to solve this situation. FIG. 3 is a circuit diagram showing the first embodiment of the present invention.

In FIG. 3, the charge-voltage converter 16 according to the present embodiment is provided with three terminals, a VDD (power supply) terminal 21, a VRD (reset drain) terminal 22, and a GND (ground) terminal 23. . And VDD
A resistor dividing circuit 24 including a resistor R1 and a resistor R2 is connected as an offset circuit between the terminal 21 and the VRD terminal 22, and a voltage dividing point (a common connection point of the resistors R1 and R2) P
Are connected to the reset drain RD.

The reset gate voltage VRG generated by the VRG generation circuit 25 is applied to the reset gate RG. The VRG generation circuit 25 outputs the reset gate clock φ
VRG as an input and its reset gate clock φVR
For example, a low level of G is clamped to a predetermined DC level and applied to the reset gate RG as a reset gate voltage (clock pulse) VRG.

In the charge-to-voltage converter 16 according to the first embodiment having the above configuration, normally, as shown in FIG.
The VRD terminal 22 is short-circuited to the VDD terminal 21. In this case, the reset drain voltage VRD becomes equal to the drive power supply voltage VDD. Also, if necessary, FIG.
As shown in (B), the VRD terminal 22 is connected to the GND terminal 23.
And short circuit. In this case, the divided voltage at the voltage dividing point P obtained by dividing the drive power supply voltage VDD according to the resistance ratio between the resistors R1 and R2 is the reset drain voltage V
RD.

That is, when adjusting the reset gate voltage VRG with a low VDD value, VDD = VRD. On the other hand, when using at a high VDD value, VRG = GND. At this time, VRD <VDD, and the fact that the reset gate voltage VRG does not follow the fluctuation of the drive power supply voltage VDD can be compensated for by offsetting the reset drain voltage VRD by the resistance dividing circuit 24. Even if it changes, the reset gate RG operates correctly.

Therefore, by selecting the short-circuit destination of the VRG terminal 22, it is possible to cope with two types of power supplies having different power supply voltages VDD. Switching of the short-circuit destination of the VRG terminal 22 is possible by, for example, a wire bonding method at an assembly stage.
If double bonding is performed, there is no need to change the terminal arrangement of the final product. As a result, it is possible to manufacture a product corresponding to two types of power supply specifications while using a common wafer process, so that the cost merit is high.

In this embodiment, the short-circuit destination of the VRG terminal 22 is fixedly determined by wire bonding. However, as shown in FIG. 5, the movable contact a is connected to the VRD terminal 22 and the fixed contact b is connected to the VRD terminal 22. By providing a changeover switch 26 having the VDD terminal 21 and the other fixed contact c connected to the GND terminal 23 outside the device, the user can selectively switch the VRD terminal 22 according to the power supply used. It becomes possible.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In the present embodiment, a V that generates a reset drain voltage VRD that varies according to a change in the drive power supply voltage VDD is provided between the VDD terminal 21 and the reset drain RD.
The configuration is such that the RD generation circuit 27 is connected as an offset circuit.

As shown in FIG. 7, for example, a VRD generating circuit 27 includes a so-called diode-connected n-channel transistor Q having a gate terminal and a drain electrode commonly connected to a VDD terminal 21;
A source output voltage of the n-channel transistor Q as a reset drain voltage VRD.
D.

Since the VRD generating circuit 27 having the above-described configuration has a circuit configuration using n-channel transistors, the same gain as the gain of the potential ΦRG below the reset gate RG with respect to the drive power supply voltage VDD can be obtained. Thus, if the relationship between the reset gate voltage VRG and the reset drain voltage VRD is adjusted to an optimum value under a certain VDD condition, the threshold voltage of the n-channel transistor Q becomes V
Assuming that th, even if the VDD condition changes, VRD =
(VDD−Vth), and the reset gate voltage VRG
Can be compensated for by the offset of the reset drain voltage VRD, so that the operation of the reset gate RG does not occur. Therefore, the drive power supply voltage VDD can be designated as the operable range, so that the drive power supply voltage VDD
A CCD area sensor with variable D can be realized.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention. In the present embodiment, the reset gate voltage VRG
Of the VRG generation circuit 25 under the condition that 0 <gain <1 follows the drive power supply voltage VDD.
Is provided with an amplitude amplifying circuit 28 for amplifying the amplitude of the reset gate clock φVRG in the preceding stage. Note that the present embodiment does not employ a configuration for offsetting the reset drain voltage VRD as in the first and second embodiments, and therefore a protection resistor R4 is provided between the VDD terminal 21 and the reset drain RD. It is connected.

As described above, the reset gate voltage VRG can be made to follow the drive power supply voltage VDD with 0 <gain <1, and the portion that cannot be followed can be compensated by amplifying the amplitude of the reset gate clock φVRG. Even when the drive power supply voltage VDD changes, the reset gate RG can operate correctly.

Here, the amplitude amplifying circuit 28 can be constituted by an inverter circuit or the like. Further, inversion of the amplitude of the reset gate clock φVRG, phase adjustment, and the like may be optimized at the input stage.

In each of the above embodiments, the case where the present invention is applied to the charge-voltage converter of the area sensor has been described. However, the present invention is not limited to this. Applicable.

[0033]

As described above, according to the first aspect of the present invention, in the charge-to-voltage converter for converting the signal charge obtained by photoelectric conversion in each pixel into a voltage, the driving power supply voltage of the device is reduced. By offsetting the reset drain voltage when it changes, it is possible to compensate for the fact that the reset gate voltage does not follow the change in the drive power supply voltage, so that it is possible to produce a product that can support two types of power supply specifications.

According to the fourth aspect of the present invention, in the charge-voltage converter for converting signal charges obtained by photoelectric conversion in each pixel into a voltage, when the drive power supply voltage of the device changes, the amplitude of the reset gate clock is changed. Is amplified, it is possible to compensate for the fact that the reset gate voltage does not follow the change in the drive power supply voltage, so that a product that can support two types of power supply specifications can be manufactured.

[Brief description of the drawings]

FIG. 1 shows an interline transfer system C to which the present invention is applied
It is a schematic structure figure showing an example of a CD area sensor.

FIG. 2 is a diagram illustrating a potential image of a reset gate unit.

FIG. 3 is a circuit diagram showing a first embodiment of the present invention.

FIG. 4 is a diagram showing a form of terminal connection in the first embodiment.

FIG. 5 is a diagram showing a modified example of terminal connection.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an example of a VRD generation circuit.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention.

[Explanation of Signs] 11: Sensor unit, 13: Vertical CCD, 15: Horizontal CC
D, 16: charge-voltage converter, 21: VDD (power supply) terminal, 22: VRD (reset drain) terminal, 23: G
ND (ground) terminal, 24: resistance dividing circuit, 25: V
RG generation circuit, 27: VRD generation circuit, 28: amplitude amplification circuit

Claims (4)

[Claims] 1. A solid-state imaging device comprising: a charge-voltage converter for converting a signal charge obtained by photoelectric conversion in each pixel into a voltage, wherein a reset drain voltage applied to a reset drain of the charge-voltage converter is A solid-state imaging device comprising an offset circuit for offsetting according to a change in a drive power supply voltage of a device. 2. The offset circuit, wherein a first resistor connected between a power supply terminal to which the drive power supply voltage is applied and the reset drain, and a reset resistor connected between the reset drain and a reset drain terminal. A resistance dividing circuit including a second resistor, wherein the power supply terminal and the reset drain terminal are connected during a first use, and the reset drain terminal and a ground terminal are connected during a second use. The solid-state imaging device according to claim 1, wherein 3. The solid-state imaging device according to claim 1, wherein the offset circuit is a transistor circuit having an n-channel transistor that shifts the drive power supply voltage by a threshold voltage and sets the reset drain voltage. . 4. A solid-state imaging device comprising a charge-voltage converter for converting signal charges obtained by photoelectric conversion in each pixel into a voltage, wherein a reset gate clock applied to a reset gate of the charge-voltage converter is provided. A solid-state imaging device comprising an amplitude amplifier circuit for amplifying an amplitude.