JPH1131882A - Multilayered interconnection board and method for manufacturing it - Google Patents

Multilayered interconnection board and method for manufacturing it

Info

Publication number
JPH1131882A
JPH1131882A JP18508797A JP18508797A JPH1131882A JP H1131882 A JPH1131882 A JP H1131882A JP 18508797 A JP18508797 A JP 18508797A JP 18508797 A JP18508797 A JP 18508797A JP H1131882 A JPH1131882 A JP H1131882A
Authority
JP
Japan
Prior art keywords
wiring board
hole
layer
insulator
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18508797A
Other languages
Japanese (ja)
Inventor
Tomiji Kojima
富次 小島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18508797A priority Critical patent/JPH1131882A/en
Publication of JPH1131882A publication Critical patent/JPH1131882A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0094Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered interconnection board and its manufacturing method, wherein high-density wiring and high-density mounting are possible while maintaining reliable electrical connection. SOLUTION: In a multilayered interconnection board, interconnection patterns 9a, 9b, 9c, and 9d layers are electrically connected with a conductive bump 6 which penetrates an interlayered insulator 7a in the thickness direction, and a plated conductor layer 8 provided on an inside wall surface of a hole penetrating the inter-layer insulator in the thickness direction. Here, the inside of a through-hole where the plated conductor layer 8 is provided is filled with an insulator 10, and the electrical joint of the conductive bump 6 to the plated conductor layer 8 is established via a conductor layer 11 which is allocated on a filled surface of the insulator 10.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多層配線板および
その製造方法に関する。
The present invention relates to a multilayer wiring board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】回路装置のコンパクト化などを図る手段
として、絶縁体層と配線パターン層とを交互に積層した
構成の多層印刷配線板が広く実用に供されている。そし
て、この種の多層配線板においては、回路の高密度化や
高機能化の要求に対応して、配線パターン層の多層化、
配線パターン層間の接続が行われている。
2. Description of the Related Art As means for reducing the size of circuit devices, multilayer printed wiring boards having a structure in which insulator layers and wiring pattern layers are alternately laminated are widely used. In this type of multilayer wiring board, in order to respond to demands for higher density and higher functionality of circuits, multilayer wiring pattern layers,
The connection between the wiring pattern layers is made.

【0003】図3は、配線パターン層間を接続する接続
部を有する多層配線板の要部構成例を示す断面図であ
る。図3において、1a,1bは外層配線パターン、1c,1d
は内層配線パターン、2は前記配線パターン1a,1c,1
d,1b間を絶縁する層間絶縁体層、3a,3bは前記配線パ
ターン1a,1c,1d,1b間を電気的に接続する接続部であ
る。ここで、層間絶縁体層2は、たとえば樹脂単独、フ
ィラーを含有する樹脂組成物、もしくはクロス類などの
基材に樹脂を付着含有したものなどの絶縁性樹脂層であ
る。
FIG. 3 is a cross-sectional view showing an example of a configuration of a main part of a multilayer wiring board having a connecting portion for connecting between wiring pattern layers. In FIG. 3, 1a and 1b are outer layer wiring patterns, and 1c and 1d.
Is the inner layer wiring pattern, and 2 is the wiring pattern 1a, 1c, 1
Interlayer insulator layers 3a and 3b for insulating between d and 1b are connecting portions for electrically connecting the wiring patterns 1a, 1c, 1d and 1b. Here, the interlayer insulating layer 2 is an insulating resin layer such as a resin alone, a resin composition containing a filler, or a material obtained by attaching and containing a resin to a base material such as cloth.

【0004】そして、このような多層配線板は、一般的
に、次のような工程によって製造されている。
[0004] Such a multilayer wiring board is generally manufactured by the following steps.

【0005】図4 (a)〜 (c)は、工程の実施態様を模式
的に示すもので、先ず、図4 (a)に断面的に示すごと
く、たとえば両面銅箔張り積層板(コア基板)4に孔明
けを行った後、形成した孔3a′内壁面を含め全面に化学
メッキを施し、さらに電気メッキ処理で厚付けし、孔3
a′内壁面の金属層(導電体層)3aを厚くして信頼性を
高める。
FIGS. 4A to 4C schematically show an embodiment of the process. First, as shown in cross section in FIG. 4A, for example, a double-sided copper foil-clad laminate (core substrate) is used. 4) After making a hole in 4, the entire surface including the inner wall surface of the formed hole 3a 'is subjected to chemical plating and further thickened by electroplating.
The reliability is improved by increasing the thickness of the metal layer (conductor layer) 3a on the inner wall surface of a '.

【0006】次いで、前記両面のメッキ層および銅箔
を、たとえばフォトエッチング処理し、所要のパターニ
ング1c,1dを行ってから、図4 (b)に断面的に示すごと
く、前記パターニング1c,1d面に絶縁性樹脂シート(た
とえばプリプレグ樹脂シート)5を介して銅箔6a,6bを
積層・配置し、加圧一体化する。
Next, the plating layers and the copper foil on both sides are subjected to, for example, photo-etching to perform required patterning 1c and 1d, and then, as shown in a sectional view in FIG. Then, copper foils 6a and 6b are laminated and arranged via an insulating resin sheet (for example, a prepreg resin sheet) 5, and integrated under pressure.

【0007】その後、図4 (c)に断面的に示すごとく、
銅箔6a,6bを一体化した状態で、孔明けを行った後、形
成した孔3b′内壁面を含め全面に化学メッキを施し、さ
らに電気メッキ処理で厚付けし、孔3b′内壁面の金属層
(導電体層)3bを厚くして信頼性を高める。
Then, as shown in cross section in FIG.
After drilling with the copper foils 6a and 6b integrated, chemical plating is applied to the entire surface including the inner wall surface of the formed hole 3b ', and further thickened by electroplating, and the inner wall surface of the hole 3b' is Increase the reliability by increasing the thickness of the metal layer (conductor layer) 3b.

【0008】次いで、前記形成したメッキ層および銅箔
6a,6bを、たとえばフォトエッチング処理し、所要のパ
ターニング1a,1bする。こうして、配線パターン1a,1
b,1c,1d間の電気的な接続および銅箔6a,6bのパター
ニングを行って、前記図3に図示したような、配線パタ
ーン1a,1b,1c,1d間を接続する接続部3a,3bを備えた
多層配線板を製造している。
Next, the formed plating layer and copper foil
6a and 6b are subjected to, for example, a photo-etching process to perform required patterning 1a and 1b. Thus, the wiring patterns 1a, 1
The electrical connection between b, 1c, 1d and the patterning of the copper foils 6a, 6b are performed, and the connection portions 3a, 3b for connecting the wiring patterns 1a, 1b, 1c, 1d as shown in FIG. We manufacture multilayer wiring boards with

【0009】一方、前記メッキ処理などを伴う配線パタ
ーン1a,1b,1c,1d間の電気的な接続工程を簡略化する
ため、たとえば導電性ペースト製の突起状導体(導電性
バンブ)の先端部を、層間絶縁体5として介在させた絶
縁性樹脂層を厚さ方向に貫通させ、かつ対向する配線パ
ターン面へ対接もしくは圧接させて電気的な接続を行う
方式も提案されている。
On the other hand, in order to simplify the electrical connection process between the wiring patterns 1a, 1b, 1c, 1d involving the plating process, for example, the tip of a projecting conductor (conductive bump) made of a conductive paste is used. A method has been proposed in which an insulating resin layer interposed as an interlayer insulator 5 is penetrated in the thickness direction, and an electrical connection is made by contacting or pressing against an opposing wiring pattern surface.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、上記構
成の多層配線板の場合は、接続部3a,3bを形成する穿設
孔領域に配線パターンニングできないし、また、電子部
品の面実装を行うことができない。すなわち、ビア接続
部3aおよびスルホール接続部3bにおいては、配線パター
ニングできないため、配線の設計・仕様や配線密度が制
約されるという問題がある。加えて、スルホール接続部
3bにおいては、電子部品の搭載・実装が制約されるの
で、実装密度の向上を図ることができない。
However, in the case of the multilayer wiring board having the above-mentioned structure, wiring patterning cannot be performed in the perforated hole area for forming the connection portions 3a and 3b, and the surface mounting of the electronic component must be performed. Can not. That is, in the via connection portion 3a and the through-hole connection portion 3b, since the wiring cannot be patterned, there is a problem that the design / specification of the wiring and the wiring density are restricted. In addition, through-hole connections
In 3b, mounting and mounting of electronic components are restricted, so that mounting density cannot be improved.

【0011】上記ビア接続部3aおよびスルホール接続部
3bに起因する問題は、多層配線板の高密度配線化ないし
コンパクト化、あるいは高密度実装回路化ないし軽薄・
短小化などの支障となる。つまり、近時、要求の高い回
路装置のコンパクト化などに対応する上で、この問題の
解決ないし解消・改善が望まれているのが現状である。
The via connection portion 3a and the through-hole connection portion
The problems caused by 3b are that high-density wiring or compaction of multilayer wiring boards, or high-density mounting circuits or
It becomes an obstacle such as shortening. In other words, in recent years, it has been desired to solve, solve, or improve this problem in order to respond to the demand for more compact circuit devices.

【0012】一方、突起状導体(導電性バンブ)の先端
部を、介在させた絶縁性樹脂層を貫通させ、対向する配
線パターン面に対接もしくは圧接することによって、配
線パターン1a,1b,1c,1d間の電気的な接続などを行う
構成は、工程も簡略で、配線密度および実装密度の向上
など図ることができる。しかしながら、さらに高い信頼
性を要求される場合は、内層配線パターン同士の接続構
成において、信頼性が懸念されることもある。
On the other hand, the leading ends of the protruding conductors (conductive bumps) penetrate through the interposed insulating resin layer and contact or press contact with the opposing wiring pattern surfaces to form the wiring patterns 1a, 1b, 1c. , 1d has a simple process, and can improve the wiring density and the mounting density. However, when higher reliability is required, there is a case where the reliability may be concerned in the connection configuration between the inner layer wiring patterns.

【0013】本発明は、上記事情に対処してなされたも
ので、高密度配線や高密度実装が可能で、かつ電気的な
接続の信頼性も高い多層配線板とその製造方法の提供を
目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a multilayer wiring board capable of high-density wiring and high-density mounting and having high reliability of electrical connection, and a method of manufacturing the same. And

【0014】[0014]

【課題を解決するための手段】請求項1の発明は、層間
絶縁体を厚さ方向に貫挿する導電性バンプ、および層間
絶縁体を厚さ方向に貫通する孔の内壁面に設けたメッキ
導電体層により、配線パターン層間が電気的に接続され
た構成を有する多層配線板であって、前記メッキ導電体
層を設けた貫通孔内が絶縁体で充填され、かつこのメッ
キ導電体層に対する導電性バンプによる電気的な接合は
絶縁体の充填面に配置した導電体層を介して行われてい
ることを特徴とする多層配線板である。
According to a first aspect of the present invention, there is provided a conductive bump for penetrating an interlayer insulator in a thickness direction, and plating provided on an inner wall surface of a hole penetrating the interlayer insulator in a thickness direction. A multilayer wiring board having a configuration in which wiring layers are electrically connected by a conductive layer, wherein the inside of the through hole provided with the plated conductive layer is filled with an insulator, and The multilayer wiring board is characterized in that the electrical connection by the conductive bumps is performed via a conductive layer disposed on the filling surface of the insulator.

【0015】請求項2の発明は、コア配線板の所定位置
に厚さ方向に貫通する孔を設け、その内壁面をメッキ導
電体層化してスルホール接続部を形成する工程と、前記
スルホール接続部を設けた貫通孔内を絶縁体で充填する
工程と、前記充填した少なくとも一方の絶縁体面に、前
記スルホール接続部に導通する導電体層を配置してコア
配線板を形成する工程と、前記コア配線板面に絶縁性シ
ートを介して層間接続用の導電性バンプを一主面に設け
た導電体箔を位置決め配置して積層体化する工程と、前
記積層体を加圧一体化して絶縁性シートを貫挿する導電
性バンプ先端部を、前記スルホール接続部に導通する導
電体層に対接・電気的に接続した導電体箔張り積層板を
形成する工程と、前記導電体箔を配線パターニングする
工程とを有することを特徴とする多層配線板の製造方法
である。
A second aspect of the present invention provides a step of forming a through hole in a thickness direction at a predetermined position of a core wiring board, forming an inner wall surface of the through hole as a plated conductor layer to form a through hole connection portion, Filling the inside of the through-hole with an insulator, forming a core wiring board by arranging a conductor layer that is conductive to the through-hole connection portion on at least one of the filled insulator surfaces, A step of positioning and arranging a conductive foil having conductive bumps for interlayer connection provided on one main surface thereof via an insulating sheet on a wiring board surface to form a laminate; A step of forming a conductive foil-clad laminate in which the tip of the conductive bump penetrating the sheet is in contact with and electrically connected to the conductive layer conducting to the through-hole connecting portion; and wiring patterning of the conductive foil And the step of A method for manufacturing a multilayer wiring board according to claim.

【0016】本発明において、コア配線板は、対象と成
る多層配線板によって、たとえば片面配線板、両面型配
線板、これらの組み合わせで形成される3層以上の多層
型が挙げられ、また、層間接続部の一部を形成する貫通
孔の穿設は、たとえばドリル加工などによって行われ
る。そして、この貫通孔内壁面の導電体層化は、一般的
な無電解メッキおよび電気メッキの併用で行ない、さら
に、内壁面を導電体層化した貫通孔内を充填する絶縁体
としては、たとえばエポキシ樹脂、フェノール樹脂、あ
るいはこれらの樹脂に無機充填剤を配合した組成物など
が挙げられる。なお、一般的に、貫通孔内の充填は、コ
ア配線板を構成する絶縁体と同じ材質の絶縁体で行うこ
とが望ましい。
In the present invention, the core wiring board may be, for example, a single-sided wiring board, a double-sided wiring board, or a multilayer of three or more layers formed by a combination thereof, depending on the multilayer wiring board to be processed. Drilling of the through-hole forming a part of the connection portion is performed by, for example, drilling. The conductor layering of the inner wall surface of the through hole is performed by using a combination of general electroless plating and electroplating. Further, as an insulator that fills the through hole with the inner wall surface being a conductor layer, for example, An epoxy resin, a phenol resin, or a composition in which an inorganic filler is blended with these resins is exemplified. In general, it is desirable to fill the through holes with an insulator made of the same material as the insulator constituting the core wiring board.

【0017】また、導電体層(箔など)としては、たと
えば厚さ18〜35μm 程度の電解銅箔やアルミ箔などが挙
げられ、その材質および厚さは、製造する多層配線板の
用途や厚さなどによって適宜選択する。そして、この導
電体箔の一主面に対する導電性バンプ(導電性突起)の
形成は、たとえばメタルマスクを用い、導電性樹脂ペー
ストをスクリーン印刷、印刷後の乾燥を適宜繰り返すこ
とによって、所定寸法(底面径,高さ)の円錐状もしく
は角錐状に形成できる。
The conductor layer (eg, foil) includes, for example, an electrolytic copper foil or an aluminum foil having a thickness of about 18 to 35 μm. It is appropriately selected depending on the size and the like. The formation of the conductive bumps (conductive protrusions) on one main surface of the conductive foil is performed by, for example, using a metal mask, screen printing a conductive resin paste and drying after printing as appropriate to obtain a predetermined size ( (Bottom diameter, height).

【0018】ここで、導電性樹脂ペーストとしては、た
とえば銀,金,銅,半田粉などの導電性粉末、これらの
合金粉末もしくは複合(混合)金属粉末と、樹脂バイン
ダー成分とを混合して調製されたペースト類が挙げられ
る。また、樹脂バインダー成分としては、たとえばポリ
カーボネート樹脂、ポリスルホン樹脂、ポリエステル樹
脂、フェノキシ樹脂などの熱可過塑性樹脂、フェノール
樹脂、ポリイミド樹脂、エポキシ樹脂などの熱硬化性樹
脂などが一般的に挙げられる。その他、メチルメタアク
リレート、ジエチルメチルメタアクリレート、トリメチ
ロールプロパントリアクリレート、ジエチレングリコー
ルジエチルアクリレート、アクリル酸メチル、アクリル
酸エチル、アクリル酸ジエチレングリコールエトキシレ
ート、ε−カプロラクトン変性ジペンタエリスリトール
のアクリレートなどのアクリル酸エステル、メタアクリ
ル酸エステルなどの紫外線硬化型樹脂もしくは電子線照
射硬化型樹脂などが挙げられる。
The conductive resin paste is prepared by mixing a conductive powder such as silver, gold, copper and solder powder, an alloy powder or a composite (mixed) metal powder thereof, and a resin binder component. Pastes. Examples of the resin binder component generally include, for example, thermoplastic resins such as polycarbonate resins, polysulfone resins, polyester resins, and phenoxy resins, and thermosetting resins such as phenol resins, polyimide resins, and epoxy resins. In addition, acrylic acid esters such as methyl methacrylate, diethyl methyl methacrylate, trimethylolpropane triacrylate, diethylene glycol diethyl acrylate, methyl acrylate, ethyl acrylate, diethylene glycol ethoxylate acrylate, acrylate of ε-caprolactone-modified dipentaerythritol, An ultraviolet curable resin such as a methacrylic acid ester or an electron beam irradiation curable resin may be used.

【0019】さらに、コア配線板面に配置する絶縁性シ
ートとしては、熱可塑性樹脂フイルム(シート)や熱硬
化性樹脂シートが挙げられ、その厚さは、一般的に、50
〜 100μm 程度が好ましい。ここで、熱可塑性樹脂シー
トとしては、たとえばポリカーボネート樹脂、ポリスル
ホン樹脂、熱可塑性ポリイミド樹脂、4フッ化ポリエチ
レン樹脂、6フッ化ポリプロピレン樹脂、ポリエーテル
エーテルケトン樹脂などのシート類が挙げられる。ま
た、硬化前の状態に保持される熱硬化性樹脂(プリプレ
グ)シートとしては、エポキシ樹脂、ビスマレイミドト
リアジン樹脂、ポリイミド樹脂、フェノール樹脂、ポリ
エステル樹脂、メラミン樹脂、あるいはブタジェンゴ
ム、ブチルゴム、天然ゴム、ネオプレンゴム、シリコー
ンゴムなどの生ゴムのシート類が挙げられる。これら合
成樹脂は、単独でもよいが絶縁性無機物や有機物系の充
填物を含有してもよく、さらにガラスクロスやマット、
有機合成繊維布やマット、あるいは紙などの補強材と組
み合わせて成るシートであってもよい。
Further, examples of the insulating sheet disposed on the surface of the core wiring board include a thermoplastic resin film (sheet) and a thermosetting resin sheet.
About 100 μm is preferable. Here, examples of the thermoplastic resin sheet include sheets such as a polycarbonate resin, a polysulfone resin, a thermoplastic polyimide resin, a tetrafluoroethylene resin, a hexafluoropropylene resin, and a polyetheretherketone resin. The thermosetting resin (prepreg) sheet kept in a state before curing includes epoxy resin, bismaleimide triazine resin, polyimide resin, phenol resin, polyester resin, melamine resin, or butadiene rubber, butyl rubber, natural rubber, neoprene Examples include sheets of raw rubber such as rubber and silicone rubber. These synthetic resins may be used alone or may contain an insulating inorganic or organic filler, and may further contain a glass cloth or mat,
A sheet formed by combining with a reinforcing material such as an organic synthetic fiber cloth, a mat, or paper may be used.

【0020】請求項1の発明では、配線パターン間の電
気的な接続が、導電性バンプおよび貫通孔内壁面に設け
たメッキ導電体層の併用で行われ、かつ貫通孔内が絶縁
体で充填されるとともに、メッキ導電体層に対する導電
性バンプの電気的な接合が充填絶縁体面に配置した導電
体層を介して行われている。つまり、貫通孔型の層間接
続部は絶縁体で充填されているため、多層配線パターン
の設計自由度を確保し易くなるとともに、有効な実装領
域の増大を図ることが可能となる。
According to the first aspect of the invention, the electrical connection between the wiring patterns is performed by using the conductive bumps and the plated conductor layer provided on the inner wall surface of the through hole, and the inside of the through hole is filled with an insulator. At the same time, the electrical bonding of the conductive bumps to the plated conductive layer is performed via the conductive layer disposed on the filling insulator surface. That is, since the through-hole type interlayer connection portion is filled with the insulator, the degree of freedom in designing the multilayer wiring pattern can be easily secured, and the effective mounting area can be increased.

【0021】請求項2の発明では、設計自由度の高い多
層配線パターンを有し、また、実装領域として有効な面
が実質的に拡大化された高密度配線の多層配線板、もし
くは軽薄短小な多層配線板を歩留まりよく提供できる。
According to the second aspect of the present invention, a multi-layer wiring board having a high-density wiring having a multi-layer wiring pattern having a high degree of freedom in design and having an effective area as a mounting area substantially enlarged, A multilayer wiring board can be provided with high yield.

【0022】[0022]

【発明の実施の形態】以下、図1および図2を参照して
実施例を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS.

【0023】図1は、この発明の第1の実施例に係る多
層配線板の要部構成を示す断面図である。図1におい
て、6は層間絶縁体7aを厚さ方向に貫挿する導電性バン
プ、8は層間絶縁体7bを厚さ方向に貫通する孔の内壁面
に設けたメッキ導電体層である。つまり、この多層配線
板は、外層配線パターン9a,9bと内層配線パターン9c,
9dとが導電性バンプ6によって電気的に接続する一方、
一部の内層配線パターン9c,9d同士が貫通孔の内壁面に
設けたメッキ導電体層8で電気的に接続する構成を採っ
たものである。
FIG. 1 is a sectional view showing the structure of a main part of a multilayer wiring board according to a first embodiment of the present invention. In FIG. 1, reference numeral 6 denotes a conductive bump penetrating the interlayer insulator 7a in the thickness direction, and reference numeral 8 denotes a plated conductor layer provided on an inner wall surface of a hole penetrating the interlayer insulator 7b in the thickness direction. In other words, this multilayer wiring board has outer wiring patterns 9a and 9b and inner wiring patterns 9c and 9c.
9d is electrically connected by the conductive bump 6,
A configuration is adopted in which some inner layer wiring patterns 9c and 9d are electrically connected to each other by a plated conductor layer 8 provided on the inner wall surface of the through hole.

【0024】上記多層配線板の構成について、さらに詳
述すると、両面の配線パターン9c,9d間を、厚さ方向に
貫通させた孔の内壁面にメッキ導電体層8でスルホール
接続部を設け、その後、前記貫通孔内を絶縁体10で充填
する一方、配線パターン9c,9dに電気的に接合する導電
体層(たとえばメッキ層)11を設けた両面型配線板をコ
ア配線板12とした構成を採っている。そして、前記両面
型配線板(コア基板)12の両面側に、導電性バンプ6を
層間接続部とした外層配線パターン9a,9bが配置された
構造と成っている。
More specifically, the structure of the multilayer wiring board will be described in more detail. A through-hole connecting portion is provided by a plated conductor layer 8 on the inner wall surface of a hole penetrating in the thickness direction between the wiring patterns 9c and 9d on both surfaces. After that, a double-sided wiring board having a conductor layer (for example, a plating layer) 11 which is electrically connected to the wiring patterns 9c and 9d while filling the inside of the through hole with an insulator 10 is used as a core wiring board 12. Has been adopted. Then, on both sides of the double-sided wiring board (core substrate) 12, outer layer wiring patterns 9a and 9b having conductive bumps 6 as interlayer connection parts are arranged.

【0025】この構成例では、配線パターン9a,9b,9
c,9d間の接続は、配線パターン9a,9c間、配線パター
ン9b,9d間、配線パターン9a,9b,9c,9d間の3か所で
行われているが、多層配線板に空間部もないので、配線
パターン形成領域および実装面領域として、全体的に有
効に利用される形態を採っている。
In this configuration example, the wiring patterns 9a, 9b, 9
The connections between c and 9d are made at three places between the wiring patterns 9a and 9c, between the wiring patterns 9b and 9d, and between the wiring patterns 9a, 9b, 9c and 9d. Since there is no wiring pattern forming area and the mounting surface area, a form that is effectively used as a whole is adopted.

【0026】次に、上記構成の多層配線板の製造方法例
について説明する。
Next, an example of a method for manufacturing a multilayer wiring board having the above-described structure will be described.

【0027】先ず、厚さ約 0.6mmのガラスエボキシ樹脂
系のコア配線板12、厚さ18μm の電解銅箔、直径 0.3mm
の孔を所定の位置に穿設して成る厚さ 0.3mmのメタルス
クリーン版、銀粉末−フェノール樹脂系の導電性ペース
ト、および厚さ約60μm のガラスエボキシ樹脂系プリプ
レグ(未硬化)をそれぞれ用意する。
First, a glass epoxy resin-based core wiring board 12 having a thickness of about 0.6 mm, an electrolytic copper foil having a thickness of 18 μm, and a diameter of 0.3 mm
A 0.3mm thick metal screen plate, a silver powder-phenolic resin-based conductive paste, and a glass epoxy resin-based prepreg (uncured) approximately 60μm thick, each of which is made by drilling holes at predetermined positions I do.

【0028】次いで、前記コア基板12の所定位置(箇
所)に、ドリル加工によって径 0.3mm程度の貫通孔を穿
設し、穿設した貫通孔の内壁面に無電解メッキおよび電
気メッキによって、層間接続部を成す導電体層8を形成
する。その後、前記貫通孔内にエポキシ樹脂系の組成物
10を充填して乾燥・硬化させてから、前記樹脂10充填面
および内層配線パターン9c,9dの被層間接続面に、たと
えば電気メッキによって、選択的に導電体層11を形成・
配置する(コア配線板の形成)。
Next, a through hole having a diameter of about 0.3 mm is formed in a predetermined position (location) of the core substrate 12 by drilling, and the inner wall surface of the formed through hole is formed by electroless plating and electroplating. The conductor layer 8 forming the connection part is formed. Thereafter, an epoxy resin-based composition is provided in the through hole.
After filling with 10 and drying and curing, the conductive layer 11 is selectively formed on the filling surface of the resin 10 and the connecting surfaces of the inner wiring patterns 9c and 9d by, for example, electroplating.
Arrange (formation of core wiring board).

【0029】一方、前記電解銅箔の一主面に、メタルス
クリーン版をそれぞれ位置決め配置し、前記コア基板12
の被層間接続面と対向する位置に、たとえば銀粉末−フ
ェノール樹脂系の導電性ペーストを印刷する。印刷した
導電性ペーストを 165℃,15分間,乾燥処理した後、同
一メタルスクリーン版をそれぞれ用い同一位置に印刷,
乾燥処理を3回繰り返してから加熱効果処理を施して円
錐状(底面径 0.3mm,高さ0.25mm)の導電性バンプ6を
それぞれ設ける。
On the other hand, a metal screen plate is positioned and arranged on one main surface of the electrolytic copper foil, and
For example, a silver powder-phenol resin-based conductive paste is printed at a position facing the interlayer connection surface of the substrate. The printed conductive paste is dried at 165 ° C for 15 minutes, and then printed at the same position using the same metal screen plate.
After the drying process is repeated three times, a heating effect process is performed to provide conical conductive bumps 6 (bottom diameter 0.3 mm, height 0.25 mm).

【0030】次に、前記コア配線板面に層間絶縁シート
を成す絶縁性シート(たとえばガラスエポキシ樹脂系の
プリプレグ)7aを介し、前記層間接続用の導電性バンプ
6を一主面に設けた導電体層(電解銅箔)を位置決め配
置して積層体化する。すなわち、前記積層体を加熱型プ
レスに当て板を介してセットし、 175℃の加熱、 40kg/
cm2 程度の圧力で 1時間加圧プレスを行って、ガラス・
エボキシ樹脂系プリプレグの硬化を行うとともに、ガラ
ス・エボキシ樹脂系プリプレグを貫通させた各導電性バ
ンプ6先端部を、互いに対向するコア配線板12の被接続
部(導電体層)11に対接・接続させて、両面の電解銅箔
と内層配線パターン9c,9dとが電気的に接続する銅箔張
り積層板を作製する。
Then, a conductive bump 6 for interlayer connection is provided on one main surface of the core wiring board via an insulating sheet (for example, a prepreg made of glass epoxy resin) 7a forming an interlayer insulating sheet. The body layer (electrolytic copper foil) is positioned and arranged to form a laminate. That is, the laminate was set on a heating die press via a contact plate, and heated at 175 ° C. and 40 kg /
Press for 1 hour at a pressure of about 2 cm
The epoxy resin-based prepreg is hardened, and the tip of each conductive bump 6 penetrating the glass-epoxy resin-based prepreg is brought into contact with the connected portion (conductor layer) 11 of the core wiring board 12 facing each other. By making connection, an electrolytic copper foil on both surfaces and inner wiring patterns 9c and 9d are electrically connected to produce a copper foil-clad laminate.

【0031】その後、前記銅箔張り積層板外層の銅箔面
にスクリーン印刷法で、所要のエッチングレジストパタ
ーンを印刷し、塩化二鉄の水溶液をエッチング液として
不要部分銅箔をエッチング除去してから、エッチンクレ
ジストを除去することにより、図1に図示する構成の多
層配線板が得られる。
Thereafter, a required etching resist pattern is printed on the copper foil surface of the outer layer of the copper foil-clad laminate by a screen printing method, and unnecessary copper foil is removed by etching using an aqueous solution of diiron chloride as an etchant. By removing the etching resist, a multilayer wiring board having the configuration shown in FIG. 1 is obtained.

【0032】上記によって製造した多層配線板は、その
配線パターン層の接続抵抗は、たとえば 2.1Ωで、この
値は、銅箔のパターン抵抗(バンプ 1個当たりの銅箔パ
ターン抵抗分1mΩ)を考慮すると、スルホール接続抵抗
の平均が1mΩとなって、ビア接続抵抗および銅箔パター
ン抵抗ともバラツキが少ないものであった。
In the multilayer wiring board manufactured as described above, the connection resistance of the wiring pattern layer is, for example, 2.1 Ω, and this value takes into account the copper foil pattern resistance (1 mΩ of copper foil pattern resistance per bump). Then, the average of the through-hole connection resistance was 1 mΩ, and both the via connection resistance and the copper foil pattern resistance had little variation.

【0033】図2は、第2の実施例に係る多層配線板の
要部構成を示す断面図である。この構成例の場合、基本
的な構成においては、前記図1に図示した構成と同様
で、配線パターン9a,9b,9c,9d間の接続は、配線パタ
ーン9a,9c間、配線パターン9b,9d間、配線パターン9
c,9d間の3か所で行われているが、配線パターン9c,9
d間はメッキ導体層8による接続部(ビア接続)を形成
しているに過ぎない。なお、この構成例では、配線パタ
ーン9a,9b,9c,9dの4層に亘る接続部がないので、導
電体層11の配置が省略されている。しかし、配線板に空
間部もないので、配線パターン形成領域および実装面領
域として、全体的に有効に利用される形態を採ってい
る。
FIG. 2 is a sectional view showing the structure of a main part of a multilayer wiring board according to a second embodiment. In the case of this configuration example, the connection between the wiring patterns 9a, 9b, 9c, 9d is basically the same as the configuration shown in FIG. Between, wiring pattern 9
It is performed at three places between c and 9d, but the wiring patterns 9c and 9d
Only the connection portion (via connection) by the plated conductor layer 8 is formed between d. In this configuration example, since there is no connection portion extending over four layers of the wiring patterns 9a, 9b, 9c, and 9d, the arrangement of the conductor layer 11 is omitted. However, since there is no space in the wiring board, a configuration is employed in which the wiring pattern forming region and the mounting surface region are effectively used as a whole.

【0034】なお、本発明は、上記実施例に限定される
ものでなく、発明の趣旨を逸脱しない範囲で、いろいろ
の変形を採ることができる。たとえば層間絶縁体層は、
ガラス・エポキシ樹脂プリプレグの代りに、熱可塑性樹
脂であってもよいし、また、導電性突起は銀粉末−フェ
ノール樹脂以外の他の導電性組成物で形成することがで
きる。さらに、コア基板は、両面型に限られるものでな
く、たとえば導電性バンプなどにより層間接続した多層
型であってもよい。
It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. For example, the interlayer insulator layer
Instead of the glass-epoxy resin prepreg, a thermoplastic resin may be used, and the conductive protrusions may be formed of a conductive composition other than silver powder-phenol resin. Further, the core substrate is not limited to the double-sided type, but may be a multilayer type in which the layers are connected by conductive bumps or the like.

【0035】[0035]

【発明の効果】請求項1の発明によれば、導電性バンプ
および貫通孔内壁面に設けたメッキ導体層の併用で配線
パターン間の電気的な接続が行われる一方、貫通孔内が
絶縁体で充填されているため、高密度配線あるいは高密
度実装が可能な多層配線板が提供される。
According to the first aspect of the present invention, the electrical connection between the wiring patterns is made by using the conductive bumps and the plated conductor layer provided on the inner wall surface of the through hole, while the inside of the through hole is made of an insulator. Thus, a multilayer wiring board capable of high-density wiring or high-density mounting is provided.

【0036】請求項2の発明によれば、配線パターンの
設計自由度が高く、かつ実装領域面が実質的に拡大化
さ、信頼性の高い高密度実装回路の構成などに適する軽
薄短小な多層配線板が歩留まりよく提供される。
According to the second aspect of the present invention, a light, thin, short, and multi-layered structure which has a high degree of freedom in designing a wiring pattern, has a substantially expanded mounting area, and is suitable for a highly reliable high-density mounting circuit, etc. Wiring boards are provided with good yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施例に係る多層配線板の要部構成を示
す断面図。
FIG. 1 is a sectional view showing a configuration of a main part of a multilayer wiring board according to a first embodiment.

【図2】第2の実施例に係る多層配線板の要部構成を示
す断面図。
FIG. 2 is a sectional view showing a configuration of a main part of a multilayer wiring board according to a second embodiment.

【図3】従来の多層配線板の要部構成例を示す断面図。FIG. 3 is a cross-sectional view showing an example of a configuration of a main part of a conventional multilayer wiring board.

【図4】従来の多層配線板の製造方法の実施態様例を模
式的に示すもので、 (a)は両面銅箔張り積層板にスルホ
ール接続部を設けた状態を示す断面図、 (b)は両面に配
線パターニングした状態を示す断面図、 (c)は多層化し
た両面銅箔張り積層板にスルホール接続部を形成する貫
通孔を設けた状態を示す断面図。
FIG. 4 schematically shows an embodiment of a conventional method for manufacturing a multilayer wiring board, in which (a) is a cross-sectional view showing a state in which a through-hole connecting portion is provided in a double-sided copper foil-clad laminate, and (b). FIG. 2 is a cross-sectional view showing a state in which wiring patterning is performed on both sides, and FIG. 2C is a cross-sectional view showing a state in which a through hole for forming a through-hole connection portion is provided in a multilayered double-sided copper foil-clad laminate.

【符号の説明】[Explanation of symbols]

6……導電性バンプ(層間接続部) 7a,7b……層間絶縁体 8……メッキ導電体層(層間接続部) 9a,9b,9c,9d……配線パターン 10……充填絶縁体(メッキ導体層形成貫通孔内の充填) 11……導電体層 12……コア配線板 6 Conductive bumps (interlayer connection parts) 7a, 7b ... Interlayer insulator 8 ... Plating conductor layers (interlayer connection parts) 9a, 9b, 9c, 9d ... Wiring pattern 10 ... Filled insulator (plating) Filling in the through hole for forming the conductor layer) 11 Conductor layer 12 Core wiring board

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 層間絶縁体を厚さ方向に貫挿する導電性
バンプ、および層間絶縁体を厚さ方向に貫通する孔の内
壁面に設けたメッキ導電体層により、配線パターン層間
が電気的に接続された構成を有する多層配線板であっ
て、 前記メッキ導電体層を設けた貫通孔内が絶縁体で充填さ
れ、かつこのメッキ導電体層に対する導電性バンプによ
る電気的な接合は絶縁体の充填面に配置した導電体層を
介して行われていることを特徴とする多層配線板。
An electric connection between wiring pattern layers is provided by a conductive bump penetrating an interlayer insulator in a thickness direction and a plated conductor layer provided on an inner wall surface of a hole penetrating the interlayer insulator in a thickness direction. A multi-layer wiring board having a configuration in which the through hole provided with the plated conductor layer is filled with an insulator, and an electrical connection to the plated conductor layer by a conductive bump is made of an insulator. A multi-layer wiring board, wherein the multi-layer wiring board is formed through a conductor layer disposed on a filling surface of the multi-layer wiring board.
【請求項2】 コア基板の所定位置に厚さ方向に貫通す
る孔を設け、その内壁面をメッキ導電体層化してスルホ
ール接続部を形成する工程と、 前記スルホール接続部を設けた貫通孔内を絶縁体で充填
する工程と、 前記充填した少なくとも一方の絶縁体面に、前記スルホ
ール接続部に導通する導電体層を配置してコア配線板を
形成する工程と、 前記コア配線板面に絶縁性シートを介して層間接続用の
導電性バンプを一主面に設けた導電体箔を位置決め配置
して積層体化する工程と、 前記積層体を加圧一体化して絶縁性シートを貫挿する導
電性バンプ先端部を、前記スルホール接続部に導通する
導電体層に対接・電気的に接続した導電体箔張り積層板
を形成する工程と、 前記導電体箔を配線パターニングする工程とを有するこ
とを特徴とする多層配線板の製造方法。
2. A step of providing a hole penetrating in a thickness direction at a predetermined position of the core substrate, forming an inner wall surface thereof as a plated conductor layer to form a through-hole connection portion, and forming a through-hole connection portion provided with the through-hole connection portion. Filling with an insulator, forming a core wiring board by arranging a conductive layer conducting to the through-hole connection portion on at least one of the filled insulator faces, and insulating the core wiring board face from the insulating layer. A step of positioning and arranging a conductive foil having conductive bumps for interlayer connection provided on one main surface via a sheet to form a laminate, and a step of pressing and integrating the laminate to penetrate an insulating sheet. Forming a conductive foil-clad laminate in which the tip of the conductive bump is in contact with and electrically connected to the conductive layer that is electrically connected to the through-hole connecting portion; and a step of wiring patterning the conductive foil. Characterized by many A method for manufacturing a wiring board.
JP18508797A 1997-07-10 1997-07-10 Multilayered interconnection board and method for manufacturing it Pending JPH1131882A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18508797A JPH1131882A (en) 1997-07-10 1997-07-10 Multilayered interconnection board and method for manufacturing it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18508797A JPH1131882A (en) 1997-07-10 1997-07-10 Multilayered interconnection board and method for manufacturing it

Publications (1)

Publication Number Publication Date
JPH1131882A true JPH1131882A (en) 1999-02-02

Family

ID=16164612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18508797A Pending JPH1131882A (en) 1997-07-10 1997-07-10 Multilayered interconnection board and method for manufacturing it

Country Status (1)

Country Link
JP (1) JPH1131882A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100704927B1 (en) 2005-11-16 2007-04-09 삼성전기주식회사 Pcb using paste bump and method of manufacturing thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100704927B1 (en) 2005-11-16 2007-04-09 삼성전기주식회사 Pcb using paste bump and method of manufacturing thereof

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