JPH1131809A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it easy to connect each transfer electrode and shunt wiring in the shunt wiring structure in a vertical transfer register having a transfer electrode of 3 layers or more in the CCD solid-state image pickup device of total pixel reading system. SOLUTION: The solid-state image pickup device comprises a plurality of light receiving sections 2 arrayed in matrix, the vertical transfer register 3 having a transfer electrode 7 of 3 layers or more and arrayed every 2 lines of each light receiving section 2, the shunt wiring 14 formed on the vertical transfer register 3 and connected to the transfer electrode 7A through 7C. The transfer electrode 7A of the first layer is connected to the shunt wiring 14A between the light receiving section 2 and each transfer electrode 7B and 7C are connected to the shunt wiring 14B and 14C on the vertical transfer register 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device suitable for a CCD solid-state imaging device of an all-pixel readout system.

[0002]

2. Description of the Related Art FIG. 8 shows a main part of an image pickup area of a CCD solid-state image pickup device of an all-pixel reading system. When the CCD solid-state imaging device 41 is, for example, of an inter-line transfer (IT) type, a plurality of light receiving units 42 arranged in a matrix and performing a plurality of photoelectric conversions and a plurality of vertical CCD structures opposed to each light receiving unit row. An imaging area 44 including a transfer register 43;
Although not shown, it is configured to have a horizontal transfer register for transferring the signal charges transferred from the vertical transfer register 43 to the output unit.

The vertical transfer register 43 is shown in FIGS.
As shown in FIG. 8 (cross section taken along line AA in FIG. 8), a first polycrystalline silicon layer is formed on the transfer channel region of the silicon substrate 45 via a gate insulating film 46 of SiO ₂ or the like. The first transfer electrode 47A, the second transfer electrode 47B made of the second polycrystalline silicon layer, and the third transfer electrode 47C made of the third polycrystalline silicon layer are repeatedly arranged in the charge transfer direction. You. 48 is an interlayer insulating film. The first transfer electrode 47A, the second transfer electrode 47B, and the third transfer electrode 47C are commonly formed for the plurality of vertical transfer registers 43, respectively. Therefore, the first transfer electrode 47A, the second transfer electrode 47B, and the third transfer electrode 47C are sequentially overlapped between the light receiving units 42 adjacent in the vertical direction.

The vertical transfer register 43 is driven by three-phase driving pulses φ _{1 to} φ ₃ and has a first transfer electrode 47.
A, drive pulses φ ₃ , φ ₂ , φ ₁ are applied to the second transfer electrode 47B and the third transfer electrode 47C, respectively. 8 and 9, the light shielding Al layer and the like are omitted.

On the other hand, in a CCD solid-state imaging device, as a method of driving the vertical transfer register at a high speed, a shunt wiring using Al, WSi or the like having a smaller sheet resistance than polycrystalline silicon is formed in each vertical transfer register. There is known a technique in which a shunt wiring is connected to a corresponding transfer electrode, and a so-called shunt wiring structure is used to prevent deterioration of characteristics due to “rounding” of a drive pulse waveform applied to the transfer electrode.

[0006] This shunt wiring structure is HD (high quality).
It has been put to practical use in CCD solid-state imaging devices for TV and the like.

[0007]

When the shunt wiring structure is applied to the transfer electrode structure of the vertical transfer electrode 43 shown in FIG. 8, the first transfer electrode 47A of the lowermost first layer and the shunt wiring structure are applied. In order to establish the connection with the wiring on the vertical transfer register 43, as is clear from FIG. 9, the transfer electrode 47B of the second layer and the third transfer electrode 47C of the third layer
Must be avoided, and there are difficulties in manufacturing. The present invention
An object of the present invention is to provide a solid-state imaging device which solves such a manufacturing problem and enables a shunt wiring structure to be practically used in a vertical transfer register having three or more layers of transfer electrodes.

In the solid-state imaging device according to the present invention, the first-layer transfer electrode is connected to a shunt wiring between the light-receiving portions outside the vertical transfer register, and the second-layer and higher-layer transfer electrodes are connected. Are connected to the shunt wiring on the vertical transfer register.

In this configuration, the transfer electrode of the first layer in the vertical transfer register is connected to the shunt wiring between the light receiving units. A transfer electrode can be formed, and the processing of a contact portion for connecting the first-layer transfer electrode at the lowermost layer and the shunt wiring is simplified, so that a shunt in a vertical transfer register having three or more layers of transfer electrodes can be achieved. It becomes easy to manufacture a wiring structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state image pickup device according to the present invention comprises a plurality of light receiving sections arranged in a matrix, a vertical transfer register having three or more transfer electrodes arranged for each light receiving section row, A shunt wiring is provided on the vertical transfer register and connected to the transfer electrode. The first layer transfer electrode and the shunt wiring are connected between the light receiving units, and the second layer and higher transfer electrodes are connected to each other. Shunt wiring is connected to the vertical transfer register.

According to the present invention, in the solid-state image pickup device, the transfer electrodes of the second and higher layers between the light receiving sections are partially removed, and the transfer electrodes of the first layer and the shunt wiring are connected at the removed portions. Configuration.

Hereinafter, the solid-state imaging device of the present invention will be described with reference to the drawings. FIGS. 1 to 7 relate to a solid-state imaging device according to an embodiment of the present invention, and show a case where the invention is applied to an all-pixel read-out type interline transfer (IT) CCD solid-state imaging device.

FIG. 1 shows a schematic configuration of a CCD solid-state imaging device 1 according to one embodiment. The CCD solid-state imaging device 1 includes an imaging region 4 including a plurality of light receiving units (pixels) 2 that perform photoelectric conversion arranged in a matrix and a plurality of vertical transfer registers 3 having a CCD structure corresponding to each light receiving unit row. A horizontal transfer register 5 having a CCD structure, which is arranged at one end of the image pickup area 4 and to which signal charges from the vertical transfer register 3 are transferred, and an output unit 6 connected to the last stage of the horizontal transfer register 5.

In the CCD solid-state image pickup device 1, a light receiving section 2
After the signal charge generated by the light incident on the vertical transfer register 3 is read out, a three-phase driving pulse
₃ , φ ₂ , φ ₁ transfer to horizontal transfer register 5,
Further, the signal charges are transferred in the horizontal transfer register 5 by, for example, two-phase pulses and output from the output unit 6 as signals.

FIG. 2 shows a main part of this embodiment, in particular, FIG.
1 shows a transfer electrode structure provided with a shunt wiring 14 of a vertical transfer register 3 in an imaging region 4 of the CCD solid-state imaging device 1 of FIG. Since the CCD solid-state imaging device 1 is an all-pixel reading system, the transfer electrode 7 of the vertical transfer register 3 is formed of three polycrystalline silicon layers. That is, as shown in FIGS. 2 to 6, the vertical transfer register 3 is formed on the transfer channel region of the silicon substrate 11 from the first polycrystalline silicon layer via the gate insulating film 12 of, for example, SiO _2. A first transfer electrode 7A, a second transfer electrode 7B made of a second polycrystalline silicon layer, and a third transfer electrode 7C made of a third polycrystalline silicon layer are repeatedly arranged in the charge transfer direction. It is composed.

Each of the first, second and third transfer electrodes 7A, 7
B and 7C are mutually insulated by the interlayer insulating film 13. First, second and third transfer electrodes 7A, 7B and 7
C forms a 1-bit transfer section, and the first, second and third transfer electrodes 7A, 7B and 7C are formed corresponding to the respective light receiving sections 2.

Here, the first transfer electrode 7A is formed in common to all the vertical transfer registers 3 by passing between the light receiving sections 2 adjacent in the vertical direction. On the other hand, the second transfer electrode 7B and the third transfer electrode 7C are commonly formed for each of the three vertical transfer registers 3 so as to be connected between the light receiving units 2 which are adjacent in the vertical direction. Light receiving section 2 sandwiched between formed second and third transfer electrodes 7B and 7C
Between the two light receiving units 2 in the horizontal direction, that is, between the two light receiving units 2, the second and third transfer electrodes 7B and 7C are deleted so as not to be formed.

Therefore, only the first transfer electrode 7A is formed between the light receiving sections 2 on the line BB in FIG. 2, as shown in FIG. 3, and between the light receiving sections 2 on the line CC in FIG. As shown in FIG. 4, the first, second, and third transfer electrodes 7A, 7B, and 7C are formed in an overlapping state.

On each vertical transfer electrode register 3, a shunt wiring 14 [14A, 14B, 14C] made of, for example, Al, WSi or the like, in this example, WSi is interposed over the entire length in the vertical direction via an interlayer insulating film 13. Is formed. The shunt wirings 14A, 14B, and 14C are sequentially and repeatedly formed for each of the three vertical transfer registers 3.

As shown in FIGS. 2 and 3, each shunt wiring 14A is partially adjacent to the light receiving section 2 in the vertical direction.
The first transfer electrode 7 of the first layer through the contact hole 13 a of the interlayer insulating film 13 at the extension 15.
A is connected. 16A shows the contact portion.
Further, as shown in FIGS. 2 and 6, the shunt wiring 14B is provided on the vertical transfer register 3 through the contact hole 13b of the interlayer insulating film 13 to form the second-layer second transfer electrode 7B.
B. 16B shows the contact portion. Further, the shunt wiring 14C is connected to the third transfer electrode 7C of the third layer through the contact hole 13C of the interlayer insulating film 13 on the vertical transfer register 3, as shown in FIGS. 16C shows the contact portion.

These shunt wirings 14A, 14B, 1
4C are connected to, for example, Al bus lines 17, 18, and 19 formed outside the imaging area 4 on the opposite side of the horizontal transfer register 5, for example, and are connected to the bus line 1 respectively.
Three-phase drive pulses φ ₃ , φ ₂ and φ ₁ are applied through 7, 18 and 19, respectively. In FIG. 2, A
1 does not show the light-shielding layer and the like.

FIG. 7 is a cross-sectional view showing an example of a semiconductor structure of a portion including the light receiving portion and the vertical transfer register 3 of the CCD solid-state imaging device 1. An N-type impurity diffusion region 24, an N-type transfer channel region 26 forming the vertical transfer register 3, and a P-type channel stop region 27 are formed in a two-conductivity type, ie, a first P-type well region 23, Further, a P-type positive charge storage region 28 is formed on the N-type impurity diffusion region 24, and a second
Is formed to form the silicon substrate 11 described above.

Here, the photodiode PD formed by the PN junction j between the N-type impurity diffusion region 24 and the P-type well region 23 forms the light receiving section (photoelectric conversion section) 2.
Then, on the transfer channel region 26, the channel stop region 27 and the read gate 31 of the silicon substrate 11,
The transfer electrodes 7 [7A, 7B, 7C] made of the above-mentioned three layers of polycrystalline silicon are formed via the gate insulating film 12, and the shunt wires 14 [14A, 14B, 14] are further formed.
C] is formed.

According to the above configuration, the first, second, and third transfer electrodes 7 [7A, 7A,
7B, 7C], the first transfer electrode 7A of the lowermost layer is formed in common to all the vertical transfer registers 3 by passing between the light receiving units 2 which are vertically adjacent to each other, and is formed in the second layer. The second transfer electrode 7B of the third layer and the third transfer electrode 7C of the third layer are commonly formed for each of the three vertical transfer registers 3 so as to be connected between the light receiving units 2 adjacent in the vertical direction. By connecting the first transfer electrode 7A of the lowermost layer and the shunt wiring 14A between the light receiving sections 2 in which a part of the third transfer electrodes 7B and 7C have been deleted in advance,
Connection between the transfer electrode 7A and the shunt wiring 14A is facilitated. That is, since the contact hole 13a at this time only needs to be formed only in the interlayer insulating film 13 on the first transfer electrode 7A as shown in FIG. 3, the processing of the contact hole 13a becomes simple, accurate and reliable. First transfer electrode 7
A can be connected to the shunt wiring 14A.

On the other hand, the second transfer electrode 7B of the second layer and the third transfer electrode 7C of the third layer are
Since the contact holes 13b and 13c are connected to the shunt wirings 14B and 14C above, the contact holes 13b and 13c at this time are, as shown in FIG. 6 and FIG. Since the contact holes 13b and 13c need only be formed on the second transfer electrode 7B, the contact holes 13b and 13c can be formed easily and accurately and reliably.
Can be connected to the shunt wiring 14B, and the third transfer electrode 7C can be connected to the shunt wiring 14C. Therefore,
The production yield of the CCD solid-state imaging device 1 having three layers of transfer electrodes 7A to 7C and having a shunt wiring structure is improved, and practical use is possible.

With respect to the horizontal direction, the second and third transfer electrodes 7B and 7C are partially deleted, and three-layer transfer electrodes 7A, 7A,
Since the overlapping part of 7B and 7C becomes 2/3 of the conventional one,
The coupling capacitance between the transfer electrodes 7A, 7B, and 7C is reduced, the disturbance of the clock waveform for driving the vertical transfer register 3 is reduced, and the transfer electrode efficiency and the amount of charge handled can be improved.

The portion between the light receiving portions 2 of the third transfer electrode 7C of the third layer may be disconnected due to the thinness as shown in FIG. 4, but in the present embodiment, the portion in the horizontal direction Is partially deleted, the area of this portion is reduced to 2/3 of the conventional area, the probability of occurrence of disconnection is reduced, and a stable yield can be obtained. Therefore, for example, HD (high quality) TV
The present invention can be suitably applied to a CCD solid-state imaging device of an all-pixel readout method for use in a CCD.

As described above, in the embodiment of the present invention, 3
The case where the transfer electrode made of polycrystalline silicon is used has been described. However, the present invention can be applied to the case where four or more transfer electrodes are used. Further, the present invention is not limited to the interline transfer electrode (IT) type, but can be similarly applied to a frame interline transfer (FIT) type CCD solid-state imaging device.

[0027]

As will be understood from the above description, according to the solid-state imaging device of the present invention, the processing of the contact hole between the transfer electrode of the first layer and the shunt wiring is simplified, so that the solid-state imaging device is manufactured. The yield is improved.

In particular, when the transfer electrodes of the second and higher layers are deleted, the portion where the transfer electrodes of the third and higher layers overlap is reduced as compared with the conventional case. As a result, the disturbance of the clock waveform for driving the vertical transfer register is reduced, so that the transfer efficiency and the amount of charges handled are improved. In addition, since the inter-pixel portion of the uppermost transfer electrode is thin, there is a possibility of disconnection. However, in the present invention, since a part of the uppermost transfer electrode is deleted, the uppermost transfer electrode is correspondingly removed. Since the area of the transfer electrode is smaller than before, the probability of occurrence of disconnection is also reduced, and a stable yield can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram of a solid-state imaging device according to the present invention.

FIG. 2 is an explanatory diagram of an electrode structure of a solid-state imaging device according to the present invention.

FIG. 3 is a sectional view taken along line BB of FIG. 2;

FIG. 4 is a sectional view taken along the line CC of FIG. 2;

FIG. 5 is a sectional view taken along the line DD of FIG. 2;

FIG. 6 is a sectional view taken along line EE of FIG. 2;

FIG. 7 is an explanatory sectional view of a solid-state imaging device according to the present invention.

FIG. 8 is an explanatory diagram of a main part of an imaging region of a CCD solid-state imaging device of an all-pixel readout method.

FIG. 9 is a sectional view taken along line AA of FIG. 8;

[Explanation of symbols]

1,41 solid-state imaging device, 2,42 light receiving section, 3,43
Vertical transfer register, 4,44 imaging area, 5 horizontal transfer register, 6 output section, 7 [7A, 7B, 7C], 4
7 [47A, 47B, 47C] Transfer electrode, 11, 45
Silicon substrate, 12, 46 Gate insulating film, 13, 4
8 interlayer insulating film, 14 shunt wiring, 16 [16A,
16B, 16C] Contact part, 17, 18, 19
Bus line, 22 N-type silicon substrate, 23 first P
Well region, 24 N-type impurity diffusion region, 26 N-type transfer channel region, 27 P-type channel stop region,
28 P-type positive charge storage region, 29 second P-type well region, 31 read gate,

Claims (2)

[Claims] 1. A vertical transfer register having a plurality of light receiving sections arranged in a matrix, three or more layers of transfer electrodes arranged for each light receiving section row, and A shunt wire connected to an electrode, wherein the first-layer transfer electrode and the shunt wire are connected between the light-receiving units, and each of the second-layer and higher transfer electrodes and the shunt wire are A solid-state imaging device connected on the vertical transfer register. 2. The transfer electrode of the second layer or higher between the light receiving portions is partially removed, and the transfer electrode of the first layer and the shunt wiring are connected at the removed portion. Claim 1 characterized by the following:
20. The solid-state imaging device according to claim 20.