JPH1131397A - Analog fifo memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog FIFO memory device in which influence on signal components affected by a fixed pattern noise caused inside of an analog FIFO memory can be suppressed. SOLUTION: Analog multipliers 21, 26 are provided at an input side and an output side of an analog fifo memory 10, normal operation and inverse operation is alternately repeated for an input signal and an output signal synchronizing with input/output signals of the analog FIFO memory 10. A signal input/output characteristic of the analog FIFO memory 10 is not varied by this operation, but a fixed pattern noise caused inside of the analog FIFO memory 10 is modulated by the analog multiplier 26, spectrum of a fixed pattern noise having originally a low frequency is shifted to a high frequency side. Owing to the above, as a signal band and a fixed pattern noise are separated each other in frequency, a fixed pattern noise can be eliminated by a low pass filter 28. Therefore, even if this device is used for delaying a TV signal, TV picture quality is not deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog CMOS
The present invention relates to an LSI, and more particularly to a technique for reducing fixed pattern noise generated inside an analog FIFO memory.

[0002]

2. Description of the Related Art As is well known, although CMOS-LSI technology has been developed, one of the elements used in the field of analog CMOS-LSI design is an analog FIFO memory. An analog FIFO memory is a digital F
Like an IFO memory, this element delays an analog signal by a predetermined time and outputs it.

FIG. 22 is a diagram showing a basic configuration of an analog FIFO memory. As shown in FIG.
FO memory is basically an input buffer, an output buffer,
It comprises a storage element (memory cell) and an address counter. The analog FIFO memory specifies a storage element according to a memory cell selection signal output from an address counter, and outputs an analog signal value stored in the specified storage element in the form of a voltage or a charge through an output buffer. At that time, the voltage value or the charge amount input to the input buffer is written to the storage element. That is, analog FIF
The O memory performs a so-called read-modify-write operation on the memory cell specified by the address counter. The address counter is usually a cyclic counter, and the analog FIFO memory can delay a signal only during a cycle of an address.

[0004]

In an analog FIFO memory, a capacitance element is usually used as a storage element. However, since the capacitance element is easily affected by noise, an analog FIFO memory is used.
The input voltage Vin of the FO memory is added with an offset voltage Vnoise generated by accumulation of noise in the capacitance. It is known that the offset voltage Vnoise varies depending on the physical position of the storage element. That is, the output voltage Vout can be expressed by the following equation, where n is the address of the storage element. Vout = Vin + Vnoise (n) That is, the offset voltage Vnoise is expressed as a function of the address n of the storage element. Such an offset voltage Vnoise (n) is generally called fixed pattern noise.

FIG. 23 is a diagram for explaining the reason why fixed pattern noise appears in an analog FIFO memory. An analog FIFO memory is generally configured by connecting in parallel a memory bus in which a plurality of storage elements (usually using a capacitance element) are connected in parallel. FIG. 23A shows an analog FIFO memory in which four memory buses are connected in parallel using two multiplexers. In the analog FIFO memory shown in FIG. 23A, paths through which analog signals pass are classified into four paths for each memory bus to be stored. In this case, clock feedthrough generated by an analog switch used inside each multiplexer or parasitic charge at the time of switch off leaks to the storage element and is stored in the storage element as an offset voltage. Since the amount of leakage slightly differs for each analog switch, an offset voltage as shown in FIG. 23B is applied to the output signal. This is so-called fixed pattern noise.

[0006] Such fixed pattern noise becomes a major obstacle when using an analog FIFO memory for TV signal processing.

In the case of a TV signal, since the human eye is very sensitive to brightness, the specification of the ratio of noise to signal is extremely strict at -60 dB or less, and the fixed pattern noise of the analog FIFO memory is reduced. If these specifications are not satisfied, the image will appear as noise on the TV image.

On the other hand, the offset of the switching element is caused by a parasitic resistance, a parasitic capacitance, or a delicate timing of switching. At present, a precise analysis has not been made yet, and the variation of the offset is eliminated. It is extremely difficult. In addition, in consideration of the variation in element characteristics due to the normal LSI manufacturing process, it is almost impossible to suppress the fixed pattern noise to less than the TV signal specification by the manufacturing process.

Therefore, the analog FIFO memory is stored in T
When used for V signal processing, there is a problem that noise appears on a TV image due to such fixed pattern noise, and image quality is degraded.

[0010] There have been development examples of analog FIFO memories so far (K. Matsui, T. Matsuura et al., "CMOS v
edeo Filters Using Switched Capacitor 14MHz Circui
ts ", IEEE J. Solid-State Circuits, pp.1096-1101,198
5. Ken A. Nishimura, Paul R. Gray, "A Monolithic Anal
og Video Comb Filter in 1.2-um CMOS ", IEEE Jour
nal of Solid-State Circuits, VOL.28, NO.12, pp1331-13
39, DECEMBER 1993.) However, since such fixed pattern noise occurs, it has not been put to practical use in TV signal processing. This issue has been left unresolved for more than a decade since the first report.

In view of the above problems, the present invention provides an analog F
Analog FIFO capable of reducing the influence of fixed pattern noise generated inside an IFO memory on signal components
O memory device is provided,
In particular, it is an object of the present invention to eliminate adverse effects on TV image quality when used for TV signal processing.

[0012]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is an analog F
As an IFO memory device, an analog FIFO memory having a plurality of storage elements for storing analog signals, delaying an input analog signal by a predetermined time, and outputting in an input order;
An output-side conversion unit that performs a conversion on the output signal of the analog FIFO memory to reduce the effect of fixed pattern noise generated inside the analog FIFO memory on a signal component; And an input-side conversion unit for performing a conversion reverse to the conversion of the output-side conversion unit.

According to the first aspect of the present invention, the fixed-pattern noise generated inside the analog FIFO memory is converted by the output-side converter so that the influence on the signal component is reduced. At this time, the signal component is also converted by the output-side conversion unit. However, the input signal of the analog FIFO memory is subjected to the conversion opposite to the conversion of the output-side conversion unit by the input-side conversion unit. Is not converted at all, and the original signal waveform is kept. Therefore, without affecting the signal components, the analog FI
The effect of fixed pattern noise generated inside the FO memory on signal components can be reduced.

According to a second aspect of the present invention, the output-side converter in the analog FIFO memory device of the first aspect modulates the frequency so that the frequency of the fixed pattern noise transits to a higher frequency side than the signal band.

According to the second aspect of the present invention, the frequency of the fixed pattern noise generated inside the analog FIFO memory is shifted to a higher frequency side than the signal band by the frequency modulation by the output side conversion unit, and the frequency characteristic of the signal component is changed. Does not change, so that the fixed pattern noise and the signal component can be separated in frequency. Therefore, the influence of the fixed pattern noise on the signal component can be reduced without affecting the signal component.

According to a third aspect of the present invention, in the analog FIFO memory device according to the second aspect, the input side conversion unit corrects an input signal of the analog FIFO memory in synchronization with a signal input / output timing of the analog FIFO memory. Inverting operation and inverting operation are performed alternately, and the output-side converter alternately performs forward operation and inverting operation on the output signal of the analog FIFO memory in synchronization with the signal input / output timing of the analog FIFO memory. Assumed to be performed.

According to the third aspect of the present invention, the fixed pattern noise is alternately subjected to the normal rotation operation and the inversion operation in synchronization with the signal input / output timing of the analog FIFO memory by the output side conversion unit. Of the signal input / output operation. On the other hand, the input signal of the analog FIFO memory device performs the normal rotation operation and the inversion operation alternately in synchronization with the signal input / output timing of the analog FIFO memory by the input-side conversion unit. Since the normal rotation operation and the inversion operation are alternately performed in synchronization with the signal input / output timing of the FIFO memory, the output signal of the analog FIFO memory device becomes only a signal of the normal phase or the opposite phase with respect to the input signal. . That is, the signal components are not subjected to frequency modulation. For this reason, the frequency of the fixed pattern noise shifts to the high frequency side by half the frequency of the signal input / output operation of the analog FIFO memory. Therefore, the fixed pattern noise and the signal component can be reliably separated in frequency.

According to a fourth aspect of the present invention, in the analog FIFO memory device according to the third aspect, the input-side converter includes a first frequency divider for dividing a clock signal for driving the analog FIFO memory; For the input signal of the analog FIFO memory, when the logical level of the output signal of the first frequency divider is one logical level, the normal operation is performed, and when the logical level of the output signal is another logical level, the inverting operation is performed. An input-side signal inverting unit, wherein the output-side converter includes a second frequency divider for dividing a clock signal for driving the analog FIFO memory, and an output signal of the analog FIFO memory. Output side signal inverting means for performing a normal operation when the logical level of the output signal of the second frequency divider is one logical level and performing an inverting operation when the logical level is another logical level. It is assumed that example.

According to the invention of claim 4, the input-side conversion unit and the output-side conversion unit in the invention of claim 3 can be realized with a simple configuration.

According to a fifth aspect of the present invention, in the analog FIFO memory device of the third aspect, the analog FIFO memory has a variable number of delay stages, which is the number of signals to be held, and the analog FIFO memory device includes The output signal of the side conversion unit is inverted when the number of delay stages of the analog FIFO memory is either an even number or an odd number, and the signal is not inverted when the other is the other.

According to the fifth aspect of the present invention, the analog FIF
Regardless of the number of delay stages of the O memory, the output signal can always be fixed to one of the normal phase output and the negative phase output.

According to a sixth aspect of the present invention, the analog FIFO memory device according to the third aspect includes an even number of the analog FIFO memories, and each of the analog FIFO memories operates in parallel and access is sequentially performed in a cyclic manner. And the input-side conversion unit is configured to include the even-numbered analog FIFOs.
The input side of the O-memory is provided with input-side signal inverting means for inverting a signal every other order in the access order, and the output-side conversion section outputs the output of the even-numbered analog FIFO memories. It is assumed that the output side signal inverting means for inverting the signal is provided every other access order on the side.

According to the sixth aspect of the present invention, the analog FIFO
Even if no means for alternately performing the normal rotation operation and the reverse operation in synchronization with the signal input / output operation of the O memory is not provided, the input side of the even number of analog FIFO memories is provided every other access order.
By providing input-side signal inversion means for inverting a signal and providing output-side signal inversion means for inverting a signal every other access order on the output side, frequency modulation can be performed only on fixed pattern noise. . Therefore,
With a simple circuit configuration, fixed pattern noise and signal components can be reliably separated in frequency.

According to a seventh aspect of the present invention, in the analog FIFO memory device according to the third aspect, the analog FIFO
The O memory includes an even number of memory buses to which a plurality of storage elements for storing analog differential signals are respectively connected, an input-side multiplexer that sequentially inputs the input analog differential signals to each memory bus in order, An output-side multiplexer that sequentially and cyclically outputs an analog differential signal from each memory bus, wherein the input-side conversion unit includes an even-numbered memory bus that outputs an analog differential signal every other signal in the signal input order. The input signal is connected to the input side multiplexer so that the motion signal is inverted and input,
It is assumed that the output-side converter is configured by connecting the even-numbered memory buses to the output-side multiplexer such that an analog differential signal is inverted and output every other memory bus in the order of signal output.

According to the seventh aspect of the present invention, the analog FIF
Even if there is no means for alternately performing a normal rotation operation and a reverse operation in synchronization with the signal input / output operation of the O memory, an analog differential signal is inverted and input every other number of memory buses in the order of signal input. By connecting to the input-side multiplexer so as to connect the output-side multiplexer so that an analog differential signal is inverted and output every other signal in the order of signal output, frequency modulation can be performed only on fixed pattern noise. Therefore, the fixed pattern noise and the signal component can be reliably separated in frequency with a simple circuit configuration.

In the invention according to claim 8, the analog FIFO memory device according to claim 1 is used for delaying a TV signal, and the output-side converter visually removes fixed pattern noise from a TV image. Frequency modulation.

According to the eighth aspect of the present invention, the fixed pattern noise generated inside the analog FIFO memory by the frequency modulation by the output-side converter is visually removed from the TV image, and the frequency characteristic of the signal component does not change. The effect of fixed pattern noise on signal components
It can be visually reduced on the image.

According to a ninth aspect of the present invention, in the analog FIFO memory device according to the eighth aspect, the input-side conversion unit includes
The analog FIFO is synchronized with the image update timing.
The normal rotation operation and the inversion operation are alternately performed on the input signal of the O memory, and the output side conversion unit performs the normal rotation operation on the output signal of the analog FIFO memory in synchronization with the update timing of the TV image. And the inversion operation are performed alternately.

According to the ninth aspect of the present invention, the fixed pattern noise is generated by alternately performing the normal rotation operation and the reverse operation in synchronization with the update timing of the TV image by the output side conversion unit. The noise is averaged out. On the other hand, the input signal of the analog FIFO memory is alternately subjected to the normal rotation operation and the inversion operation in synchronization with the update timing of the TV image by the input-side conversion unit, and the output signal of the input-side conversion unit is synchronized with the update timing of the TV image. Since the normal rotation operation and the inversion operation are alternately performed in synchronization, the output signal of the analog FIFO memory only becomes a signal of the normal phase or the negative phase with respect to the input signal. That is, the signal components are not subjected to frequency modulation. Therefore, the influence of the fixed pattern noise on the signal component can be visually reduced on the TV image.

According to a tenth aspect of the present invention, the output-side converter in the analog FIFO memory device of the first aspect performs voltage conversion such that the level of fixed pattern noise is compressed with respect to the signal level.

According to the tenth aspect of the present invention, the level of the fixed pattern noise generated inside the analog FIFO memory by the voltage conversion in the output side conversion unit is compressed with respect to the signal level, and the level of the signal component does not change. The fixed pattern noise and the signal component can be separated in terms of voltage level. Therefore, the influence of the fixed pattern noise on the signal component can be reduced without affecting the signal component.

In the eleventh aspect of the present invention, the analog FIFO memory device of the tenth aspect is characterized in that the analog FIFO memory device
An input-side converter for performing a voltage conversion on the input signal of the memory according to a logarithmic function, and an inverse function of a logarithmic function used for the voltage conversion in the input-side converter for the output signal of the analog FIFO memory. An output-side conversion unit that performs voltage conversion according to a certain exponential function is provided.

The solution taken by the twelfth invention is the following.
An analog FIFO memory device used for delaying a V signal has a plurality of storage elements for storing analog signals and a counter for sequentially specifying storage elements for inputting and outputting signals, and delays an input analog signal by a predetermined time. And an analog FIFO memory for outputting fixed pattern noise generated inside the analog FIFO memory in a TV image.
In order to change the correspondence between the storage element of the FIFO memory and the position on the TV image every time the TV image is updated, the analog FIFO memory counter is reset at a different timing every time the TV image is updated based on the TV vertical synchronization signal. Reset means.

According to the twelfth aspect of the present invention, the counter of the analog FIFO memory is reset at a different timing every time the TV image is updated by the reset means, so that the correspondence between the storage element of the analog FIFO memory and the position on the TV image can be obtained. , TV image so that fixed pattern noise is visually removed. Therefore, the influence of the fixed pattern noise on the signal component can be visually reduced on the TV image.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic principle of the present invention will be described.

FIG. 1 is a diagram for explaining the principle of fixed pattern noise reduction in the analog FIFO memory device according to the present invention. As shown in FIG. 1, an analog FIFO memory device according to the present invention includes an input-side conversion unit 102 that performs conversion F as preprocessing on a signal Vin (t, v) input to an analog FIFO memory 101, FIF
An output-side conversion unit 103 that performs an inverse conversion F- ¹ of pre-processing on a signal output from the O memory 101 is provided.

An analog FIFO memory as shown in FIG.
In the device, the input signal Vin (t, v) is sent to the input-side converter 102.
And the inverse transform F by the output side transform unit 103^-1To
As a result, it is output as it is without being affected by the conversion.
However, the lock generated inside the analog FIFO memory 101 is
The constant pattern noise N (t, v) is output by the output side conversion unit 103.
Inverse transformation F^-1By F^-1(N (t, v)) and output
Is done. Therefore, the output of the output side conversion unit 103 is Vin (t, v) + F^-1(N (t, v))  Becomes That is, the inverse conversion in the output side conversion unit 103
F^-1If set properly, fixed pattern noise can affect the signal.
In other words, the effect of shattering can be reduced. Moreover, the input side conversion unit
The conversion F in the output side conversion unit 103
Conversion F^-1If the conversion is set to the reverse, the input signal Vin (t, v)
Has no effect.

If the inverse conversion F ^-1 at the output side of the analog FIFO memory is regarded as a conversion for reducing the influence of fixed pattern noise generated inside the analog FIFO memory on the signal component, the conversion at the input side of the analog FIFO memory is considered. The transformation F corresponds to the inverse of this transformation.

According to the present invention, the conversion F and the inverse conversion F ^-1 are set from the viewpoint of time (or frequency), voltage, and even human vision, based on such a principle, so that they can be generated inside the analog FIFO memory. This reduces the effect of fixed pattern noise on the signal.

(First Embodiment) In an analog FIFO memory device according to a first embodiment of the present invention, the conversion F and the inverse conversion F ^-1 are set from the viewpoint of time (or frequency). In other words, focusing on the fact that fixed pattern noise generated inside an analog FIFO memory is likely to occur as a low-frequency component, the fixed-pattern noise is driven to a high-frequency component by applying the principle of a so-called chopper circuit to an analog FIFO memory, and then a filter is applied. To remove this.

FIG. 2 shows an analog FIFO according to this embodiment.
FIG. 2 is a diagram schematically illustrating a configuration of a memory device. As shown in FIG. 2, the analog FIFO memory device according to the present embodiment includes multipliers 2 and 3 on the input side and the output side of the analog FIFO memory 1, respectively. A low-pass filter 4 for removing components is provided.

FIG. 3 is a diagram showing waveforms of signals and fixed pattern noise in the analog FIFO memory device according to the present embodiment shown in FIG. In FIG. 3, (a) is the input signal S1, (b) is the signal component S2 of the output signal of the analog FIFO memory 1, (c) is the signal component S3 of the output signal of the output side multiplier 3, ( d) is analog FI
Fixed pattern noise N1 generated inside the FO memory 1,
(E) is a fixed pattern noise component N2 of the output signal of the output-side multiplier 3.

The input multiplier 2 and the output multiplier 3 drive the analog FIFO memory 1 in synchronization with the signal input / output timing of the analog FIFO memory 1 with respect to the input signal and output signal of the analog FIFO memory 1. The normal operation and the reverse operation are alternately and repeatedly performed (in synchronization with the clock signal). That is, the input-side multiplier 2 and the output-side multiplier 3 perform a so-called chopper operation.

By such an operation, FIGS.
As shown in (c), the waveform of the input signal S1 is once modulated by the input multiplier 2, but is again modulated by the output multiplier 3 to output the original signal waveform. However, since the fixed pattern noise generated inside the analog FIFO memory 1 is subjected only to the modulation by the output-side multiplier 3, the fixed pattern noise N1 as shown in FIG. The fixed pattern noise component N2 output from the output-side multiplier 3 in order to alternately perform the normal rotation operation and the inversion operation.
Has a waveform as shown in FIG.

FIG. 4 shows this as a frequency spectrum. That is, when the chopper operation is not performed, the signal and the fixed pattern noise cannot be separated because the spectrum of the fixed pattern noise exists in the signal band as shown in FIG. 4A, but as in the present embodiment, By performing the chopper operation, the spectrum of the fixed pattern noise can be driven out of the signal band as shown in FIG. 4B, so that the fixed pattern noise component can be removed by the low-pass filter (LPF) 4. become.

What is important here is to synchronize the signal input / output timing of the analog FIFO memory 1 with the switching timing between the normal rotation operation and the inversion operation of the input and output multipliers 2 and 3. As a result, when the operation of the input side and output side multipliers 2 and 3 is switched, the analog FIFO
Signal input / output of the memory 1 can be prevented from being performed, and a transient signal in the inversion operation by the multipliers 2 and 3 can be prevented from being stored in the analog FIFO memory 1. In a normal chopper circuit, such synchronization is unnecessary, but in this embodiment, the analog F
Synchronization between the input / output timing of the IFO memory 1 and the timing of switching between the normal rotation operation and the inversion operation of the input and output multipliers 2 and 3 is essential. This makes it possible to perform the chopper operation while completely maintaining the input signal waveform.

In FIG. 2, the drive clock signal (frequency fclk) of the analog FIFO memory 1 and the drive signal (frequency fclk / 2) of the input and output multipliers 2 and 3 are synchronized, so that the analog FIFO memory 1 And the timing of switching between the normal operation and the inversion operation of the input and output multipliers 2 and 3 are synchronized.

At this time, the input signal S1 is set as shown in FIG.
It is assumed that a DC component as shown in FIG. Then, the signal that passes through the input multiplier 2 and is written into the analog FIFO memory 1 has a frequency fcl as shown in FIG.
The signal S2 is modulated at k / 2. When the signal S2 is output from the analog FIFO memory 1, the signal S2 is similarly modulated by the output-side multiplier 3, so that it is converted into the original DC component as shown in FIG. That is, an operation completely opposite to the operation performed at the time of input is performed at the time of output, whereby the input signal waveform is completely restored.

When the input signal S1 is subjected to an operation of being rotated forward on the input side and rotated forward on the output side or an operation of being inverted on the input side and inverted on the output side, the output signal S3 is output in the normal phase. On the other hand, if the input signal S1 is subjected to an operation of being inverted at the input side and inverted at the output side or an operation of being inverted at the input side and inverted at the output side, the output signal S3 is inverted. Phase output signal, but in any case,
The signal and the fixed pattern noise can be separated in frequency.

FIG. 5 is a diagram showing a circuit configuration of the analog FIFO memory device according to the first embodiment of the present invention. In FIG. 5, reference numeral 10 denotes an analog FIFO memory, 21 denotes a first analog multiplier as input-side signal inversion means for alternately performing a normal operation and an inversion operation on an input signal, and 22 denotes a first analog multiplier 21 A first frequency divider 26 for generating and outputting a signal for switching control between the normal rotation operation and the inversion operation of the output side signal for alternately performing the normal rotation operation and the inversion operation on the signal output from the analog FIFO memory 10 A second analog multiplier as inverting means; 27, a second frequency divider for generating and outputting a signal for controlling switching between the normal operation and inversion operation of the second analog multiplier 26; This is a low-pass filter that removes high-frequency components from the output signal of the device 26. The first and second frequency dividers 22 and 27 divide the frequency of a clock signal for driving the analog FIFO memory 10 to thereby produce the first and second analog multipliers 2 and 27.
1 and 26 are generated by a simple configuration using D flip-flops 22a and 27a.

The input side converter 20 is constituted by the first analog multiplier 21 and the first frequency divider 22, and the output side converter by the second analog multiplier 26 and the second frequency divider 27. 25 are constituted.

The analog FIFO memory 10 includes a plurality of memory buses 12 respectively connected to a plurality of storage elements (memory cells) 11, a first address decoder 13 for designating an address of the memory bus 12 for inputting and outputting signals, A second address decoder 14 for designating an address on the memory bus 12 of the memory cell 11 for reading and writing a signal;
An input multiplexer 1 for inputting a signal to one memory bus 12 designated by a first address decoder 13
5. An output multiplexer 16 that outputs a signal from one memory bus 12 designated by the first address decoder 13, counts an externally applied clock signal,
A memory cell 11 for reading and writing signals to the first and second address decoders 13 and 14 based on the count data.
, An input buffer 18, and an output buffer 19.

The operation of the analog FIFO memory device according to this embodiment will be described.

The input signal is input to a first analog multiplier 21, which outputs a first frequency divider 22.
The input signal is alternately inverted or inverted according to the logic level of the control signal generated and output from the analog FIFO memory 10 and input to the analog FIFO memory 10.

In the analog FIFO memory 10, a read-modify-write operation is performed in synchronization with an externally applied clock signal. When the memory cell 11 for reading and writing a signal is designated by the counter 17, the first
The address of one memory bus 12 is designated by the address decoder 13 and the second address decoder 1
4 designates the address of one memory cell 11 in one memory bus 12. The output-side multiplexer 16 reads a signal stored in the one memory cell 11 specified by the second address decoder 14 from the one memory bus 12 specified by the first address decoder 13. The read signal is output from the analog FIFO memory 10 via the output buffer 19.

On the other hand, the signal input to the analog FIFO memory 10 is input to the input multiplexer 15 via the input buffer 18. Input side multiplexer 15
Inputs an input signal to the one memory bus 12 specified by the first address decoder 13. The one memory bus 12 to which the signal is input causes the one memory cell 11 designated by the second address decoder 14 to store an input signal.

The output signal of the analog FIFO memory 10 is input to a second analog multiplier 26, and the second analog multiplier 26 outputs the analog FIFO according to the logic level of the control signal generated and output from the second frequency divider 27. Memory 10
Are alternately forward or inverted and output. The low-frequency noise component of the output signal of the second analog multiplier 26 is removed by the low-pass filter 28.

FIG. 6 shows the signal read / write operation of the analog FIFO memory 10 and the first and second analog multipliers 21,
26 is a timing chart illustrating a timing of a switching operation between a normal rotation operation and a reverse operation of the control unit. As shown in FIG. 6, in the analog FIFO memory 10, the signal stored in the memory cell 11 designated by the counter 17 is first read, and then the signal is written to the memory cell 11 from which the signal was read. That is, a so-called read-modify-write operation is performed.

The first and second analog multipliers 2 are synchronized with the signal read / write operation of the analog FIFO memory 10.
Steps 1 and 26 alternately repeat the normal rotation operation and the reverse operation. This synchronization is performed by the first and second analog multipliers 21,
26 is realized by controlling a clock signal for driving the analog FIFO memory 10 by a signal generated by dividing the frequency by the first and second frequency dividers 22 and 27. Since the first and second frequency dividers 22 and 27 together constitute a frequency divider, if the frequency of the clock signal for driving the analog FIFO memory 10 is fclk, the first and second analog multipliers 21 and 27 will be described. The frequency of the control signal applied to 26 is fclk / 2. Therefore, the analog FI
The fixed pattern noise generated inside the FO memory 10 is the first
And by the chopper operation of the second analog multipliers 21 and 26, the frequency is shifted toward the high frequency side by fclk / 2. Therefore, in order to separate the fixed pattern noise from the signal band, it is preferable to satisfy the following conditions. fclk> 4 × fsignal where fsignal is the upper limit frequency of the signal band.

In FIG. 6, the first analog multiplier 2
Since the normal rotation operation and the inversion operation of 1 and 26 are always the same, when the number of delay stages of the analog FIFO memory 10 is an even number, the output signal becomes a normal-phase output signal, while the number of delay stages of the analog FIFO memory 10 is an odd number. , The output signal is an inverted-phase output signal. In any case, the signal and the fixed pattern noise can be separated in frequency.

When the first analog multiplier 21 performs a normal operation, the second analog multiplier 26 performs an inversion operation, while when the first analog multiplier 21 performs an inversion operation, the second analog multiplier 26 performs a second operation. May be controlled to perform the normal rotation operation. In this case, the analog FI
When the number of delay stages of the FO memory 10 is an even number, the output signal becomes an inverted-phase output signal, while the analog FIFO memory 1
When the number of delay stages of 0 is an odd number, the output signal is a positive-phase output signal. Even in this case, the signal and the fixed pattern noise can be frequency separated in any case.

The operation of the chopper employed in this embodiment is effective when removing low-frequency noise.
It is not effective for high frequency noise. For example, if high frequency noise having a frequency of fclk / 2 is generated from the analog FIFO memory 10, the frequency fclk as in the present embodiment is assumed.
When k / 2 modulation is applied, this high-frequency noise becomes low-frequency noise and overlaps with the signal band and cannot be removed well. That is, the present embodiment is realized by paying attention to the fact that the fixed pattern noise generated in the analog FIFO memory 10 has a low frequency.
This will be described.

FIG. 7 is a diagram showing an example of addressing of a memory cell in the analog FIFO memory 10.
1 is a memory cell, and 12 is a memory bus. In the figure,
5A shows vertical addressing for vertically addressing the memory bus 12, and FIG.
2 shows a parallel addressing in which addressing is performed in parallel to 2. If the analog FIFO memory 10 has n
Assuming that the memory cell 11 is constituted by m memory buses 12 connected to the memory cells 11, respectively, FIG.
In the case of vertical addressing as shown in FIG. 7A, the fixed pattern noise has a frequency component of fclk / m.
In the case of parallel addressing as shown in (b), the fixed pattern noise has a frequency component of fclk / n. Since m and n are usually sufficiently large numbers, the frequency of the fixed pattern noise can be considered to be sufficiently lower than the clock frequency fclk for driving the analog FIFO memory 10. Therefore, the chopper operation employed in the present embodiment effectively acts to remove fixed pattern noise.

FIG. 8 shows an analog FIFO according to this embodiment.
FIG. 10 is a diagram illustrating a modification of the memory device, and is an analog FIFO.
The present embodiment is applied when the number of delay stages of the memory 10 is made variable. 8, the configuration is the same as that of the analog FIFO memory device according to the present embodiment shown in FIG. 5, except that a signal inverting means 29 is added after the low-pass filter 28. The signal inverting means 29 makes the phase of the output signal constant with respect to the input signal even if the number of delay stages of the analog FIFO memory 10 changes. In this modification, the signal inverting means 29 receives a signal for controlling the number of delay stages of the analog FIFO memory 10 as input, and converts the signal output from the low-pass filter 28 only when the number of delay stages of the analog FIFO memory 10 is odd. Invert.

The analog FI according to the present embodiment shown in FIG.
In the FO memory device, when the number of delay stages in the analog FIFO memory 10 is an even number, the input signal is inverted by the first analog multiplier 21 to be analog FIFO.
When input to the memory 10, it is inverted by the second analog multiplier 26 when output from the analog FIFO memory 10, and is inverted by the first analog multiplier 21 and input to the analog FIFO memory 10. When output from the analog FIFO memory 10, the second
Of the analog multiplier 26. Therefore, the output signal becomes a positive-phase output with respect to the input signal.

However, when the number of delay stages in the analog FIFO memory 10 is odd, the input signal is inverted by the first analog multiplier 21 to be analog FIFO.
When input to the memory 10, when output from the analog FIFO memory 10, the signal is inverted by the second analog multiplier 26, while it is inverted by the first analog multiplier 21 and input to the analog FIFO memory 10. Output from the analog FIFO memory 10
Of the analog multiplier 26. Therefore, the output signal has the opposite phase output to the input signal.

Therefore, the analog FIFO memory 10
If the number of delay stages is made variable, the output signal switches between the normal phase and the reverse phase in accordance with the number of delay stages in the analog FIFO memory 10.

Therefore, in a modification of the present embodiment shown in FIG. 8, a signal inverting means 29 is provided after the low-pass filter 28 so that the signal inverting means is used only when the number of delay stages in the analog FIFO memory 10 becomes odd. 29 is used to invert the output signal. As a result, regardless of the number of delay stages of the analog FIFO memory 10, a positive-phase output signal can always be obtained for the input signal.

The signal inverting means 29 is an analog FIFO.
Only when the number of delay stages of the O memory 10 is an even number, the signal output from the low-pass filter 28 may be inverted. In this case, an output signal having the opposite phase to the input signal can always be obtained.

Further, when the first analog multiplier 21 performs a normal operation, the second analog multiplier 26 performs an inversion operation, and when the first analog multiplier 21 performs an inversion operation, the second analog multiplier 26 performs a second operation. The same effect can be obtained by providing the signal inverting means 29 even when the analog multiplier 26 is controlled to perform the normal rotation operation. In this case, when the signal inverting means 29 inverts the signal output from the low-pass filter 28 only when the number of delay stages of the analog FIFO memory 10 is an even number, the input signal always has a positive phase output. When a signal can be obtained and the signal inverting means 29 inverts the signal output from the low-pass filter 28 only when the number of delay stages of the analog FIFO memory 10 is odd, the signal is always inverted with respect to the input signal. A phase output signal can be obtained.

In the present embodiment, when the analog FIFO memory 10 handles analog differential signals, a signal inverting circuit having a simple configuration as shown in FIG. 9 is used instead of the analog multipliers 21 and 26. it can. 9, 31a and 31b are signal input terminals, 32 is a control signal input terminal, 33a and 33b are signal output terminals, 34a and 34.
b, 34c and 34d are switches, and 35a and 35b are sample and hold circuits (SH). In the case of the normal operation of the signal, the switches 34a and 34d are turned on and the switches 34b and 34c are turned off to input the signal to the sample and hold circuits 35a and 35b. The switch 34c is turned on and the switches 34a and 34d are turned off, and the polarity of the signal is input to the sample and hold circuits 35a and 35b. Switching of the switches 34 a to 34 d is controlled by a control signal input to the terminal 32. With such a simple configuration, the signal output terminals 33a, 33b
Can be inverted at a predetermined timing.

(Second Embodiment) In a second embodiment of the present invention, the chopper operation described in the first embodiment is applied to an analog FIFO memory device having a parallel configuration.

FIGS. 10A and 10B are diagrams showing a case where the chopper operation described in the first embodiment is applied to an analog FIFO memory device having a parallel configuration. FIG. 10A is a diagram showing a schematic configuration, and FIG. () Is a timing chart showing the correspondence between the memory to be accessed and the operation of the multiplier in the analog FIFO memory device shown in (a). The analog FIFO memory device shown in FIG. 10A includes first and second analog FIFO memories 1a and 1b, and switches input and output of signals by first and second switching means 5 and 6. The read-modify-write operation is sequentially and alternately performed on the first analog FIFO memory 1a and the second analog FIFO memory 1b. In the analog FIFO memory device having the parallel configuration, the operation speed required for each analog FIFO memory can be suppressed low by circulating the plurality of analog FIFO memories.

An analog FIFO memory device having a parallel configuration is usually configured using an even number of analog FIFO memories. In this case, if the normal rotation operation and the reverse operation are alternately performed by the chopper operation as described in the first embodiment, the same operation is always performed for each analog FIFO memory. For example, FIG.
As shown in (b), the first analog FIFO memory 1
a is accessed, the input and output multipliers 2,
3, the forward operation is always performed, while when the second analog FIFO memory 1b is accessed, the inverting operation is always performed by the input and output multipliers 2, 3.

Therefore, in the analog FIFO memory device having a parallel configuration composed of an even number of analog FIFO memories, when performing the chopper operation, each analog FIFO memory
Since the operation for the input / output signal of the memory is fixed to either the normal operation or the reverse operation, it is not necessary to alternately switch the normal operation and the reverse operation for each analog FIFO memory input / output signal every clock cycle. Absent. That is, the same processing as the chopper operation can be performed without using means for alternately performing the normal rotation operation and the reverse operation.

FIG. 11 is a diagram showing a configuration of an analog FIFO memory device according to a second embodiment of the present invention. The analog FIFO memory device having a parallel configuration has a normal rotation operation and an inversion operation of an analog multiplier and the like. FIG. 6 is a diagram showing a state where a chopper operation is realized without using a means for performing the operations alternately.
In FIG. 11, reference numerals 41a and 41b denote first and second analog FIFO memories having the same configuration as the analog FIFO memory 10 in the analog FIFO memory device according to the first embodiment shown in FIG. Also, 42
Is switching means for distributing an input signal to the first analog FIFO memory 41a and the second analog FIFO memory 41b, and 43 is a first analog FIFO memory for inverting the input signal.
Input-side signal inverting means for inputting to the O memory 41a, 44 is an output-side signal inverting means for inverting the signal output from the first analog FIFO memory 41b, 45 is a sample-hold circuit, and 46 is a low-pass filter.

The operation of the analog FIFO memory device shown in FIG. 11 will be described. The input signal is distributed by the switching means 42 to the first analog FIFO memory 41a or the second analog FIFO memory 41b. First and second
The first analog FIFO memories 41a and 41b are driven by a clock signal.
The input signal distributed by the switching means 42 is input to 1a after being inverted by the input-side signal inverting means 43, while the input signal distributed by the switching means 42 is directly input to the second analog FIFO memory 41b. You.

The output signal of the first analog FIFO memory 41a is inverted by the output-side signal inversion means 44 and input to the sample-and-hold circuit 45, while the output signal of the second analog FIFO memory 41b is used as it is. Is input to The sample and hold circuit 45 includes the first and second analog FIFO memories 41.
The output signals a and 41b are alternately sampled and held and output. Thereby, the first analog FIFO memory 4
The fixed pattern noise generated in 1a is inverted and output, while the fixed pattern noise generated in the second analog FIFO memory 41b is output as it is.

Therefore, the first and second analog FIs
If the FO memories 41a and 41b are designed with a congruent layout pattern on the LSI and the generated fixed pattern noises are almost the same, the sign of the fixed pattern noise input to the low-pass filter 46 is inverted every operation clock. Is output. That is, since the frequency of the fixed pattern noise is modulated to a high frequency, it can be easily removed by the low-pass filter 46.

That is, in this embodiment, the input-side signal inverting means 4 is connected to the input side of the first analog FIFO memory 41a.
3 and the second analog FIFO memory 41b
By not providing the signal inverting means on the input side, the function equivalent to the input side conversion unit 20 in the analog FIFO memory device according to the first embodiment shown in FIG. 5 can be said to be realized. Further, the first analog FIFO memory 4
By providing the output-side signal inverting means 44 on the output side of 1a and not providing the signal inverting means on the output side of the second analog FIFO memory 41b, the analog FIFO memory device according to the first embodiment shown in FIG. It can be said that a function equivalent to the output-side conversion unit 25 is realized. Therefore, there is no need for a means such as a frequency divider and an analog multiplier for alternately performing a normal rotation operation and a reverse operation, so that the circuit configuration is simplified.

The input signal inverting means 43 may be provided on either input side of the first and second analog FIFO memories 41a and 41b, and the output signal inverting means 44 may be provided in the first and second analog FIFO memories 41a and 41b. FIFO memory 41a,
It may be provided on any output side of 41b.

Further, in this embodiment, the analog FIFO
Although the number of memories was 2, an even number of analog FIFOs
An analog FIFO memory device having a memory can realize a chopper operation with a similar configuration. That is, the signal inverting means may be provided at every other access order on the input side of the even number of analog FIFO memories, and the signal inverting means may be provided at every other access order at the output side. With such a configuration, the chopper operation can be realized without using a means for alternately performing the normal rotation operation and the reverse operation.

(Third Embodiment) The third embodiment of the present invention is a parallel analog analog F shown in the second embodiment.
The configuration in which the chopper operation is realized without using the means for alternately performing the normal rotation operation and the reverse operation in the IFO memory device is applied to an analog FIFO memory which stores analog differential signals and operates independently.

FIG. 12 is a diagram showing a configuration of an analog FIFO memory device according to the third embodiment of the present invention. FIG.
2, an analog FIFO memory 50 stores analog differential signals, and includes an even number of memory buses 51 to which a plurality of memory cells are respectively connected, input-side and output-side multiplexers 52 and 53, an input buffer 54,
And an output buffer 55. The input-side multiplexer 52 selects one of the plurality of memory buses 51 and inputs an input signal from the input buffer 54, and the output-side multiplexer 53 selects one of the plurality of memory buses 51 and reads out the signal. Output to the output buffer 55. FIG. 12 omits a counter for specifying a memory cell for reading and writing a signal by counting an externally applied clock signal, and an address decoder for specifying an address of a memory bus and a memory cell. 58 is an analog FI
This is a low-pass filter that removes high-frequency components from the output signal of the FO memory 50.

The analog FIFO memory 50 shown in FIG.
Is characterized in that the connection between the positive and negative phase input terminals of the memory bus 51 and the output terminal of the input multiplexer 52 is reversed between the odd-numbered memory bus 51 and the even-numbered memory bus 51, and The connection between the positive and negative output terminals of the memory bus 51 and the input terminal of the output multiplexer 53 is reversed between the odd-numbered memory bus 51 and the even-numbered memory bus 51. Actually, the input / output terminals of the memory bus 51 are alternately laid out alternately for each memory bus 51.

Therefore, the fixed pattern noise generated in the odd-numbered memory bus 51 is output as it is, while the fixed pattern noise generated in the even-numbered memory bus 51 is inverted and output.

Therefore, the analog FIFO memory 50
Is vertical addressing for vertically addressing the memory bus 51 as shown in FIG. 7A, the sign of the output fixed pattern noise is inverted every clock. That is, when fixed pattern noise is generated inside each memory bus 51, the frequency of the fixed pattern noise can be modulated to a high frequency by arranging the layout alternately for each memory bus 51. Therefore, the fixed pattern noise can be easily removed by the low-pass filter 58 as in the second embodiment.

That is, in the present embodiment, the input-side multiplexer 52 is configured such that the analog differential signal is input to the odd-numbered memory bus 51 in the normal direction and the analog differential signal is inverted to the even-numbered memory bus 51. And the respective memory buses 51, it can be said that a function equivalent to the input-side converter 20 in the analog FIFO memory device according to the first embodiment shown in FIG. 5 is realized. The output-side multiplexer 53 is connected to each memory bus 51 so that the analog differential signal is output from the odd-numbered memory bus 51 in the normal direction and the analog differential signal is inverted from the even-numbered memory bus 51. By
It can be said that a function equivalent to that of the output-side converter 25 in the analog FIFO memory device according to the first embodiment shown in FIG. 5 is realized. Therefore, there is no need for a means such as a frequency divider and an analog multiplier for alternately performing a normal rotation operation and a reverse operation, so that the circuit configuration is simplified.

The connection between each memory bus 51 and the input-side multiplexer 52 and the output-side multiplexer 53 is not limited to that shown in this embodiment.
For example, the input-side multiplexer 52 and each memory bus 51 are connected such that the analog differential signal is invertedly input to the odd-numbered memory bus 51 and the analog differential signal is normally input to the even-numbered memory bus 51. The output-side multiplexer 53 and each of the output-side multiplexers 53 may be connected so that the analog differential signal is inverted from the odd-numbered memory bus 51 and the analog differential signal is output from the even-numbered memory bus 51. The memory bus 51 may be connected. In other words, each memory bus 51 has 1
Every other memory bus 51 is connected to the input multiplexer 52 so that the analog differential signal is inverted and input every other, and the analog differential signals are inverted and output every other memory bus 51 in the order of signal output. Output side multiplexer 53
Is connected, the chopper operation can be realized without using a means for alternately performing the normal rotation operation and the reverse operation.

(Fourth Embodiment) The analog FIFO memory device according to the first embodiment is based on the premise that it is used for delaying a TV signal. In addition to this, fixed pattern noise is made invisible on a TV image by utilizing the characteristics of human vision. That is, in the present embodiment, the effect of the fixed pattern noise on the signal is visually removed, and for this purpose, a chopper operation is used as in the first embodiment.

FIGS. 13A and 13B are diagrams for explaining the principle of visually removing the influence of fixed pattern noise by a chopper operation in this embodiment. FIG. 13A shows a fixed pattern without a chopper operation. A noise waveform, (b), is a fixed pattern noise waveform when a chopper operation is performed in the present embodiment.

In this embodiment, the chopper operation is performed in synchronization with the update timing of the TV image, and the cycle of the chopper operation is adjusted to the cycle of the vertical synchronization signal of the TV image. As a result, as shown in FIG. 13B, the sign of the fixed pattern noise component is inverted for each image. FIG.
In (b), the solid line indicates fixed pattern noise in the current image, and the broken line indicates fixed pattern noise in the next image. When the positive / negative of the fixed pattern noise component is inverted for each image in this manner, the visual average value becomes 0 (the dashed line in FIG. 13B). That is, a filter is applied according to the characteristics of human vision, and the fixed pattern noise becomes invisible to human eyes, so that the influence of the fixed pattern noise can be visually removed.

As described above, in the present embodiment, the influence of the fixed pattern noise is visually removed by modulating the fixed pattern noise appearing in the TV image at a high frequency that cannot be perceived by human eyes.

FIG. 14 shows an analog FIFO according to this embodiment.
FIG. 3 is a diagram illustrating a circuit configuration of an O memory device. In FIG. 14, the analog FIFO according to the first embodiment shown in FIG.
Components common to those of the memory device are denoted by the same reference numerals as in FIG. 61 is a third analog multiplier, 62 is a vertical synchronizing signal SH of the TV image and the analog FIFO memory 10
, A first control means for generating and outputting a first control signal Sa for controlling the third analog multiplier 61, a fourth analog multiplier 66, and a first control 67 A second control signal Sb which receives the signal Sa as input and generates and outputs a second control signal Sb for controlling the fourth analog multiplier 66;
The control means 68 receives the vertical synchronizing signal SH of the TV image and the clock signal for driving the analog FIFO memory 10, and controls the reset operation of the counter 17 of the analog FIFO memory 10.

The analog F according to this embodiment shown in FIG.
The operation of the IFO memory device will be described.

The first control means 62 uses the D flip-flop 62a to convert the TV image vertical synchronizing signal SH
A signal for controlling switching between the normal operation and the inversion operation of the analog multiplier 61 is latched by a clock signal by a D flip-flop 62b, and the signal is latched as a first control signal Sa as a third analog multiplier. Input to 61. An input signal of the analog FIFO memory device is first supplied to a first control signal Sa by a third analog multiplier 61.
Is modulated at the frequency of the vertical synchronizing signal SH of the TV image. The input signal modulated by the third analog multiplier 61 is input to the first analog multiplier 21, and the first analog multiplier 21 uses the analog FIFO memory 1.
The signal is modulated at half the frequency of the drive clock signal of 0 and input to the analog FIFO memory 10.

The signal output from the analog FIFO memory 10 is first modulated by the second analog multiplier 26 at half the frequency of the driving clock signal of the analog FIFO memory 10, and then the high-frequency component is reduced by the low-pass filter 28. Removed. The signal from which the high-frequency component has been removed is modulated by the fourth analog multiplier 66 at the frequency of the vertical synchronization signal SH of the TV image according to the second control signal Sb.

Here, the operation of receiving the input signal of the analog FIFO memory device by the third analog multiplier 61 and the fourth analog multiplier 66 is the reverse operation, and as described in the first embodiment. First analog multiplier 2
Since the operation received by the first and second analog multipliers 26 is the reverse operation, the input signal of the analog FIFO memory device is supplied to the first to fourth analog multipliers 21, 26, 6
The signal is delayed by the number of delay stages of the analog FIFO memory 10 without being affected by the signal operation by the signals 1 and 66, and is output with the same waveform as that at the time of input.

However, the fixed pattern noise generated inside the analog FIFO memory 10 is reduced by the second analog multiplier 2
6 undergoes a modulation operation, the frequency of which is shifted to a higher frequency side and is therefore removed by the low-pass filter 28. Further, the fixed pattern noise generated inside the analog FIFO memory 10 is reduced by the fourth analog multiplier 66.
Is inverted for each image, so that only the average value of the fixed pattern noise is visible on the TV image, so that the influence of the fixed pattern noise is also visually removed.

The input signal is output after being delayed by the delay time of the analog FIFO memory 10. Therefore, in order to accurately return the output signal to the original signal, the second control signal Sb is set to be more analog FI than the first control signal Sa.
The signal must be delayed by the delay time of the FO memory 10 and given to the fourth analog multiplier. Therefore, analog FIF
A signal synchronized with the cycle is output from the counter 17 of the O memory 10 and the second control means 67 is used by using this signal.
Thus, the first control signal Sa is delayed by the delay time of the analog FIFO memory 10 and output as the second control signal Sb.

FIG. 15 is a signal waveform diagram showing the relationship between the vertical synchronizing signal SH of the TV image and the first and second control signals Sa and Sb. As shown in FIG. 15, the second control signal Sb
Is delayed by the delay time of the analog FIFO memory 10 compared to the first control signal Sa. This is analog FI
Since the output signal of the FO memory 10 is delayed with respect to the input signal by the delay time of the analog FIFO memory 10, the multiplication operation by the fourth analog multiplier 66 is also performed in comparison with the multiplication operation by the third analog multiplier 61. This is because it is necessary to delay by a delay time of 10.

After the high-frequency component is removed from the output signal of the analog FIFO memory 10 by the low-pass filter 28, the fourth analog multiplier 66 performs the normal operation and inversion according to the logical level of the second control signal Sb. Since the operation is alternately performed, the input signal is completely restored.

Further, in order to effectively perform the chopper operation according to the present embodiment, it is necessary to fix the position where the fixed pattern noise occurs in the TV image. FIG. 16 is a diagram showing the correspondence between the pixels of the TV image and the addresses of the analog FIFO memory. Normally, the delay time in the analog FIFO memory is not synchronized with the cycle of the horizontal line of the TV image, and therefore, as shown in FIGS.
The address of the analog FIFO memory corresponding to the pixel on the TV image changes for each image. Therefore, TV
In an image, the fixed pattern noise appears as pattern noise flowing for each image.

Therefore, in this embodiment, a third control means 68 comprising a D flip-flop 68a and a NAND gate 68b is provided, and the third control means 68 converts the TV image vertical synchronizing signal SH into a counter 17 of the analog FIFO memory 10. Of the analog FIFO memory 10 in synchronization with the vertical synchronizing signal SH of the TV image.
Is reset. By such an operation, the position where the fixed pattern noise occurs on the TV image can be fixed, so that the influence of the fixed pattern noise can be visually and reliably removed.

The chopper operation according to the present embodiment is not only performed in combination with the first embodiment, but also has an effect sufficient to visually remove the influence of fixed pattern noise even if performed alone. can get.

FIG. 17 is a diagram showing a modification of the analog FIFO memory device according to the fourth embodiment of the present invention, and is a diagram showing a configuration in which the chopper operation according to the present embodiment is independently performed. is there. 17 is compared with FIG. 14, the first and second analog multipliers 21 and 26, the first and second frequency dividers 22 and 27, and the low-pass filter 28
Is omitted, the input signal modulated by the third analog multiplier 61 is input to the analog FIFO memory 10, and the signal output from the analog FIFO memory 10 is directly input to the fourth analog multiplier 66. It is supposed to be. The input side converter 60 is constituted by the third analog multiplier 61 and the first control means 62, and the fourth analog multiplier 66 and the second control means 67
The output side conversion unit 65 is configured by the above. With the configuration shown in FIG. 17, fixed pattern noise can be visually removed from a TV image.

(Fifth Embodiment) In the fifth embodiment of the present invention, similarly to the fourth embodiment, fixed pattern noise is made invisible on a TV image by utilizing the characteristics of human vision. By controlling the reset timing of the counter of the analog FIFO memory 10 from the outside, the same effect as the chopper operation according to the fourth embodiment can be obtained.

FIG. 18 is a diagram showing a configuration of an analog FIFO memory device according to the fifth embodiment of the present invention. FIG.
In FIG. 8, the same components as those of the analog FIFO memory device according to the first embodiment shown in FIG. 71 is a vertical synchronizing signal SH of the TV image
A first counter 72 for counting the rising or falling edge of the counter counts a clock signal for driving the analog FIFO memory 10, and when the counted value reaches an upper limit corresponding to the counted value of the first counter 71, This is a second counter for resetting the counter 17 of the FIFO memory 10. The first and second counters 71 and 72 constitute a reset unit.

FIG. 19 is a timing chart showing the operation of the analog FIFO memory device shown in FIG. FIG.
As shown in FIG. 9, the first counter 71 counts the falling edge of the vertical synchronizing signal SH of the TV image. The upper limit of the count value of the second counter 72 is set according to the count value of the first counter 71. In FIG. 19, when the count value of the first counter 71 is "0", m0 is set, when it is "1", m1 is set, when it is "2", m2 is set, and when it is "3", m3 is set.
Are set as the upper limit values of the count value of the second counter 72, respectively. The second counter 72 has an analog FIFO
The clock signal for driving the memory 10 is counted, and when the counted value reaches the upper limit set according to the counted value of the first counter 71, the reset signal SR is raised, and the counter 17 of the analog FIFO memory 10 is activated. Reset. As a result, the time from the falling edge of the vertical synchronizing signal SH of the TV image to the rising edge of the reset signal SR differs for each TV image (time t0, t).
1, t2, t3).

With such an operation, the relationship between the pixels of the TV image and the memory address of the analog FIFO memory 10 designated by the counter 17 is shifted for each image according to the count value of the first counter 71. . In other words, the fixed pattern noise is modulated for each image, and it can be said that the first counter 71 plays the role of setting the modulation mode of the fixed pattern noise for each image. Therefore, if this modulation is a visually appropriate frequency, the fixed pattern noise is averaged out on the TV image, so that it becomes invisible to human eyes and can be visually removed.

(Sixth Embodiment) FIG. 20 shows a sixth embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating a configuration of an analog FIFO memory device according to the embodiment. The sixth embodiment of the present invention is to lower the level of fixed pattern noise relative to the signal level using voltage conversion.

Noise such as fixed pattern noise is particularly noticeable when the intensity of the superimposed signal itself is low. For this reason, when the input signal is small, it is necessary to suppress the fixed pattern noise accordingly. Therefore, when the input signal is small, the level of the input signal is raised in the pre-processing, input to the analog FIFO memory 1, and the signal output from the analog FIFO memory 1 is reduced to the original level. Accordingly, the level of fixed pattern noise generated inside the analog FIFO memory 1 can be reduced.

That is, as shown in FIG.
A nonlinear expansion circuit 80 for performing a nonlinear expansion operation using a logarithmic function or the like is provided on the input side of the IFO memory 1 as an input-side conversion unit, and a nonlinear compression circuit 90 for performing a nonlinear compression operation using an exponential function or the like is provided on the output side. By providing the output side conversion unit, fixed pattern noise generated inside the analog FIFO memory 1 can be compressed. The non-linear expansion operation performed by the non-linear expansion circuit 80 may be any type as long as the output y is larger than the function x = y with respect to the input x. Needs to be a circuit that implements the inverse function of the function of the expansion operation performed by the nonlinear expansion circuit 80.

In the analog FIFO memory device shown in FIG. 20, the level of an input signal is raised by a non-linear expansion circuit 80 in a low level range and input to the analog FIFO memory 1, and the output signal of the analog FIFO memory 1 is Conversely, in the low level region, the nonlinear compression circuit 90
Lower the level by

For example, it is assumed that the level of fixed pattern noise generated inside the analog FIFO memory device 10 is 4 mV. At this time, if the level of the input signal is 5 mV, the influence of the fixed pattern noise on the input signal becomes extremely large. Here, assuming that the voltage gain of the nonlinear expansion circuit 80 for the signal of level 5 mV is four times and the voltage gain of the nonlinear compression circuit 90 for the signal of level 20 mV is １ ／, the input signal is the nonlinear expansion circuit. 80, the level is converted to 20 mV, input to the analog FIFO memory 1, output from the analog FIFO memory 1, and output to the non-linear compression circuit 90 for 5mV.
Is level converted again. At the same time, analog FIF
The fixed pattern noise generated in the O memory 1 is also level-converted to 1 mV by the non-linear compression circuit 90. Therefore, only the fixed pattern noise is level-converted from 4 mV to 1 mV without changing the signal level, and the influence of the fixed pattern noise on the signal can be greatly reduced.

FIG. 21 shows a non-linear expansion circuit 80 shown in FIG.
3A and 3B are diagrams illustrating an example of a circuit configuration of the non-linear compression circuit 90. FIG. 3A illustrates an example of a circuit configuration of the non-linear expansion circuit 80, and FIG.

In the non-linear expansion circuit 80 shown in FIG. 21A, the signal input from the input terminal 81 is
2, the current is converted into a current, and flows into a nonlinear resistor 83 constituted by an NPN transistor. It is well known that if an NPN transistor is diode-connected, the output voltage is logarithmically converted with respect to the current flowing therethrough. Therefore, the output terminal 8 is used as the output of the operational amplifier 84.
5, the input signal is converted according to a logarithmic function and output.

In the non-linear compression circuit 90 shown in FIG. 21 (b), the resistance element 93 and the NPN
The connection relationship with the nonlinear resistor 92 formed of a transistor is reversed. Therefore, when the signal input from the input terminal 91 is converted into a current by the nonlinear resistor 92, the signal is converted exponentially. Since this current flows into the resistance element 93, a voltage in which the input signal is exponentially converted is generated at both ends, and the input signal is converted as an output of the operational amplifier 94 at the output terminal 95 in accordance with the exponential function. Is done.

In this embodiment, the analog FIFO
Not only can fixed pattern noise generated in the memory 1 be compressed, but also all noise other than fixed pattern noise can be compressed. Therefore, the application target of the present embodiment is not limited to the analog FIFO memory, and a nonlinear expansion circuit is provided on the input side for all analog circuits including a sampling circuit such as a switched capacitor circuit.
This can be applied by providing a non-linear compression circuit on the output side.

[0120]

As described above, according to the present invention, the fixed pattern noise generated inside the analog FIFO memory is shifted to the high frequency side, and the fixed pattern noise and the signal band can be separated in frequency. Also, analog FIF
O memory is configured in parallel or analog FIFO
When the memory buses are configured in parallel in the memory, the fixed pattern noise and the signal band can be separated in frequency with a simple circuit configuration.

Further, the influence of fixed pattern noise on signal components can be visually reduced on a TV image. Further, the fixed pattern noise and the signal component can be separated in terms of voltage level.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of fixed pattern noise reduction in an analog FIFO memory device according to the present invention.

FIG. 2 is an analog FIF according to the first embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating a configuration of an O memory device.

FIG. 3 is a diagram showing waveforms of signals and fixed pattern noise in the analog FIFO memory device shown in FIG. 2;
(A) is the input signal S1, (b) is the signal component S2 of the output signal of the analog FIFO memory 1, (c) is the signal component S3 of the output signal of the output multiplier 3, and (d) is the analog signal. Fixed pattern noise N generated in FIFO memory 1
1, (e) is a fixed pattern noise component N2 of the output signal of the output-side multiplier 3.

FIGS. 4A and 4B are analog FIFOs shown in FIG. 2;
FIG. 4 is a diagram illustrating a frequency spectrum of a signal and fixed pattern noise in the memory device.

FIG. 5 is an analog FIF according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of an O memory device.

6 is a timing chart showing the timing of a signal read / write operation of the analog FIFO memory 10 shown in FIG.

7A and 7B are diagrams illustrating an example of addressing of a memory cell in an analog FIFO memory, wherein FIG. 7A illustrates vertical addressing, and FIG. 7B illustrates parallel addressing;

FIG. 8 is an analog FIF according to the first embodiment of the present invention.
FIG. 9 is a diagram showing a modification of the O memory device, and is an analog FIFO.
FIG. 9 is a diagram showing a case where the present embodiment is applied when the number of delay stages of the O memory is variable.

FIG. 9 is a diagram illustrating a configuration example of a circuit used as a signal inversion unit instead of an analog multiplier when an analog FIFO memory handles an analog differential signal.

FIGS. 10A and 10B are diagrams illustrating a case where the chopper operation described in the first embodiment is applied to an analog FIFO memory device having a parallel configuration, where FIG. 10A is a diagram illustrating a schematic configuration, and FIG. 6 is a timing chart showing a correspondence between a memory to be accessed and an operation of a multiplier in the analog FIFO memory device shown in FIG.

FIG. 11 shows an analog FI according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of the FO memory device, in which a chopper operation is realized without using a multiplier for an analog FIFO memory device having a parallel configuration.

FIG. 12 shows an analog FI according to a third embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an FO memory device.

13A and 13B are diagrams for explaining the principle of visually removing the influence of fixed pattern noise by a chopper operation according to the fourth embodiment of the present invention. FIG. 13A illustrates fixed pattern noise without a chopper operation. The waveform (b) is a fixed pattern noise waveform when a chopper operation is performed in the present embodiment.

FIG. 14 shows an analog FI according to a fourth embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of the FO memory device.

15 is a signal waveform diagram showing a relationship between a vertical synchronization signal SH of a TV image and first and second control signals Sa and Sb in the analog FIFO memory device shown in FIG.

FIGS. 16A and 16B are diagrams showing the correspondence between pixels of a TV image and addresses of an analog FIFO memory.

FIG. 17 shows an analog FI according to a fourth embodiment of the present invention.
It is a figure which shows the modification of an FO memory device, and is a figure which shows what was comprised so that the chopper operation which concerns on this embodiment may be performed independently.

FIG. 18 shows an analog FI according to a fifth embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an FO memory device.

19 is a timing chart showing an operation of the analog FIFO memory device shown in FIG.

FIG. 20 is an analog FI according to a sixth embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating a configuration of an FO memory device.

FIG. 21 is a diagram showing an example of a circuit configuration of a nonlinear compression circuit and a nonlinear expansion circuit in the analog FIFO memory device according to the sixth embodiment of the present invention shown in FIG. 20,
(A) is a circuit configuration example of a non-linear compression circuit, and (b) is a circuit configuration example of a non-linear expansion circuit.

FIG. 22 is a diagram showing a basic configuration of an analog FIFO memory.

FIGS. 23A and 23B are diagrams for explaining the reason why fixed pattern noise appears in an analog FIFO memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Analog FIFO memory 11 Memory cell (storage element) 20 Input side conversion part 21 1st analog multiplier (input side signal inversion means) 22 1st frequency divider 25 Output side conversion part 26 2nd analog multiplier ( Output-side signal inversion means) 27 Second frequency divider 29 Signal inversion means 41a First analog FIFO memory 41b Second analog FIFO memory 43 Input-side signal inversion means 44 Output-side signal inversion means 50 Analog FIFO memory 51 Memory bus 52 Input-side multiplexer 53 Output-side multiplexer 60 Input-side converter 65 Output-side converter 70 Reset means 80 Nonlinear expansion circuit (Input-side converter) 90 Nonlinear compression circuit (Output-side converter) 101 Analog FIFO memory 102 Input-side converter 103 Output side conversion unit

Claims (12)

[Claims] An analog FIFO memory having a plurality of storage elements for storing analog signals, delaying an input analog signal by a predetermined time and outputting the signals in the order of input, and an analog FIFO memory for an output signal of the analog FIFO memory. An output-side conversion unit that performs conversion for reducing the influence of fixed pattern noise generated inside the memory on the signal component; and an input that performs conversion reverse to the conversion of the output-side conversion unit on the input signal of the analog FIFO memory. An analog FIFO memory device comprising a side conversion unit. 2. The analog FIFO memory device according to claim 1, wherein the output-side conversion unit performs frequency modulation such that the frequency of the fixed pattern noise transits to a higher frequency side than a signal band. Analog FIFO memory device. 3. The analog FIFO memory device according to claim 2, wherein the input-side conversion unit is configured to synchronize the analog FIFO memory with a signal input / output timing of the analog FIFO memory.
The output side conversion unit performs the normal rotation operation and the inversion operation alternately with respect to the input signal of the memory, and the output-side conversion unit synchronizes with the signal input / output timing of the analog FIFO memory.
An analog FIFO memory device wherein a normal rotation operation and a reverse operation are alternately performed on an output signal of a memory. 4. The analog FIFO memory device according to claim 3, wherein the input-side conversion unit includes: a first frequency divider that divides a frequency of a clock signal for driving the analog FIFO memory; and an input of the analog FIFO memory. Input side signal inverting means for performing a normal operation when the logical level of the output signal of the first frequency divider is one logical level, and performing an inverting operation when the logical level of the output signal is another logical level A second frequency divider for dividing a clock signal for driving the analog FIFO memory, and a second frequency divider for the output signal of the analog FIFO memory. Output side signal inverting means for performing a normal operation when the logical level of the output signal of the device is one logical level, and performing an inverting operation when the logical level is another logical level. An analog FIFO memory device. 5. The analog FIFO memory device according to claim 3, wherein the analog FIFO memory has a variable number of delay stages, which is the number of signals to be held, and the analog FIFO memory device has an output-side conversion unit. Output signal of the analog FIFO
An analog FIFO comprising signal inverting means for inverting when the number of delay stages of the memory is one of an even number and an odd number, but not inverting when the number is the other.
O memory device. 6. The analog FIFO memory device according to claim 3, further comprising an even number of said analog FIFO memories, wherein each of said analog FIFO memories operates in parallel and access is sequentially performed in a cyclic manner. The input-side conversion unit is configured by providing input-side signal inversion means for inverting a signal at every other access order on the input side of the even-numbered analog FIFO memories, The analog FIFO memory device is characterized in that the unit is provided with output side signal inverting means for inverting a signal every other access order on the output side of the even number of analog FIFO memories. . 7. The analog FIFO memory device according to claim 3, wherein said analog FIFO memory comprises: an even number of memory buses each connected to a plurality of storage elements for storing analog differential signals; An input-side multiplexer that sequentially and cyclically inputs a differential signal to each memory bus; and an output-side multiplexer that sequentially and cyclically outputs an analog differential signal from each memory bus. Is configured such that the even number of memory buses are connected to the input side multiplexer so that an analog differential signal is inverted and input every other one in the signal input order. The output-side multiplexer is arranged such that the even-numbered memory buses are alternately output in the signal output order and the analog differential signal is inverted and output. Analog FI characterized by being constituted by being connected
FO memory device. 8. The analog FIFO memory device according to claim 1, wherein the analog FIFO memory device is used for delaying a TV signal, and the output-side conversion unit detects fixed pattern noise in a TV image. An analog FIFO memory device, which performs frequency modulation so as to be eliminated. 9. The analog FIFO memory device according to claim 8, wherein the input-side conversion unit synchronizes with an input signal of the analog FIFO memory in synchronization with a TV image update timing.
A normal rotation operation and a reverse operation are alternately performed, and the output-side conversion unit synchronizes with the update timing of the TV image to output signals of the analog FIFO memory.
An analog FIFO memory device wherein a normal rotation operation and a reverse operation are alternately performed. 10. The analog FIFO memory device according to claim 1, wherein the output-side conversion unit performs voltage conversion so that the level of the fixed pattern noise is compressed with respect to the signal level. Analog FIFO memory device. 11. The analog FIFO memory device according to claim 10, wherein the input-side conversion section performs voltage conversion on an input signal of the analog FIFO memory according to a logarithmic function, and the output-side conversion section. An analog FIFO memory for performing voltage conversion on an output signal of the analog FIFO memory in accordance with an exponential function which is an inverse function of a logarithmic function used in the voltage conversion in the input side conversion unit. Memory device. 12. An analog FIFO memory device used for delaying a TV signal, comprising: a plurality of storage elements for storing analog signals; and a counter for sequentially specifying storage elements for inputting and outputting signals. An analog FIFO memory for delaying an analog signal by a predetermined time and outputting in the order of input; a storage element of the analog FIFO memory and a TV image so that a fixed pattern noise generated inside the analog FIFO memory in a TV image is visually removed. Reset means for resetting the counter of the analog FIFO memory at a different timing each time the TV image is updated based on a TV vertical synchronization signal so as to change the correspondence with the upper position every time the TV image is updated. FIFO memory device.