JPH11312140A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a bus system for an information processor, capable of maximizing the application efficiency of three buses, i.e., a system bus, a memory bus and a processor bus. SOLUTION: A processor bus1 711 connected to a processor1 701, a processor bus2 712 connected to a processor 2 702, a memory bus 112 connected to a main memory 104, and a system bus 11 connected to a connection device 105 are connected to a four-cross connection controller 705. The controller 705 controls the mutual data transfer among the processor bus1 711, the processor bus2 712, the memory bus 112, and the system bus 113.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system used for an information processing device such as a workstation, a personal computer, and a word processor.

[0002]

2. Description of the Related Art Conventionally, a bus system in an information processing apparatus is
Bite, Vol. 14, No. 12, (1989), 417-4
24 pages, (BYTE, Volume 14, Number 12
(1989), p. 417-424). Brett
A configuration in which the memory bus and the system bus are individually connected to the processor bus, or the processor bus and the memory bus are individually connected to the system bus, as in the bus system described in Glass, "INSIDEEISA". Had become.

[0003]

The former is a so-called direct memory access (hereinafter referred to as DMA) in which a system bus and a memory bus operate in conjunction with each other.
In this case, since the processor bus cannot operate independently, the use efficiency of the processor bus deteriorates. On the other hand, the latter has a problem that the system bus cannot operate independently at the time of so-called main memory access in which the processor bus and the memory bus operate in conjunction with each other.

[0004] The configuration and problems of these conventional bus systems will be described later in detail with reference to the drawings.

An object of the present invention is to provide a bus system of an information processing apparatus which maximizes the use efficiency of each bus.

Another object of the present invention is to provide a bus system capable of simultaneously performing an interlocking operation of a processor bus and a memory bus and an independent operation of a system bus.

A further object of the present invention is to provide a bus system capable of simultaneously performing an interlocking operation of a system bus and a memory bus and an independent operation of a processor bus.

Still another object of the present invention is to provide a bus system for an information processing device which maximizes the use efficiency of each bus when at least four or more of a system bus, a memory bus, and a processor bus are interconnected. Is to do.

[0009]

In order to achieve the above object, according to the present invention, four buses of a first processor bus, a second processor bus, a memory bus, and a system bus are connected at least in a four-way configuration. In addition, while any two of the four buses operate in conjunction with each other, the other buses can operate independently.

That is, in the present invention, a first processor, a second processor, a main memory, an input / output device, a first processor bus connected to the first processor, An information processing apparatus having a second processor bus connected to a processor, a memory bus connected to the main memory, and a system bus connected to the input / output device, wherein the first processor bus and the second Processor bus, the memory bus, and the system bus are connected, and the first processor, the second
Processor, connection means for transferring data between any two of the main memory and the input / output device, the connection means using the connected first processor bus and the memory bus, A first data transfer mode for transferring a first data signal between the first processor and the main memory, and the main memory and the input / output device using the connected memory bus and the system bus A third data transfer mode for transferring a second data signal between the I / O device and the second input / output device using the connected system bus and the second processor bus.
Transfer the third data signal to and from the fourth processor
And a first data transfer mode for transferring a first data signal between the second processor and the first processor using the connected second processor bus and the first processor bus. An information processing apparatus that executes any one of the data transfer modes.

The present invention also provides a first device, a second device, a third device, a fourth device, and the first device.
An information processing apparatus having a first bus connected to a device, a second bus connected to the second device, a third bus connected to the third device, and a fourth bus connected to the fourth device. The first bus, the second bus, the third bus, and the fourth bus are connected, and the first device, the second device, the third device, and the fourth bus are connected using these buses. A connection device that enables data transfer between any two of the devices, the connection device comprising:
A first data transfer mode for transferring a first data signal between the first device and the second device using the first bus and the second bus connected to the second bus; A second data transfer mode for transferring a second data signal between the second device and the third device by using a bus and the third bus, and connecting the third bus and the fourth bus to each other. A third data transfer mode for transferring a third data signal between the main memory and the input / output device using the fourth bus and the first bus, And a fourth data transfer mode for transferring a fourth data signal between the first device and the first device.

As a result, the use efficiency of the four buses can be maximized.

In order to achieve the above object, according to the present invention, at least three types of buses, namely, a processor bus, a memory bus, and a system bus, are connected in a three-way configuration, and any two of the three types of buses are connected. During the interlocking operation, another type of bus can operate independently.

That is, in the present invention, a connection device such as a processor bus to which at least one processor is connected, a memory bus to be connected to a main memory, and at least one input / output device (hereinafter, I / O device) is connected. Control means for connecting at least three-way connection of the three types of system buses, and the control means enables interconnection of various buses.

That is, in the present invention, a bus system of an information processing apparatus is a system in which a processor bus to which at least one processor is connected, a memory bus to be connected to a main memory, and at least one connection device are connected. A bus and these three types of buses are connected, and are constituted by connection control means for interconnecting these three types of buses.

In the present invention, the connection control means includes a data path switching means for connecting the data buses of the three types of buses to each other and transferring data on these buses to each other, and a control bus for each of the three types of buses. An address bus is connected to transfer a control signal and an address on these buses to each other and to generate a data path control signal to a data path switching means.
It consists of a memory connection controller.

Preferably, the data path switching means and the bus / memory connection controller are individually or integrally formed on one integrated circuit.

Further, according to the present invention, the connection control means is similarly formed even when the three types of buses are not one but each of the three types of buses is a plurality, so that these buses can be interconnected. It can be.

In the configuration of the present invention described above, the three types of buses of the processor bus, the memory bus, and the system bus are connected to each other in at least a three-forked manner, so that, for example, a processor on the processor bus is connected to a main memory on the memory bus. In the case of a processor main memory access for accessing a memory, data is transferred only through the processor bus and the memory bus, and does not pass through the system bus. Therefore, the system bus can operate independently. On the other hand, in the case of DMA in which a connected device on the system bus accesses the main memory on the memory bus, data is transferred only through the system bus and the memory bus and does not pass through the processor bus, so that the processor bus operates independently. It is possible to do.

Thus, the use efficiency of the three types of buses can be maximized.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIGS. 2 and 3 show the configuration of the bus system in the prior art, which will be described in detail here for comparison with the present invention.

In FIGS. 1, 2 and 3, 1 is used in common.
01 is an N (N is an integer) processor, 102 is a cache memory system (cache), 104 is a main memory (main memory), and 105 is an M (M is an integer) system bus connection device. As the system bus connection device 105, a disk / file controller,
A so-called input / output (I / O) device such as a drawing / display system controller or a network / communication system controller is shown. 111 is a processor bus, 112 is a memory bus, 1
13 is a system bus. And 10 in FIG.
Reference numeral 3 denotes a three-way connection controller, and 201 and 301 in FIGS.
02 is a memory connection controller.

In the conventional bus system shown in FIGS. 2 and 3, the system bus 113 and the memory bus 11 are shown in FIG.
2 are independently connected to the processor bus 111 by a bus connection controller 201 and a memory connection controller 202, respectively. On the other hand, in FIG. 3, the processor bus 111 and the memory bus 112 are independently connected to the system bus 113 by the bus connection controller 301 and the memory connection controller 302, respectively.

In the configuration of FIG. 2, the system bus 11
In the DMA operation for transferring data between the third connection device 105 and the main memory on the memory bus 112,
Via the processor bus 111. Therefore, independent operations of the processor bus 111 such as data transfer between the processor 101 and the cache 102 or between the plurality of processors 101 cannot be performed simultaneously with the DMA operation. On the other hand, in the configuration of FIG. 3, data transfer is performed between the processor 101 and the main memory 104, that is, in a so-called processor main memory access, the data passes through the system bus 113. System bus 1 for data transfer between 105
13 independent operations cannot be performed simultaneously with processor main memory access.

On the other hand, in the bus system of FIG. 1 according to the first embodiment of the present invention, three types of buses, ie, a processor bus 111, a memory bus 112, and a system bus 113,
A three-way connection controller 103 has a three-way connection. Therefore, in the case of the DMA operation, since the signal does not pass through the processor bus 111, the processor bus 1
Eleven independent operations can be performed simultaneously with the DMA operation. Also, in the case of the processor main memory access, since the access does not pass through the system bus 113,
3 independent operations can be performed simultaneously with the processor main memory access. As a result, the use efficiency of the three types of buses can be maximized even in the case of DMA and processor main memory access.

Hereinafter, an example of performance evaluation of the bus system of the first embodiment of the present invention shown in FIG. 1 and the conventional bus system shown in FIGS. 2 and 3 will be described, and the first embodiment of the present invention will be described. The effect of is described quantitatively.

In the bus systems shown in FIGS. 1, 2 and 3, the maximum data throughput of the processor bus 111 is 400 megabytes / second, the maximum data throughput of the memory bus 112 is 400 megabytes / second, and the system bus 1
13 is assumed to have a maximum data throughput of 200 megabytes / second. The ratio of main memory access on the processor bus 111 is 40%, the ratio of DMA on the system bus 113 is 70%, the bus connection controller 201
, And the maximum bus acquisition ratio of 301 is 50%. The performance evaluation of each bus system when both the processor bus 111 and the system bus 113 try to operate at the maximum data throughput under the above conditions is as follows.

First, in the conventional bus system shown in FIG. 2, if the system bus 113 operates at the maximum throughput of 200 megabytes / second, it is 140% which is 70% of the maximum throughput.
A request for a megabyte / second DMA is sent to the bus connection controller 201. Since the bus connection controller 201 can acquire the bus up to 200 MB / sec which is 50% of 400 MB / sec for the processor bus 111, the bus connection controller 201 acquires all DMA requests of 140 MB / sec. As a result, the system bus 113 can operate at 200 MB / s, while the processor bus 111 operates at D
Due to MA requirements, substantially (400-140) = 260
It can only operate at megabytes per second. At this time, the processor main memory access is 104 MB / sec, which is 40% of 260 MB / sec. Therefore, the request for the memory bus 112 is (140 + 104) = 254.
Megabytes / second, and the memory bus 112 can respond to this request. Summarizing the above, the usage efficiency of the three types of buses in the conventional bus system of FIG.
2 = 254/400 = 63.5%, system bus 113
Is 200/200 = 100%.

Next, in the conventional bus system shown in FIG. 3, when the processor bus 111 attempts to operate at the maximum throughput of 400 Mbytes / sec, the main memory access request of 160% of the megabyte / sec, which is 40% of that, is sent to the bus connection controller 301. Sent to Bus connection controller 3
01 can acquire the bus only up to 100 MB / sec which is 50% of 200 MB / sec for the system bus 113. Thus, the processor main memory access is processed only at 100 MB / s, so that the processor bus 111 has 40 MB at 40%.
It can only operate at 250 MB / s. At this time, the system bus 113 is substantially (200-
100) = 100 megabytes / second. Therefore,
DMA requests are 70% of 100 megabytes / second70
Megabytes / second. As a result, the request to the memory bus 112 is (100 + 70) = 170 megabytes / second, and the memory bus 112 can respond to this request. In summary, the use efficiency of the three types of buses in the conventional bus system of FIG.
400 = 62.5%, memory bus 112 is 170/40
0 = 42.5%, system bus 113 is 100/200
= 50%.

On the other hand, in the bus system of FIG. 1 according to the first embodiment of the present invention, the processor bus 111
Tries to run at 400 MB / s,
0% of the 160 MB / s main memory access request is sent to the three-way controller 103. or,
When the system bus 113 attempts to operate at 200 megabytes / second, 70% of the 140 megabyte DMA requests are sent to the three-way controller 103, respectively. The three-way connection controller 103 combines the processor main memory access request and the DMA request (160
+140) = 300 megabytes / second is sent to the memory bus 112, which can serve this request. Thus, the processor bus 111 can operate at 400 megabytes / second and the system bus 113 can operate at 200 megabytes / second. As described above, the use efficiency of the three types of buses in the bus system according to the first embodiment of the present invention shown in FIG.
%, The memory bus 112 is 300/400 = 75%, and the system bus 113 is 200/200 = 100%.

The above results are shown in Table 1. As is apparent from Table 1, it can be understood that the bus system of FIG. 1 according to the present invention maximizes the use efficiency of the three types of buses.

[0032]

[Table 1]

Prior to the embodiment showing the specific configuration of the present invention, a bus system according to the second and third embodiments of the present invention will be described with reference to FIGS.

7 and 8, reference numerals 701 and 703 denote single-configuration processors 1 to N to which individual cache memory systems (Caches) can be connected, and 801 denote N multi-configuration processors to which individual cache memory systems can be connected. It is. 711 and 712 are individually configured processors 701 and 703 and the four-way controller 7 respectively.
Reference numeral 705 denotes a processor bus connecting the processor buses 711 and 712, the memory bus 112, and the system bus 113. or,
702, 704 and 802 are processors 701,
This is a cache memory system individually connected to 703 and 801. The system bus connection device 10
Reference numeral 5 denotes an I / O device similar to that of the previous embodiment.

In the second embodiment of the present invention shown in FIG. 7, four buses of three types, ie, two processor buses 711 and 712, a memory bus 112 and a system bus 113, are connected by a four-way connection controller 705 to four buses. They are connected in a crossroad. Processors 701 and 703 are independently configured processors to which separate cache memory systems 702 and 704 can be connected. Therefore, the processor 70
1 and 703 can directly access the respective individual cache memories 702 and 704 without passing through the processor bus, but cannot share the processor bus.

In FIG. 7, the four-way connection controller 7
05 controls connection of three types of four buses,
The communication between the processors 701 and 703 can be performed in parallel with the DMA, or the main memory access by the processor 701 and the system bus access by the processor 703 can be performed in parallel.

Thus, in this embodiment, as in the previous embodiment, the use efficiency of three types and four buses can be maximized.

FIG. 8 is similar to the first embodiment shown in FIG.
The three buses of the processor bus 111, the memory bus 112, and the system bus 113 are connected to the three-way connection controller 1.
03, it is connected on a three-way. The processor 801 has a separate cache memory system (cach
This is a multi-configuration processor to which e) can be connected. Therefore, each of the processors 801 can access the individual cache memory 802 without passing through the processor bus,
Further, the processor bus 111 can be shared. Further, in the bus system according to the third embodiment of the present invention shown in FIG.
As in FIG. 1, it is possible to perform operations such as performing the DMA and the independent operation of the processor bus 111 in parallel, or performing the main memory access from the processor bus 111 and the operation of the system bus 113 in parallel. As in the first embodiment, the use efficiency of three types of three buses can be maximized.

Next, a specific embodiment of the main part of the above embodiment of the present invention will be described in detail with reference to FIGS. 4, 5 and 6. FIG. In particular, the detailed configuration of the three-way connection controller 103 of the first and third embodiments shown in FIGS. 1 and 7 will be described. However, the four-way connection controller 705 shown in FIG. 7 can be similarly configured.

FIG. 4 shows a three-way connection controller 10.
3 shows a configuration diagram of two integrated circuits. In FIG. 4, a three-way connection controller 103 includes a processor bus 111, a memory bus 112, and a system bus 113.
Is connected. These buses are address buses 411, 414, 417, control buses 412, 415, respectively.
418, and data buses 413, 416, and 419. In the present embodiment, the three-way connection controller 103 includes two integrated circuits, that is, a bus-memory connection controller 401 and a data path switch 402. However, the three-way connection controller 103
It can also be constituted by one or three or more integrated circuits.

The data path switch 402 connects three types of data buses of a processor data bus 413, a memory data bus 416, and a system data bus 419 in a three-junction manner. Then, according to the data path control signal 420 output from the bus / memory connection controller 401, connection and disconnection of the three types of data buses 413, 416, and 419 are performed.
And control the data input / output direction. On the other hand, the bus / memory connection controller 401 is connected to a processor address bus 411, a processor control bus 412, a system address bus 417, and a system control bus 418. Then, the statuses of the processor bus 111 and the system bus 113 are monitored. Also, it outputs a memory address bus 414, a memory control bus 415, and a data path control signal 412 to output the main memory 104 and the data path switch 40.
2 is controlled. The data path control signal 412 will be described later in detail.

The bus / memory connection controller 401 comprises:
When a processor main memory access is requested from the processor bus 111, the processor bus 111 and the memory bus 112 are operated in conjunction, and the system bus 113 is operated independently. Further, when a DMA is requested from the system bus 113, the system bus 113 and the memory bus 11
2 are operated in conjunction with each other to operate the processor bus 111 independently. Also, the processor bus 111 is connected to the system bus 1
When there is an access request to the system bus 113 or an access request from the system bus 113 to the processor bus 111, the processor bus 111 and the system bus 113 are operated in conjunction. Further, when a request from the processor bus 111 and a request from the system bus 113 conflict with each other, for example, when a memory access request is issued from both at the same time, a wait operation is performed on one of the buses. Arbitration control function.

FIG. 5 shows the data path switch 40 in FIG.
FIG. 2 is a diagram showing an internal configuration of one embodiment of FIG. In FIG. 5, reference numerals 507, 508, and 509 denote data input / output drivers connected to the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively.
02, 503 are data latch circuits (Latch), 504,
505 and 506 are data selectors (Selectors). The decoder circuit 510 decodes the data path control signal 420 output from the bus / memory connection controller 401 and outputs enable signals (Enable) 511, 512, 513 of the input / output buffers 507, 508, 509.
Then, select signals (Select) 514, 515, 516 of the data selectors 504, 505, 506 are generated.

The data latches 501, 502 and 503 have a processor data bus 413 and a memory data bus 4 respectively.
16. Input data from the system data bus 419 is latched. The selectors 504, 505, and 506 each include a processor data bus 413, a memory data bus 416,
The output data to the system data bus 419 is selected from the input data from the other two types of data buses. As a result, it is possible to control input data from any one of the three data buses to be output to both of the other two data buses, or to output data only to one of the data buses and not to the other. It can be carried out. Therefore, the data path control signal 420 allows the interlocking operation of all three data buses,
Alternatively, any two of the three interlocking operations and the other one of the independent operations can be performed.

FIG. 6 is a diagram showing an embodiment of the internal configuration of the bus / memory connection controller 401 in FIG. In FIG. 6, reference numerals 601, 602, 603, and 604 denote input / output drivers, and reference numerals 605, 606, 607, and 608 denote latch circuits (Latch). Further, 609 and 610 are decoder circuits, 611 and 612 are encoder circuits, 613 is a sequencer which is a logical operation unit, and 614 is a decoder circuit.
615 is a selector, 616 is a memory control signal generator, and 617 is a data path control signal generator.

Input signals from the processor address bus 411, the processor control bus 412, the system address bus 417, and the system control bus 418 are sent to the latch circuits 605, 607, and 606 via input / output drivers 601, 602, 603, and 604, respectively. , 608.
Input from two types of address buses, a latch circuit 605,
The addresses latched in the 606 are the decoder circuits 6 respectively.
09 and 610 are decoded. The decoding result is 2
In addition to the data of the latch circuits 607 and 608 which are the signal inputs from the control buses 412 and 418, the processor bus 1 is controlled by the encoder circuits 611 and 612, respectively.
11 and a signal indicating the state of the system bus 113. As a result, the bus / memory connection controller 401 communicates with the processor bus 111 and the system bus 11
3 can be monitored.

The processor bus 111 and the system bus 1 encoded by the encoder circuits 611 and 612
13 is a sequencer 613 which is a logical operation unit.
Is input to The sequencer 613 includes two types of buses 11
From the status signals 1 and 113, the correspondence to each bus and the operation of the memory bus 112 are calculated and output as code information. The sequencer 613 includes a general-purpose microprocessor and a dedicated hardware configuration.

The code information output from the sequencer 613 is decoded by the decoder circuit 614, and the output enable signals 618, 619, 620, 621 of the input / output drivers 601, 602, 603, 604, the select signal 622 of the selector circuit 615, the memory Control signal generator 6
16, a memory control code 623 and a data path control code 624 to the data path control signal generation unit 617, and a control output signal 625 to the processor control bus 412 and the system control bus 418 via the input / output drivers 602 and 604, respectively. 626.

The input / output driver 601 is connected to the system bus 1
When the access to the processor bus 111 occurs from 13, the input / output address from the system address bus 417 is output to the processor address bus 411. Also, the input / output driver 602 connects to the processor control bus 412 with
It outputs a control output signal 625 defined by the specifications of the processor bus 111. On the other hand, the input / output driver 603 outputs an input / output address from the processor address bus 411 to the system address bus 417 when an access from the processor bus 111 to the system bus 113 occurs. Further, the input / output driver 604 outputs a control output signal 626 defined by the specification of the system bus 113 to the system control bus 418.

When an address is input from the processor address bus 411 and the system address bus 417 and an access to the memory bus 112 occurs, the selector circuit 615 selects one of the addresses to select the memory address bus 4.
14 is output. The memory control signal generation unit 616 functions as a code conversion circuit, converts the memory control code 623 output from the decoder circuit 614 into a memory control signal defined by the specification of the memory bus 112, and
15 is output. The data path control signal generation unit 617 also functions as a code conversion circuit, and converts the data path control code 624 output from the decoder circuit 614 into a data path control signal 420 for the data path switch 402 and outputs it.

The three-way connection controller 10 described in detail above
The bus / memory connection controller 401 in 3 can control connection, disconnection, weight, and the like of three types of buses.

Next, an embodiment of various data and signals in the above-described three-way connection controller 103 will be described in detail with reference to FIGS.

FIG. 9 shows a data path control signal 420 output from the bus / memory connection controller 401 to the data path switch 402 and the decoder 51 corresponding thereto.
I / O drivers 507, 508, 5 decoded with 0
09, enable signal 511, 512, 513, select signal 51 of data selectors 504, 505, 506
4 shows an example of the relationship with 4, 515, and 516. In the figure, the columns of master (master), slave (Slave), and read / write (Lead / Wrete) at the top are data transfer master / slave, and the data transfer is read / write from master to slave. It means transfer. The remaining signal at the top is the signal 5 shown in FIG.
The signal names corresponding to 11 to 516 are described. DT-CNT in the rightmost column at the top is the data path control signal 420. This data path control signal (DT-CNT) 420 is represented by 3 bits in this embodiment. In the idle state (Idel) where no transfer is performed, the DT-CNT 420 is 0 (“000”).

Each enable signal (DIR-P,
DIR-M, DIR-S) 511, 512, 513 are
It is "0" when each of the input / output drivers 507, 508, and 509 is an input, and is "1" when each is an output. The select signal (SEL-P) 514 is “0” when the selector 504 selects the memory bus 112 side,
It is "1" when selecting the side. Also, the select signal (S
EL-M) 515 is “0” when the selector 505 selects the processor bus 111 side, and “1” when the selector 505 selects the system bus 113 side. Further, the select signal (S
EL-S) 516 is “0” when the selector 506 selects the processor bus 111 side, and “1” when the selector 506 selects the memory bus 112 side. According to this figure, DT-CN input to the decoder 510 of the data path switch 402
By T420, the control of the selectors 504 to 506 and the input / output drivers 507 to 509 in the data path switch 402 can be executed, respectively, and the connection direction of the three types of buses can be controlled.

Next, the operation of the three-way connection controller 103 according to the present invention will be described with reference to FIG.
FIG. 19 is a detailed block diagram of the bus connected to FIG.
This will be described with reference to the timing chart of FIG.

In these figures, the same reference numerals as those in FIGS. 1 and 4 denote the same items. Reference numerals 1910 and 1911 denote DMA master I / O devices and slave I / O devices corresponding to the system bus connection device 105, respectively. In FIG. 19, an acknowledgment signal (ACK) 19
Reference numeral 02 denotes a response signal to the processor 101, which indicates that the data has been determined at the time of reading, and that the data has been captured at the time of writing.

Row address strobe signal (RAS) 1
903, column address strobe signal (CAS) 19
04, a write enable signal (WE) 1905 is a part of the memory control signal sent to the memory control bus 415 of the main memory 104, respectively. The address selection signal (AD-MPX) is an internal signal of the bus / memory connection controller 401, and outputs a row address when the signal is high and a column address when the signal is low. System bus ground signal (S-GNT) 1906
Is a system bus connection device 105, which gives permission to use the system bus 113 to an I / O device 1910 that can be a DMA master, thereby enabling the device to become a DMA master. The address / data strobe signal (S-STB) 1907 is output from the system bus master.
The output is from the device 1910, the output is from the bus / memory connection controller 401 at the time of processor I / O access, and the address is output at the time of reading and the address and data are both output at the time of writing. A system bus slave response signal (S-ACK) 1908 is a response signal of the system bus slave, which is output by the bus / memory connection controller 401 at the time of DMA access, and is output by the slave I at the time of processor system bus I / O access.
The / O device 1911 outputs. At the time of reading, data is determined, and at the time of writing, data is taken in. S-GN
T1906, S-STB1907, S-ACK190
8 and a signal indicating read / write distinction (S-REA
D) 1909 belongs to the control output signal 626 sent to the system control bus 418. System bus address (S
-ADD) is sent to the system address bus 417.
The system bus read / write signal (S-REA)
D) indicates a read when high (H).

FIG. 16 shows a bus memory connection controller 40.
FIG. 7 is a diagram illustrating an example of a state transition of one sequencer 613. FIGS. 10 to 15 are diagrams showing signals output in a plurality of steps of each state transition of each transfer type shown in FIG. 16, respectively, a processor main memory read, a processor main memory write, and a processor system bus device. Read, processor system bus device write, DMA read, and DMA write.
"O" indicates signal assertion, and S-READ190
“H” and “L” of 9 mean that the signal values are output as high and low, respectively. A bar described above a signal name means that the signal has negative logic.

In FIG. 16, in step S2 of the processor system bus device read corresponding to FIG. 12, the system bus slave waits for data determination. In step S3 of the processor system bus device write corresponding to FIG. 13, a write response wait is performed. In step S1 of the DMA read corresponding to FIG. 14, S-STB reception wait is performed, and the transition destination to the next step S2 is determined according to the read / write determination when receiving the S-STB. Also, in step S8 of the DMA read,
In S5 of the DMA write, the DMA master S-STB waits for negation.

In the time charts of FIGS. 17 and 18, which are transfer time charts defined by FIGS. 9 to 16, those shown in parentheses are the output sources of the respective signals.

That is, (BMCC) indicates that the bus memory connection controller 401 outputs, and (I / O) indicates the DMA I / O device 1910 or the slave I which has become the slave of the processor system bus I / O access. / O device 1911 is shown.

Now, the data path switch 40 shown in FIG.
The two latch circuits 501, 502, and 503 are configured by edge trigger flip-flops and are latched at the rising edge of the clock (CLK) shown in FIGS. A start signal (START) 1901 is a transfer start signal output from the processor 1, and is used by latching an address at the rising edge of the clock (CLK) from which the signal is output. Otherwise, M-ADD indicates a memory address sent to memory address bus 414. Also, P-Dat
a, M-data, and S-data indicate data sent to the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively. Furthermore, P-Latc
h, M-Latch, and S-Latch are latches 501, respectively.
Reference numerals 502 and 503 show the latched data.

In step S3 of the processor system bus device write shown in FIG. 13, one cycle of a wait due to the S-ACK assertion wait is included. Also, FIG.
In step S2 of the processor system bus device read indicated by 2, the wait has entered two cycles due to the S-ACK assertion wait. Then, the DM shown in FIG.
It is apparent from FIG. 16 that the wait due to the S-STB assertion wait is one cycle in step S1 of the A read, and the wait due to the S-STB negation wait is one cycle in step S3.

In FIG. 18, at step S1 of the DMA write, the wait due to the S-STB assertion wait is also 1
Although a cycle has been entered, the negation wait in step S5 is executed with no wait.

The bus memory connection controller 401 and the data path switch 402 shown in FIGS. 4, 5, and 6 are operated by the method shown in FIGS. The operation of one embodiment of the three-way controller 103 has been understood.

The four-way connection controller 70 shown in FIG.
Although the configuration and operation of 5 and the like are not described in detail here,
It can be easily understood from the configuration and operation of the three-way connection controller described above.

Further, in the above description of FIG.
Although the processor bus 111, the memory bus 112, and the system bus 113 are all address / data separated type buses, it goes without saying that the present invention can be applied to an address / data multiplex type bus. For example, when the processor bus 111 and the system bus 113 are address / data multiplexed buses, in FIG. 4, one processor address bus 411 and one processor data bus 413, and one system address bus 417 and one system data bus 419 are provided. And is connected to both the bus / memory connection controller 401 and the data path switch 402. In addition, it is obvious that various modifications can be made under the basic concept of the present invention regardless of the above-described embodiment.

[0068]

According to the present invention described in detail above, while any two of the at least three buses of the processor bus, the memory bus, and the system bus are operating in conjunction with each other, the other buses can be used. Since more than one bus can operate independently, there is an effect that the use efficiency of each bus is maximized.
In particular, when a plurality of processors are connected on a processor bus, or when a cache memory system is connected, the DMA operation and data transfer between the plurality of processors or between the processor and the cache memory system can be performed simultaneously, In addition, there is an effect that a processor main memory access and data transfer between a plurality of system bus connected devices can be performed simultaneously.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of a bus system of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional bus system.

FIG. 3 is another schematic configuration diagram of a conventional bus system.

FIG. 4 is a schematic configuration diagram showing one embodiment of a three-way connection controller 103 according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing an embodiment of the data path switch 402 in the embodiment of the three-way connection controller 103 according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing one embodiment of a bus memory connection controller 401 in one embodiment of the three-way connection controller 103 in the first embodiment of the present invention.

FIG. 7 is a schematic configuration diagram showing a second embodiment of the bus system of the present invention.

FIG. 8 is a schematic configuration diagram showing a third embodiment of the bus system of the present invention.

FIG. 9 shows the data path switch 40 of the present invention shown in FIG.
FIG. 4 is a diagram showing a correspondence between a data path control signal 420 decoded by a decoder 510 in FIG.

FIG. 10 is a diagram showing a relationship between a data path control signal 420 and various signals in each step of a state transition in the case of a processor main memory read in the embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between a data path control signal 420 and various signals in each state transition step in the case of a processor main memory write in the embodiment of the present invention.

FIG. 12 is a diagram showing a relationship between a data path control signal 420 and various signals in each step of a state transition in the case of a processor system bus device read in the embodiment of the present invention.

FIG. 13 is a diagram showing a relationship between a data path control signal 420 and various signals in each state transition step in the case of a processor system bus device write in the embodiment of the present invention.

FIG. 14 shows a data path control signal 4 in each state transition step in the case of a DMA read in the embodiment of the present invention.
The figure which shows the relationship between 20 and various signals.

FIG. 15 shows a data path control signal 4 in each state transition step in the case of a DMA write in the embodiment of the present invention.
The figure which shows the relationship between 20 and various signals.

16 is a bus / memory connection controller 4 shown in FIG.
FIG. 9 is a transition diagram showing an embodiment of a state transition of the sequencer 601 in 01.

FIG. 17 is a time chart showing an example of data transfer defined by FIGS. 9 to 16;

FIG. 18 is another time chart illustrating an example of data transfer defined by FIGS. 9 to 16;

FIG. 19 shows the three-way connection controller 103 and each bus 11 in FIG. 4 showing signals appearing in FIG. 17 and FIG.
FIG. 2 is a configuration diagram specifically showing connections with 1, 112, and 113.

[Explanation of symbols]

 101: N processors, 102: Cache memory system, 103: Three-way connection controller, 104: Main memory, 105: M system bus connection devices, 111: Processor bus, 112: Memory bus, 113: System bus.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Koichi Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Jin Kawaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Address Co., Ltd.Microelectronics Equipment Development Laboratory, Hitachi, Ltd. (72) Inventor Kazuharu Yuno 5-2-1 Omikacho, Hitachi City, Ibaraki Pref. 810 Shimoimaizumi Inside Hitachi Office System Design and Development Center

Claims (4)

[Claims] A first processor, a second processor, a main memory, an input / output device, a first processor bus connected to the first processor, and a second processor connected to the second processor. An information processing apparatus comprising: a second processor bus; a memory bus connected to the main memory; and a system bus connected to the input / output device, wherein the first processor bus, the second processor bus, and the Connecting means for connecting a memory bus and the system bus and transferring data between any two of the first processor, the second processor, the main memory, and the input / output device; The means transfers a first data signal between the first processor and the main memory using the connected first processor bus and the memory bus. Using a first data transfer mode, connected to the memory bus said system bus,
A third data transfer mode for transferring a second data signal between the main memory and the input / output device, and using the connected system bus and the second processor bus, A fourth data transfer mode for transferring a third data signal between the second processor and the second processor, wherein the second processor bus and the first processor bus are connected to each other; An information processing apparatus, which executes any one of a first data transfer mode for transferring a first data signal with a first processor. 2. The information processing apparatus according to claim 1, wherein a cache memory is connected to at least one of said first processor and said second processor. 3. A first device, a second device, a third device, a fourth device, a first bus connected to the first device, a second bus connected to the second device, A third bus connected to a third device;
An information processing apparatus having a fourth bus connected to a device, wherein the first bus, the second bus, the third bus, and the fourth bus
A connection device that connects to a bus and enables data transfer between any two of the first device, the second device, the third device, and the fourth device using these buses; A first data transfer mode for transferring a first data signal between the first device and the second device using the first bus and the second bus connected to the connection device; A second data transfer mode for transferring a second data signal between the second device and the third device using the second bus and the third bus, and the connected third bus And the fourth bus, and the
A third data transfer mode for transferring a third data signal between the second device and the third device, and using the fourth bus and the first bus connected to each other; An information processing apparatus, which enables any one of a fourth data transfer mode for transferring a fourth data signal to and from a device. 4. The information processing apparatus according to claim 3, wherein a cache memory is connected to at least one of said first device and said fourth device.