JPH1131119A - Data transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer circuit which surely performs transfer up to the end of data and efficiently performs data transfer even when it is applied to a data communication system that performs a finite data input. SOLUTION: This data transfer circuit is a data transfer circuit 15 that performs data transfer between peripheral circuits and main memory through a data bus. It detects the existence of a data input from a peripheral circuit and performs data transfer when data quantity that is temporarily stored in internal memory 152 exceeds a prescribed threshold in a period when there is a data input. On the other hand, in a period when there is no data input, it performs data transfer regardless of whether data quantity that is temporarily stored in the memory 152 exceeds the threshold or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is applied to a terminal device or the like of a data communication system, and transfers data input from a peripheral circuit (including a bus master) to a main memory of the terminal device or the like via a data bus. The present invention relates to a data transfer circuit.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing an example of a conventional data transfer circuit of this kind.

Referring to FIG. 8, this data transfer circuit comprises:
Data input interface 25 for converting the format of data input from a peripheral circuit (not shown) to a format handled internally
1, an internal memory 252 for temporarily storing data from the data input interface 251, and an internal memory 2
An internal memory control circuit 253 for controlling while counting the number of data to be written to and read from the data 52 and the number of data to be read, and calculates the amount of data stored in the internal memory 252 based on the count result of the internal memory control circuit 253. Subtraction circuit 254 and subtraction circuit 254
A comparison circuit 25 that compares the amount of data stored in the internal memory 252 obtained from the above with a threshold value, detects that the data amount has exceeded the threshold value, and outputs a threshold excess signal Th.
5 and a bus master control circuit 2 for controlling execution of data transfer based on the threshold excess signal Th from the comparison circuit 255.
56.

Next, the operation of the conventional data transfer circuit will be described.

When data is sent from a peripheral circuit, the sent data is sent to the data input interface 251.
Is converted from the format of the input data to the data transfer circuit to the format in the data transfer circuit and sent to the internal memory 252.

The data sent to the internal memory 252 is temporarily stored in the internal memory 252 at the address indicated by the write address pointer, and is output to the bus master control circuit 256 from the address indicated by the read address pointer.

The internal memory control circuit 253 has two counters for a write address pointer and a read address pointer. The write address pointer is used to control the input side of the internal memory 252, and increments the counter by one each time it detects that there has been one data input from the data input interface 251. The read address pointer is used for controlling the output side of the internal memory 252, and increments the counter by one each time it detects that the bus master control circuit 256 has performed one data transfer.

The subtraction circuit 254 is connected to the internal memory control circuit 2
The difference between the write address pointer and the read address pointer in 53 is calculated, and the amount of data currently stored in the internal memory 252 is calculated.

The comparison circuit 255 compares the amount of data stored in the internal memory 252 obtained from the subtraction circuit 254 with a threshold value, detects that the data amount has exceeded the threshold value, and detects a threshold excess signal. Th is output to the bus master control circuit 256.

[0010] The bus master control circuit 256 performs overall control of the data bus. In addition, execution of data transfer is controlled based on the threshold excess signal Th from the comparison circuit 255. Specifically, the threshold excess signal T from the comparison circuit 255
h is monitored, and if the amount of data currently stored in the internal memory 252 exceeds the threshold value, the data transfer is executed in a burst manner. When the amount of data stored in the internal memory 252 becomes equal to or smaller than the threshold, the data transfer is terminated. According to such a method, data transfer can be performed efficiently.

[0011]

SUMMARY OF THE INVENTION Including the above example,
In a conventional data transfer circuit, there is a problem that if there is a finite data input, data having a data amount equal to or less than the threshold value remains in the internal memory. The data remaining in the internal memory in this manner is not transferred until the data exceeds the next threshold value. Moreover, because of the finite data input, it is not expected that the threshold value will be exceeded next, and the data will remain permanently in the internal memory. In particular, this is a problem when the data remaining in the internal memory is important data.

As a method for preventing such a situation, a method in which the concept of the threshold value is deleted, that is, a method in which data transfer is started when at least one data to be transferred is accumulated in the internal memory. Conceivable. Specifically, this method includes comparing a data amount stored in an internal memory with a 0 data amount, detecting that the data amount is 0, and outputting a data amount zero signal 0, and a comparing circuit. And a bus master control circuit that controls the execution of data transfer based on the data amount zero signal 0 from the CPU.

However, when this method is adopted, the occupation rate of the data bus to be used becomes high, and efficient data transfer cannot be performed. In particular, recently, many peripheral circuits often use the same data bus, and it is not preferable that the occupation ratio be high. For this reason, in order to transfer data efficiently, it is necessary to keep the concept of the threshold value.

An object of the present invention is to provide a data transfer circuit capable of transferring data to the end of data reliably and efficiently transferring data even when applied to a data communication system to which finite data is input. is there.

[0015]

According to the present invention, in a data transfer circuit for transferring data between a peripheral circuit and a main memory through a data bus, the presence or absence of data input from the peripheral circuit is detected, and During a certain period, data transfer is performed when the amount of data temporarily stored inside exceeds a predetermined threshold value, while during a period of no data input, the amount of data temporarily stored internally exceeds the threshold value. A data transfer circuit characterized in that data transfer is performed regardless of whether or not the data is exceeded.

According to the present invention, a data input interface for converting a format of data input from the peripheral circuit to a format used internally is provided, and a data input interface is provided based on a predetermined signal input prior to data input from the peripheral circuit. An input valid period detection circuit for detecting the presence or absence of data input, an internal memory for temporarily storing data from the data input interface, and counting the number of data to be written and read to and from the internal memory. An internal memory control circuit that controls the internal memory, a subtraction circuit that calculates the amount of data stored in the internal memory based on the count result of the internal memory control circuit, and an internal memory that is stored in the internal memory obtained from the subtraction circuit. The data amount is compared with the threshold value and the 0 data amount, and the data amount is A comparison circuit for detecting that the threshold value has been exceeded and that the data amount is 0, and a bus master control for controlling execution of data transfer based on the detection signal of the input valid period detection circuit and the detection signal of the comparison circuit And a data transfer circuit having a circuit.

Further, according to the present invention, the bus master control circuit is configured to output the data when the data input is present and the amount of data stored in the internal memory exceeds the threshold value or when there is no data input. The data transfer circuit for controlling the data stored in the memory to perform data transfer until the data amount becomes zero is obtained.

According to the present invention, the bus master control circuit starts data transfer when data is input or when the amount of data stored in the internal memory exceeds the threshold value. Control to terminate the data transfer when the amount of data stored in the internal memory becomes 0, and to switch between performing and not performing data transfer when there is data input. The data transfer circuit described in ☆ 2 is obtained.

According to the present invention, further, the data input interface and the input valid period detection circuit may be configured such that:
No. format, Sync. The data transfer circuit is provided which is switchably compatible with a plurality of data input formats including a format and a handshake format.

According to the present invention, the internal memory further comprises:
The data transfer circuit temporarily stores data from the data input interface at an address specified by a write address pointer, and sequentially outputs data from an address specified by a read address pointer.

According to the present invention, the internal memory control circuit further includes a write counter for a write address pointer of the internal memory and a read counter for a read address pointer, and counts the number of data to be written by the write counter. At the same time, the number of data to be read is counted by a read counter, and the subtraction circuit calculates the amount of data stored in the internal memory from the difference between the write counter count result of the internal memory control circuit and the count result of the read counter. The above data transfer circuit is obtained.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a terminal device in a data communication system to which a data transfer circuit according to an embodiment of the present invention is applied. With reference to FIG. 1, the present terminal device transmits an MP transmitted from an artificial satellite (not shown).
It is assumed that the device handles EG image data. The terminal device includes an antenna 10 for receiving image data sent from an artificial satellite, a tuner 11 for selecting a data received by the antenna 10, and demodulation of modulated data output from the tuner 11. A QPSK demodulation circuit 12 that performs error correction on a transmission line for data output from the QPSK demodulation circuit 12, a descrambling circuit 14 that descrambles data output from the error correction circuit 13, , The data output from the descrambling circuit 14
A data transfer circuit 15 according to the present invention for transferring data to
A CPU 16 for controlling a data bus and a memory 1 for temporarily storing data transferred from the data transfer circuit 15
7 and the data stored in the memory 17 are read, and the MPEG image data in the transport stream format is
TS DEMUX18 to be multiplexed and TS DEMUX18
An MPEG decoder 19 for decoding the data demultiplexed by the EMUX 18, and an MPEG decoder 1
9 and a display circuit 20 for displaying the data decoded.

FIG. 2 is a block diagram showing a configuration of the data transfer circuit 15 according to the present invention shown in FIG. Referring to FIG. 2, data transfer circuit 15 includes a data input interface 151 for converting a format of data input from descrambling circuit 14 (FIG. 1) into a format handled internally.
Input valid period detection for monitoring the Enable1 signal as a predetermined signal input from the descrambling circuit 14 prior to data input, detecting the presence or absence of data input, and outputting the data input presence / absence signal DI indicating the presence / absence of data input A circuit 157, an internal memory 152 for temporarily storing data from the data input interface 151, and an internal memory control circuit 153 for controlling while counting the number of data to be written and read to and from the internal memory 152, and A subtraction circuit 154 for calculating the amount of data stored in the internal memory 152 based on the count result of the internal memory control circuit 153, and a threshold value and a data amount stored in the internal memory 152 obtained from the subtraction circuit 154. Data amount is threshold compared to 0 data amount respectively The excess it and the amount of data is 0
, And outputs a threshold excess signal Th and a data amount zero signal 0, a data input presence / absence signal DI from the input valid period detection circuit 157, and a threshold excess signal Th from the comparison circuit 155. And a bus master control circuit 156 for controlling the transfer of data stored in the internal memory 152 to the memory 17 (FIG. 1) or the like based on the data amount zero signal 0.

Next, the operation of the data transfer circuit 15 will be described.

First, descrambled data is sent from the descrambling circuit 14. Here, it is assumed that data is input in a format as shown in FIG. That is, Clock, Enable1, and Da
Three types of signals of ta (7: 0) are transmitted. Dat
It is assumed that a is input in 8 bits. This data input cannot be controlled from the data transfer circuit 15. That is, the input is performed in a format other than the handshake. In FIG. 3, a period in which the Enable1 signal is High is a data input valid period. Therefore, the data input interface 151 needs to take in the data of the valid period. Data input interface 151
Is not only an interface corresponding to the waveform as shown in FIG. Format or handshake format. Further, a plurality of data input formats may be switchably supported. In this case,
The input valid period detection circuit 157 also supports a plurality of data input formats.

In the input valid period detecting circuit 157, E
It monitors the enable1 signal and generates a data input presence / absence signal DI indicating a valid period / invalid period of data input. The data input presence signal DI is, as shown in FIG.
“High indicates a valid period during which data is input”, and “Low indicates an invalid period during which no data is input”.

The internal memory 152 stores data from the data input interface 151 in the internal memory control circuit 1.
53 temporarily stores the data at the address specified by the write address pointer and sequentially outputs data from the address specified by the read address pointer.

The internal memory control circuit 153 includes a write counter for a write address pointer of the internal memory 152 and a read counter for a read address pointer. The internal memory control circuit 153 counts the number of data to be written by a write counter and the number of data to be read by a read counter.

The subtraction circuit calculates the amount of data stored in the internal memory 152 from the difference between the count result of the write counter of the internal memory control circuit 153 and the count result of the read counter.

The comparison circuit 155 compares the data amount calculated by the subtraction circuit 154 with a predetermined threshold value. As a result of the comparison, “if the amount of data currently stored in the internal memory 152 exceeds the threshold, the threshold excess signal Th is set to Low”, and “if not, the threshold excess signal Th is set to High”. And outputs it to the bus master control circuit 156. Further, the comparison circuit 155 determines whether the data amount is 0, and “if the data amount currently stored in the internal memory 152 is present, the data amount zero signal 0 is set to High.
, And if “0”, the data amount zero signal 0 is set to Low ”and output to the bus master control circuit 156.

The bus master control circuit 156 has a data input presence / absence signal D output from the input valid period detection circuit 157.
I'm watching.

If the data input presence / absence signal DI is High, that is, if data is currently being input, the bus master control circuit 15
6 is a threshold excess signal T output from the comparison circuit 155.
h is sampled. If the threshold excess signal Th is Low, that is, if the amount of data currently stored in the internal memory 152 exceeds the threshold, data transfer is started. On the other hand, if the threshold excess signal Th is High, that is, if the data amount currently stored in the internal memory 152 does not exceed the threshold value, the process stands by until the data amount exceeds the threshold value.

If the data input presence / absence signal DI is Low, that is, if no data is currently input, the bus master control circuit 156 outputs the signal to the internal memory 152 regardless of the state of the threshold excess signal Th output from the comparison circuit 155. Data transfer is started regardless of whether the currently stored data amount exceeds or does not exceed the threshold value.

After the data transfer is started in any of the above cases, the bus master control circuit 156 operates the comparison circuit 1
Always monitor the data amount zero signal 0 output from 55,
When the data amount zero signal 0 is Low, that is, when there is no more data to be transferred to the internal memory 152, the data transfer ends.

FIG. 5 is a diagram showing the situation at this time. The period during which the data input presence / absence signal DI is High (period A
In C), since data input is expected, the process waits until the amount of data stored in the internal memory 152 exceeds a set threshold value. When the data amount exceeds the threshold (at timing or), burst-like data transfer is started. By this data transfer, the internal memory 1
When the amount of data stored in 52 becomes 0 (at the timing or), the data transfer ends temporarily. If the threshold value is set to be larger than the data amount input by data input, the data input presence / absence signal DI becomes Lo.
Data transfer can be performed only in the section of w, and more efficient data transfer can be performed.

FIG. 6 shows a configuration example of the state machine in the bus master control circuit 156. here,
Suppose there is another state machine that manages this state machine. Now, this state machine includes an initial state state S0 and an address phase state S1.
, A data transfer phase state S2, and a transfer end state S3. This configuration is a very basic configuration in consideration of convenience of description. This state machine in the bus master control circuit 156 proceeds according to the following conditions A to D.

Condition A: (threshold excess signal Th = Low)
or (Data input presence / absence signal DI = Low) Condition B: Completion of address phase state S1 Condition C: Data amount zero signal 0 = Low Condition D: (Data amount zero signal 0 = High) and (bus cycle = Stop) Initial state state In S0, the threshold excess signal Th and the data input presence / absence signal DI are monitored, and one of them is Low.
, The data transfer starts, that is, shifts to the address phase state S1.

In the address phase state S1, when the address phase on the data bus is completed, the process shifts to the data transfer phase state S2.

In the data transfer phase state S2, the data amount zero signal 0 is monitored, and when this signal becomes low, the process shifts to the transfer end state S3.

From the transfer end state S3, the process unconditionally shifts to the initial state S0 to prepare for the next data transfer.

FIG. 7 is a diagram showing examples of waveforms of various signals when the data bus is a PCI bus of a personal computer. FIG. 7 shows the states of the state machine of the bus master control circuit 156 shown in FIG. 6 in association with each other. FIG. 7 shows only the minimum signals among the signals related to the operation of the PCI bus for convenience of description.

In FIG. 7, the data transfer circuit 15 according to the present invention is divided into a period in which data input is expected and a period in which data input is not expected. Bus master control circuit 15
In No. 6, during the period in which data input is expected, the transfer efficiency is maintained by transferring the data while leaving the concept of the threshold value. On the other hand, in a period during which no input is expected, the concept of the threshold is deleted, and data transfer is performed regardless of whether the remaining data amount exceeds or does not exceed the threshold. When the final data has been entered, the data entry always enters the invalid period. In the invalid period of the data input, the amount of data stored in the internal memory 152 is transferred regardless of the threshold value, so that the data below the threshold does not remain in the internal memory 152. . That is, it is possible to transfer data reliably to the last data and to perform data transfer efficiently.

Further, if a function of switching whether or not to perform data transfer during a period in which data input is not expected is added, it is possible to perform conventional data transfer.

[0045]

The data transfer circuit according to the present invention detects the presence / absence of data input from a peripheral circuit, and when the amount of data temporarily stored therein exceeds a predetermined threshold during a period in which data is input. On the other hand, during the period when there is no data input, data transfer is performed regardless of whether the amount of data temporarily stored inside exceeds or does not exceed the threshold value. Even when applied, data can be reliably transferred to the end and data can be transferred efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a terminal device to which a data transfer circuit according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a data transfer circuit according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a waveform of input data to a data transfer circuit illustrated in FIG. 2;

FIG. 4 is a diagram for explaining an operation of an input valid period detection circuit in the data transfer circuit shown in FIG. 2;

FIG. 5 is a diagram illustrating an example of timing at which data transfer is performed by the data transfer circuit illustrated in FIG. 2;

FIG. 6 is a diagram illustrating a configuration example of a state machine of the data transfer circuit illustrated in FIG. 2;

FIG. 7 is a diagram showing an example of a waveform when the state machine shown in FIG. 6 is applied to a PCI bus.

FIG. 8 is a block diagram showing a configuration of a data transfer circuit according to a conventional example.

[Explanation of symbols]

 Reference Signs List 10 antenna 11 tuner 12 QPSK demodulation circuit 13 error correction circuit 14 descrambling circuit 15 data transfer circuit 16 CPU 17 memory 18 TS DEMUX 19 MPEG decoder 20 display circuit 151, 251 data input interface 157 input valid period detection circuit 152, 252 internal memory 153, 253 Internal memory control circuit 154, 254 Subtraction circuit 155, 255 Comparison circuit 156, 256 Bus master control circuit S0 Initial state state S1 Address phase state S2 Data transfer phase state S3 Transfer end state

Claims (7)

[Claims] 1. A data transfer circuit for transferring data between a peripheral circuit and a main memory through a data bus,
While detecting the presence or absence of data input from the peripheral circuit, during the period of data input, while performing data transfer when the amount of data temporarily stored therein exceeds a predetermined threshold,
A data transfer circuit for performing data transfer regardless of whether the amount of data temporarily stored therein exceeds or does not exceed the threshold during a period in which there is no data input. 2. A data input interface for converting a format of data input from the peripheral circuit into a format used internally, and presence / absence of data input based on a predetermined signal input from the peripheral circuit prior to data input. , An internal memory for temporarily storing data from the data input interface, and an internal memory for controlling while counting the number of data to be written and read to and from the internal memory. A memory control circuit, a subtraction circuit that calculates an amount of data accumulated in the internal memory based on a count result of the internal memory control circuit, and a data amount accumulated in the internal memory obtained from the subtraction circuit. Compared with the threshold value and 0 data amount respectively, the data amount has exceeded the threshold value. And a comparison circuit for detecting that the data amount is 0, and a bus master control circuit for controlling execution of data transfer based on a detection signal of the input valid period detection circuit and a detection signal of the comparison circuit. Item 2. The data transfer circuit according to item 1. 3. The bus master control circuit according to claim 1, wherein when the data input is present and the amount of data stored in the internal memory exceeds the threshold, and when there is no data input, the bus master control circuit stores the data stored in the internal memory. 3. The data transfer circuit according to claim 2, wherein the data transfer circuit controls the data transfer until the data amount becomes zero. 4. The bus master control circuit controls to start data transfer when there is a data input or when the amount of data stored in the internal memory exceeds the threshold value. When the amount of data stored in the internal memory becomes zero, the data transfer is controlled to end, and when there is a data input, it is possible to switch between performing and not performing the data transfer. 3. The data transfer circuit according to 2. 5. The data input interface and the input valid period detection circuit are of an Enable type, Sy
nc. 5. The data transfer circuit according to claim 2, wherein the data transfer circuit is switchably compatible with a plurality of data input formats including a format and a handshake format. 6. The internal memory temporarily stores data from the data input interface at an address specified by a write address pointer, and sequentially outputs data from an address specified by a read address pointer. 6. The data transfer circuit according to any one of 2 to 5. 7. The internal memory control circuit includes: a write counter for a write address pointer of the internal memory;
A read counter for a read address pointer,
The number of data to be written is counted by a write counter, and the number of data to be read is counted by a read counter.
7. The data processing device according to claim 2, wherein the subtraction circuit calculates a data amount accumulated in the internal memory from a difference between the write counter count result of the internal memory control circuit and the count result of the read counter. Data transfer circuit.