JPH1131103A - Cache memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the traffic of a system bus and to improve the whole performance of a system by controlling data so that it is not registered in a cache array even if a data transfer request issued from an input/output processor is mishit. SOLUTION: When the request from a request source is a read instruction, the cache array 110 is accessed. When a hit detection circuit 140 detects cache hit in response to the access, requested data are outputted from the cache array 110 and it is transferred to an operation processing unit 200 or the input/output processor 300 being the request source through a selector 165. When cache mishit occurs in response to access to the request, the request is not registered in the cache array 110 when it is the read request on data transfer from the input/output processor 300 and it is registered in the cache array 110 when it is the request other than the request.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache memory device, and more particularly to a cache memory device shared by an arithmetic processing unit and an input / output processing unit.

[0002]

2. Description of the Related Art It is generally known that a processor repeatedly accesses the same or a nearby address, so that once accessed data can be stored in a cache memory device to increase the speed. That is, when the data related to the request is held in the cache memory device (hereinafter, referred to as a hit).
In this case, desired data can be obtained by accessing the cache memory device without accessing the main storage device.

In a conventional cache memory device, when data related to a request is not held (hereinafter, referred to as a mishit), a data block is transferred from a main memory and registered in the cache memory device, that is, a so-called on-demand replacement method. Is adopted.

[0004]

In the above-mentioned prior art,
When the data related to the request is not held, the contents in the main storage device are transferred to the cache memory device. However, when the cache memory device is shared by the arithmetic processing unit and the input / output processing unit, the following problems occur. That is, while the arithmetic processing unit repeatedly accesses local data, the input / output processing unit almost always transfers continuous data, and the same data is rarely repeatedly accessed. Therefore, if data of the input / output processing device is registered or updated in the cache memory device according to the same policy as that of the data of the arithmetic processing device, data of high use frequency is easily purged by data of low use frequency, and the system bus However, there is a problem that the traffic of the system increases and the improvement of the system performance is hindered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory device in which data handled by an input / output processing device and data handled by an arithmetic processing device are distinguished from each other, and the necessary data is hardly evicted.

[0006]

A cache memory device according to the present invention is a cache memory device shared by an input / output processing device and an arithmetic processing device, which responds to an access to a request. If a cache mishit occurs and the request is a read request related to data transfer from the input / output processing device, the request is not registered in the cache memory device. sign up.

Another cache memory device according to the present invention is a cache memory device shared by an input / output processing device and an arithmetic processing device, wherein the cache array includes a data array and an address array; When a cache mishit occurs due to a data transfer read request from the processing device, the registration processing to the cache array is not performed. When a cache mishit occurs due to other requests, the registration processing to the cache array is performed. A registration circuit.

Another cache memory device of the present invention is a cache memory device shared by an input / output processing device and an arithmetic processing device, and includes a cache array including a data array and an address array; A hit detection circuit for detecting a cache hit and a mishit in the cache array, and a registration process for the cache array when the cache mishit is detected by the hit detection circuit in response to a data transfer read request from the input / output processing device. And a registration circuit for performing a registration process for the cache array when a cache mishit caused by another request is detected by the hit detection circuit.

Further, another cache memory device according to the present invention further includes a decoder for decoding a request from a request source, and the registration circuit receives a data transfer read request from the input / output processing device based on a decoding result of the decoder. It is determined whether or not there is.

Further, an information processing system according to the present invention provides a main storage device, a cache memory device for storing a copy of the main storage device, an input / output processing device and an arithmetic processing device sharing the cache memory device. The cache memory device includes: a cache array including a data array and an address array; and a registration process for the cache array when a cache mishit occurs due to a data transfer read request from the input / output processing device. And a registration circuit for performing a registration process for the cache array when a cache miss occurs due to other requests.

Further, another information processing system of the present invention comprises:
Including a main storage device, a cache memory device that stores a copy of the main storage device, and an input / output processing device and an arithmetic processing device that share the cache memory device;
The cache memory device includes a cache array including a data array and an address array, a hit detection circuit for detecting a cache hit and a mishit in the cache array, and a cache miss due to a data transfer read request from the input / output processing device. When the hit is detected by the hit detection circuit, the registration processing for the cache array is not performed. When a cache mishit due to other requests is detected by the hit detection circuit, the registration processing for the cache array is performed. Registration circuit to perform.

In another information processing system according to the present invention, the cache memory device further includes a decoder for decoding a request from a request source, and the registration circuit receives a request from the input / output processing device based on a decoding result of the decoder. It is determined whether the request is a data transfer read request.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, in an information processing system to which the present invention is applied, a main storage device 500 and at least one cache memory device 100 are connected to a system bus 400. At least one arithmetic processing unit 200 and at least one input / output processing unit 300 are connected to the cache memory device 100.

The arithmetic processing unit 200 includes a main storage device 500
And executes each instruction in the program according to the program stored in the program. At this time, if necessary, the main storage device 500
Use the data above.

The input / output device 300 is connected to a peripheral device (not shown), and controls data transfer between the peripheral device and the main storage device 500.

Arithmetic processing unit 200 and input / output processing unit 3
When accessing the main memory 500, the contents of the cache memory 100 are checked, and if the data to be accessed exists in the cache memory 100, the cache memory 100 is accessed without accessing the main memory 500. Access the device 100.

Referring to FIG. 2, a cache memory device 100 includes a cache array 110 and a decoder 120.
, A registration circuit 130, a hit detection circuit 140, an interface circuit 150, a read buffer 160, a store buffer 170, a data coupling circuit 180, and selectors 155, 165, and 185.

The cache array 110 has a main storage device 5
The data array includes a data array for storing a part of the data array 00, an address array for managing each data stored in the data array, and the like.

The decoder 120 decodes requests from the arithmetic processing unit 200 and the input / output processing unit 300,
Check the device type of the request source and the command type. Instruction type is read instruction or write instruction (also called store instruction)
And the type of control instruction or data transfer instruction. Here, the control command refers to a transfer command of a channel program, a transfer command of control information related to an input / output command, and the like. The data transferred by the data transfer instruction is continuous data accessed by the peripheral device and does not have the property of repeatedly accessing the same data once transferred. On the other hand, what is transferred by the control command has a property of being repeatedly accessed, such as a channel program.

The registration circuit 130 generates a timing for registering data from the main storage device 500 to the cache array 110 according to the decoding result from the decoder 120.

The hit detection circuit 140 searches the address array in the cache array 110 to detect whether or not the data relating to the request exists in the data array in the cache array 110.

The interface circuit 150 exchanges data between the cache memory device 100 and the system bus 400.

The read buffer 160 includes a selector 155
Temporarily store the data selected in. The store buffer 170 is provided for the arithmetic processing device 200 or the input / output processing device 3
From 00, the store data to the main storage device 500 is temporarily stored.

The data combining circuit 180 performs a process of combining the data stored in the read buffer 160 with the data from the store buffer 170.

The selector 155 is connected to the cache array 11
Either data from 0 or data from the interface circuit 150 is selected and given to the read buffer 160. The selector 165 selects the data from the cache array 110 or the data from the read buffer 160 and outputs the selected data to the arithmetic processing device 200 or the input / output processing device 300 of the request source. The selector 185 selects data from the data coupling circuit 140 or data from the read buffer 160 and supplies the selected data to the cache array 110.

Next, the operation of the embodiment of the cache memory device of the present invention will be described with reference to the drawings.

Referring to FIGS. 2 and 3, when a request from a request source is issued, the decoder 120 decodes the request. This decryption result is stored in the registration circuit 130. If the decryption result is a read instruction (step S101), the cache array 110 is accessed. When the hit detection circuit 140 detects a cache hit in response to this access (step S102),
The requested data is output from the cache array 110 and is sent via the selector 165 to the processing unit 2 of the request source.
00 or transferred to the input / output processing device 300 (step S106).

When the hit detection circuit 140 detects a cache mishit (step S102), the interface circuit 150 issues a block load instruction to the system bus 40.
0 to the main storage device 500 (step S1).
03). After a predetermined access time has elapsed, main storage device 500 outputs the requested block data to system bus 400. This block data is stored in the interface circuit 1
From the read buffer 160 via the selector 155
Is stored temporarily.

The decryption result stored in the registration circuit 130 is “a request issued from the input / output processing device”.
And if it is a “data transfer request” (step S
104), without registering in the cache array 110,
The data stored in the read buffer 160 is the selector 1
The data is transferred to the input / output processing device 300 of the request source via the link 65. On the other hand, if the request is not “a request issued from the input / output processing device” or is not a “data transfer request” (step S104), the read buffer 160
Is registered in the cache array 110 (step S105), and transferred to the requesting input / output processing device 300 via the selector 165.

That is, the data transferred from the main storage device 500 to the input / output processing device 300 must be transferred from the peripheral device to the main storage device 500 for the next data transfer. Is hardly used by other devices connected to the cache array 110, the data is not registered in the cache array 110 even when a cache miss occurs due to a read instruction.

Next, if the result of decoding by the decoder 120 is a write command (step S101), the cache array 110 is first accessed. When the hit detection circuit 140 detects a cache mishit in response to this access (step S112), the interface circuit 150 issues a block load instruction to the main storage device 500 via the system bus 400 (step S11).
3). In this case, the main storage device 500 outputs the requested block data to the system bus 400 after a predetermined access time has elapsed. The block data is temporarily stored in the read buffer 160 from the interface circuit 150 via the selector 155. On the other hand, when the hit detection circuit 140 detects a cache hit, the requested data is output from the cache array 110,
The data is temporarily stored in the read buffer 160 via the selector 155 (step S116).

The data combination circuit 180 combines the data (block data) stored in the read buffer 160 with the store data from the store buffer 170 (step S114). The data combined by the data combining circuit 180 is registered in the cache array 110 via the selector 185.

That is, in the case of a write instruction, even a data transfer from the input / output processing device 300 is registered in the cache array 110. The reason for this operation is that data written from the input / output processing device 300 to the main storage device 500 is highly likely to be accessed by the arithmetic processing device 200 as it is.

As described above, according to the embodiment of the present invention, even when a data transfer read request issued from the input / output processing device 300 has a mishit, the data is not registered in the cache array 110. The required data is stored in the cache array 1
10 can be made harder to be kicked out.

[0036]

As is apparent from the above description, according to the present invention, data transferred from the main storage device to the input / output processing device is not registered in the cache memory device, and it becomes difficult to remove frequently used data. Therefore, the traffic on the system bus is reduced, and the performance of the entire system is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an information processing system to which the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of a cache memory device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a flow of an operation according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 100 cache memory device 110 cache array 120 decoder 130 registration circuit 140 hit detection circuit 150 interface circuit 155, 165, 185 selector 160 read buffer 170 store buffer 180 data coupling circuit 200 arithmetic processing device 300 input / output processing device 400 system bus 500 main storage apparatus

Claims (7)

[Claims] 1. A cache memory device shared by an input / output processing device and an arithmetic processing device, wherein when a cache mishit occurs in response to an access to a request, the request is sent from the input / output processing device. A cache memory device which does not register a read request related to the data transfer of the above in the cache memory device, and registers the other request in the cache memory device. 2. A cache memory device shared by an input / output processing device and an arithmetic processing device, comprising: a cache array including a data array and an address array; and a cache provided by a data transfer read request from the input / output processing device. A registration circuit that does not perform registration processing on the cache array when a mishit occurs, and performs registration processing on the cache array when a cache mishit occurs due to other requests. Cache memory device. 3. A cache memory device shared by an input / output processing device and an arithmetic processing device, comprising: a cache array including a data array and an address array; and detecting a cache hit and a mishit in the cache array. A hit detecting circuit, when a cache mishit is detected by the hit detecting circuit in response to a data transfer read request from the input / output processing device, the registration processing for the cache array is not performed; And a registration circuit for performing a registration process for the cache array when the hit detection circuit detects the data. 4. A decoder for decoding a request from a request source, wherein the registration circuit determines whether or not the request is a data transfer read request from the input / output processing device based on a decoding result of the decoder. 4. The cache memory device according to claim 3, wherein 5. An information processing system comprising: a main storage device; a cache memory device storing a copy of the main storage device; and an input / output processing device and an arithmetic processing device sharing the cache memory device. The cache memory device includes a cache array including a data array and an address array, and does not perform a registration process on the cache array when a cache mishit occurs due to a data transfer read request from the input / output processing device. And a registration circuit for performing a registration process for the cache array when a cache miss occurs due to a request other than the above. 6. An information processing system comprising: a main storage device; a cache memory device that stores a copy of the main storage device; and an input / output processing device and an arithmetic processing device that share the cache memory device. A cache array including a data array and an address array; a hit detection circuit for detecting cache hits and mishits in the cache array; and a cache miss due to a data transfer read request from the input / output processing device. When the hit is detected by the hit detection circuit, the registration processing for the cache array is not performed. When a cache mishit due to other requests is detected by the hit detection circuit, the registration processing for the cache array is performed. Registration circuit to perform An information processing system characterized by: 7. The cache memory device further includes a decoder for decoding a request from a request source, and the registration circuit determines whether or not the request is a data transfer read request from the input / output processing device based on a decoding result of the decoder. The information processing system according to claim 6, wherein the determination is performed.