JPH11308534A - Output buffer for ccd solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in an output buffer by constituting the output buffer by connecting it between the power supply terminal of a first power source to be used for reset and the power supply terminal of a second power source which is used for the transfer drive of electric charges or having a power supply voltage lower than the first power source having a voltage similar to such a power source. SOLUTION: Concerning an output buffer 11 for a CCD solid-state imaging device, a well 6a is selectively formed on the surface part of an n-type semiconductor substrate 5. Inside the well 6a, a driving transistor M1 for a source follower circuit on the first stage of the output buffer 11 is formed together with a floating diffusion area 7, a horizontal transfer register or an image pickup area. A first power source 8 generates the power supply voltage of 15 V, for example, and a second power source 9 is a power source for a horizontal transfer register transfer drive but prepares a power supply voltage for the output buffer 11 together with the first power source 8 as well. The power supply voltage generated by this second power source 9 is 7 V, for example.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output buffer of a CCD solid-state image pickup device, and more particularly to a first power supply and at least a second power supply having an absolute value of a power supply voltage smaller than the first power supply. Cascade-connected source follower circuits of a plurality of stages which receive at least the potential of the floating diffusion region of the CCD solid-state imaging device used for resetting the floating diffusion region near the output end of the charge transfer section as an input. Output buffer.

[0002]

2. Description of the Related Art A CCD solid-state imaging device has a schematic configuration as shown in FIG. In the figure, reference numeral 1 denotes an image area (imaging area) in which light receiving elements are arranged vertically and horizontally, and a vertical transfer register is provided corresponding to each light receiving element vertical column. Reference numeral 2 denotes a horizontal transfer register, which transfers signal charges vertically transferred from each vertical transfer register in the horizontal direction. F
D is a floating diffusion region provided on the output end side of the horizontal transfer register 2, and is repeatedly reset to a predetermined reset potential, and thereafter, receives a signal charge from the horizontal transfer register 2 and repeats an operation of becoming a potential corresponding to the signal charge. . Reference numeral 3 denotes the output buffer (output buffer circuit), and FIG. 4 shows one conventional example.

[0005] M1 is a MOS transistor having a gate connected to the floating diffusion region FD, forming a drive transistor of a source follower circuit in the first stage, and a drain connected to a power supply _VDD terminal. The power supply voltage V _DD is relatively high, for example, about 15V. This is because a high voltage of about 15 V is required as a reset voltage in order to completely reset the electrons transferred by the horizontal transfer register 2. And
In connection with this, the DC level of the output of the horizontal transfer register 2 also becomes a high value of 10 V or more. In response to this, the power supply of about 15 V has been used as it is as the power supply for the output buffer.

A MOS transistor M2 forms a current source (current supply means) for the MOS transistor M1. The gate of the MOS transistor M2 receives a constant voltage V _GG and the drain thereof is MO.
The source of the S transistor M1 is grounded via a resistor R _SS . M3 is a MOS transistor forming a drive transistor of a source follower circuit of the next stage, M4
Is a MOS transistor forming the current source,
M5 is a MOS transistor forming a driving transistor of the last source follower circuit, and M6 is a MOS transistor forming a current source thereof.
OS transistor. Note that these transistors M
1 to M6 are all N-channel MOS transistors,
For example, the driving MOS transistors M1, M3, and M5 are in an enhancement mode, and the MOS transistors M2, M4, and M6 forming a current source are in a depletion mode.

As described above, the signal charges transferred by the horizontal transfer register 2 of the solid-state image sensor are impedance-converted by an output buffer comprising a multi-stage source follower circuit and output to the outside (outside the solid-state image sensor).

Conventionally, the output buffer is about 1
The power supply voltage V _{DD of} 5 V was used as it was as the power supply voltage.

[0007]

However, the output buffer can actually operate sufficiently even with a power supply voltage of about 5 V. Nevertheless, if such an unnecessarily high voltage is used as the power supply voltage, a large waste of power consumption occurs. This is a problem that cannot be overlooked. In particular, when the battery is used for a portable electronic device or the like, the life of a battery used as a power source is shortened, and the frequency of battery replacement is increased.

The present invention has been made to solve such a problem, and has as its object to reduce the power consumption of an output buffer of a CCD solid-state imaging device.

[0009]

According to the first aspect of the present invention, the output buffer of the CCD solid-state imaging device has a power supply terminal of the first power supply used for the reset operation, and a power supply used for the charge transfer drive or a voltage similar thereto. However, it is characterized in that it is connected between a power supply terminal of a second power supply having a lower power supply voltage than the first power supply.

Therefore, according to the output buffer of the CCD solid-state imaging device of the first aspect, the source follower circuit of each stage operates by receiving the difference between the power supply voltages of the first power supply and the second power supply as the power supply voltage. Therefore, the power supply voltage becomes lower than before, and wasteful power consumption is reduced. Relatively common CC
Taking a D solid-state image sensor as an example, the first power supply is 15 V
And a power supply voltage of 7 as a second power supply.
When a horizontal transfer drive power supply of V is used, a power supply voltage of 8 V is received, so that the power supply voltage of the output buffer is reduced to about one half of the conventional power supply, and wasteful power consumption can be significantly reduced. .

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The output buffer of the CCD solid-state imaging device according to the present invention basically includes a power supply terminal for a power supply used for electron transfer or a power supply terminal of a second power supply having a voltage similar to the power supply, and a power supply terminal for the second power supply. The power supply voltage is high and is connected between a power supply terminal of a first power supply and a power supply terminal of a first power supply which is also used for a reset operation.
The power supply voltage when a power supply for driving a horizontal transfer register is used as the power supply for the power supply is, for example, 7V. In this case, the power supply voltage of the output buffer is 8V.

However, these are merely one embodiment of the present invention, and the present invention is not limited to the embodiment. Further, the connection between the output buffer and the power supply terminal of the second power supply may be direct or via a resistor. With this configuration, the power supply voltage of the output buffer can be set to an optimum value by the resistor.

It is not indispensable to use the transfer drive power supply of the horizontal transfer register as the second power supply, and a power supply independent of the transfer drive power supply may be used. This is because if the power supply voltage is optimum for the transfer driving power supply, the difference between the first and second power supply voltages is not always the optimum value for the power supply voltage for the output buffer. When an independent power supply different from the horizontal transfer register driving power supply is used as the second power supply, the power supply voltage difference between the first and second power supplies can be set to an optimum value as the power supply voltage of the output buffer. Thus, wasteful power consumption in the output buffer can be substantially eliminated.

The transistors other than at least the first stage drive transistor in the plurality of stages of source follower circuits are wells electrically separated from the ground, that is, different from the well where the floating diffusion region and the horizontal transfer register are formed. It may be formed in a well, and the well may be connected to a power supply terminal of a second power supply. By doing so, the well becomes the power supply voltage level of the second power supply having an absolute value higher than the ground level, and furthermore, the gate oxide film of the MOS transistor constituting the output buffer can be made thinner, Characteristics can be improved. Also, since the PN junction breakdown voltage between the drain and the well can be reduced, the source /
It is possible to realize the Sylow Junction of the drain, and in that respect, it is also possible to improve the performance of the transistor.

It is preferable that only the driving MOS transistor of the first stage output buffer among the output buffers be formed in the floating diffusion region or in the well in which the horizontal transfer register is formed. That is, if the driving MOS transistor of the first-stage output buffer is formed in another well, the wiring connecting the floating diffusion region and the gate electrode of the driving MOS transistor of the first-stage output buffer becomes long, and the parasitic region is formed in the floating diffusion region. This is because the capacity of the output section increases and the conversion efficiency of the output section decreases. However, if the conversion rate can be made sufficiently high by other means, the driving MOS transistor in the first stage will be
The floating diffusion region may be provided in a well different from the well. Of course, when it is not necessary to take any special measures for improving the characteristics of these MOS transistors, all of the MOS transistors may be provided in a well having a floating diffusion region. As described above, the present invention can be implemented in various modes.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. 1A and 1B show one embodiment of an output buffer according to the present invention. FIG. 1A is a circuit diagram, and FIG. 1B is a sectional view showing a main part. In the drawing, reference numeral 5 denotes an n-type semiconductor substrate; 6a, a well formed selectively on the surface of the semiconductor substrate 5; in the well 6a, a floating diffusion region 7, a horizontal transfer register (not shown), an imaging region, or the like; And an output buffer (11) to be described later.
Drive transistor (M
1) is formed. 8 is a first power supply, for example, 15
V power supply voltage. Reference numeral 9 denotes a second power supply, which is originally a power supply for the horizontal transfer register transfer drive circuit 10, but in the present embodiment, the power supply voltage for the output buffer (11) is also used together with the first power supply 8. to make. The power supply voltage generated by the second power supply 9 is, for example, 7V.

Reference numeral 11 denotes an output buffer, which is composed of MOS transistors M1 to M6. In M1, the gate is the floating diffusion region 7 (FD).
, Constitutes a driving transistor of a source follower circuit of the first stage, and has a drain connected to a power supply terminal of the first power supply 8. The MOS transistor M1 is formed in the well 6a as described above.

M2 is a MOS transistor serving as a current source (current supply means) for the MOS transistor M1, and its gate receives a constant voltage _VGG and its drain is MO
The source of the S transistor M1 is connected to the power supply terminal of the second power supply 9 via a resistor R _SS . M
3 is a MOS transistor forming a driving transistor of a source follower circuit of the next stage, and M4 is a MOS transistor forming a current source thereof.
A transistor transistor, M5 is a MOS transistor forming a driving transistor of the final stage source follower circuit, and M6 is a MOS transistor forming a current source thereof. The sources of the MOS transistors M4 and M6 forming a current source are also connected to the power supply terminal of the second power supply 9 via the resistor Rss, similarly to the source of M2.

The transistors M2 to M6 are formed in a well 2b different from the well 2a, and the well 2b is connected to a power supply terminal of a second power supply 9. However, for convenience, the MOS transistors M3 to M6 are not shown in FIG. 1B, but exist in the well 2b. By doing so, the pn between the drain and the well 2b of the MOS transistors M2 to M6 in the well 2b is reduced.
The withstand voltage of the junction can be lower by the power supply voltage of the second power supply 9 than before, and the gate oxide film of each MOS transistor can be made thinner, and the characteristics of the MOS transistor can be improved. You can.

However, the MOS transistor M1, ie, the driving MOS of the source follower circuit of the first stage of the output buffer 11,
Providing only the transistor in the well 2a where the floating diffusion region 7 is provided instead of the well 2b can shorten the wiring length connecting the gate of the MOS transistor M1 and the floating diffusion region 7 and thus extend the floating diffusion region 7
This is because it is possible to reduce the parasitic capacitance that is parasitic on the device and increase the conversion efficiency of the output unit. That is, if the MOS transistor M1
The well 2 is similar to the other MOS transistors M2 to M6.
b, the characteristics of the MOS transistor M1 can be improved and the required breakdown voltage can be reduced. However, in that case, the distance between the MOS transistor M1 and the floating diffusion region 7 increases, and the gate electrode of the MOS transistor M1 increases. The length of the wiring connecting between the floating diffusion region 7 and the floating diffusion region 7 is increased, and the capacitance parasitic on the floating diffusion region 7 is increased. Therefore, the charge-to-voltage conversion rate of the output section is reduced. This is not preferred. Therefore, only the MOS transistor M1 is provided in the well 2a instead of the well 2b, with emphasis placed on improving the conversion efficiency of the output unit rather than improving its characteristics.

However, if the conversion rate can be made sufficiently high by other means or the like, the MOS transistor M1 is also connected to another M transistor.
It may be provided in the well 6b together with the OS transistors M2 to M6. Of course, the MOS transistors M1 to M1
If it is not necessary to take the above-described measures for improving the characteristics of M6, all the MOS transistors M1 to M6 may be provided in the well 2a.

According to such an output buffer 11, a voltage obtained by further subtracting the voltage drop at the resistor Rss from the difference between the power supply voltage of the first power supply 8 and the power supply voltage of the second power supply 9 as the power supply voltage, for example, 5V, this value is
This is a substantially optimum value as the power supply voltage of the output buffer 11,
No wasteful power consumption occurs.

FIG. 2 is a circuit diagram showing a second embodiment of the output buffer according to the present invention. In the present embodiment, instead of using the power supply for the horizontal transfer register as the second power supply, an independent power supply 19 is used.
The horizontal transfer register transfer drive circuit 10 is driven by a horizontal transfer register power supply 9a. The power supply voltage of the second power supply 19 is, for example, 10 V, and 5 V is supplied to the output buffer 11.
The voltage of V is applied as the power supply voltage. still,
In this embodiment, there is no resistor Rss. Therefore, the resistance Rss
No power consumption occurs. The horizontal transfer register transfer drive circuit 10 is a power supply 9 for the horizontal transfer register which is a dedicated power supply.
The power supply voltage (for example, 7V) is received from a.

According to the embodiment shown in FIG.
By setting the value obtained by subtracting the power supply voltage of the power supply voltage 9 from the power supply voltage of the first power supply voltage 8 to be an optimal value as the power supply voltage for the output buffer 11, wasteful power consumption can be eliminated. . However, the present invention can be implemented in a mode in which the resistor Rss is provided.

[0025]

According to the output buffer of the CCD solid-state imaging device of the first aspect, the source follower circuits of each stage operate by receiving the difference between the power supply voltages of the first power supply and the second power supply as the power supply voltage. Therefore, the power supply voltage becomes lower than before, and wasteful power consumption is reduced.

According to the output buffer of the CCD solid-state imaging device of the second aspect, the power source for driving the transfer of the charge transfer section is used as the second power source. Output buffer can be obtained.

According to the output buffer of the CCD solid-state imaging device, the source of each MOS transistor forming the current source of the output buffer is connected to the power supply terminal of the second power supply via the resistor. In addition, the power supply voltage of the output buffer can be reduced by the voltage drop caused by this.

According to the output buffer of the CCD solid-state imaging device of the present invention, at least each transistor other than the driving transistor of the first stage among the plurality of source follower circuits is formed in a well electrically separated from the ground. ,
Since the well is connected to the power supply terminal of the second power supply,
The withstand voltage required for the PN junction between the drain of the transistor in the well and the well is reduced by the power supply voltage of the second power supply, and the gate oxide film of the transistor can be made thinner. Can improve the characteristics of the transistor.

According to the output buffer of the CCD solid-state image pickup device of the present invention, since a power source different from the power source for the horizontal transfer register is used as the second power source, the power source voltage of the power source is reduced. The value obtained by subtracting the value from the power supply voltage can be set so as to be an optimum value as the power supply voltage for the output buffer, and it is possible to eliminate wasteful power consumption.

[Brief description of the drawings]

FIGS. 1A and 1B show one embodiment of an output buffer of the present invention, in which FIG. 1A is a circuit diagram and FIG. 1B is a cross-sectional view showing a main part.

FIG. 2 is a circuit diagram showing a second embodiment of the output buffer of the present invention.

FIG. 3 is a plan view illustrating a schematic configuration of a CCD solid-state imaging device.

FIG. 4 is a circuit diagram showing a conventional example of an output buffer of a CCD solid-state imaging device.

[Explanation of symbols]

5 ... semiconductor substrate, 6a, 6b ... well, 7 ...
・ Floating diffusion area (FD), 8.
.. A first power supply, 9 a second power supply, 10 a horizontal transfer register transfer drive circuit, 11 a source follower circuit, 19 a second power supply.

Claims (5)

[Claims] 1. A CCD solid-state imaging device using at least a first power supply used for resetting a floating diffusion region near an output end of a charge transfer unit and a second power supply having an absolute value of a power supply voltage smaller than the first power supply. What is claimed is: 1. An output buffer, comprising a plurality of source follower circuits connected in cascade, receiving an electric potential of said floating diffusion region of an element as an input, said output buffer comprising: a power supply terminal of said first power supply; An output buffer for a CCD solid-state imaging device, wherein the output buffer is connected between a power supply terminal of a power supply and a power supply terminal. 2. The CCD according to claim 1, wherein a transfer drive power supply of the charge transfer section is used as the second power supply.
Output buffer of solid-state image sensor. 3. The CCD solid-state imaging device according to claim 1, wherein a source of each MOS transistor forming a current source of the output buffer is connected to a power supply terminal of the second power supply via a resistor. Output buffer. 4. A transistor other than at least the first-stage drive transistor of the plurality of source follower circuits is formed in a well electrically separated from the ground, and the well is connected to a power supply terminal of a second power supply. 4. An output buffer for a CCD solid-state imaging device according to claim 1, wherein 5. The output buffer of a CCD solid-state imaging device according to claim 1, wherein an independent power supply different from a transfer driving power supply of the charge transfer unit is used as the second power supply.