JPH11307895A - Wiring board - Google Patents

Wiring board

Info

Publication number
JPH11307895A
JPH11307895A JP11694198A JP11694198A JPH11307895A JP H11307895 A JPH11307895 A JP H11307895A JP 11694198 A JP11694198 A JP 11694198A JP 11694198 A JP11694198 A JP 11694198A JP H11307895 A JPH11307895 A JP H11307895A
Authority
JP
Japan
Prior art keywords
circuit wiring
wiring
brazing material
melting point
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11694198A
Other languages
Japanese (ja)
Inventor
Mitsuhiko Nozuma
光彦 野妻
Takaaki Fujioka
孝昭 藤岡
Yuichiro Yamaguchi
雄一朗 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP11694198A priority Critical patent/JPH11307895A/en
Publication of JPH11307895A publication Critical patent/JPH11307895A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To make it possible to securely and electrically connect a semiconductor and the like to a circuit wiring through low melting point solder. SOLUTION: A wiring board comprises a circuit wiring 2 having a main conductive layer 5 comprising gold formed on the surface formed on an insulation substrate 1 by means of a thin film forming technology and on which an electronic component A is connected through solder material. A 10 to 1500- nm-thick barrier layer 6 comprising platinum or rhodium is formed covering at least a region of the circuit wiring 2 to which the electronic component A is connected through the solder material 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は配線基板に関し、よ
り詳細には混成集積回路装置や半導体素子を収容する半
導体素子収納用パッケージ等に使用される配線基板に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, and more particularly to a wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing a semiconductor element, and the like.

【0002】[0002]

【従来の技術】従来、例えば半導体素子等の能動部品や
容量素子、抵抗器等の受動部品を多数搭載し、所定の電
子回路を構成するようになした混成集積回路装置は、通
常、酸化アルミニウム質焼結体から成る絶縁基体の内部
及び表面にタングステン、モリブデン等の高融点金属材
料から成る回路配線を形成した構造の配線基板を準備
し、該配線基板の絶縁基体上面に半導体素子や容量素
子、抵抗器等を搭載取着するとともに該半導体素子等の
電極を前記回路配線に電気的に接続することによって形
成されている。
2. Description of the Related Art Conventionally, a hybrid integrated circuit device having a large number of active components such as a semiconductor device, a large number of passive components such as a capacitance device and a resistor, and constituting a predetermined electronic circuit is usually made of aluminum oxide. A wiring board having a structure in which circuit wiring made of a refractory metal material such as tungsten or molybdenum is formed inside and on the surface of an insulating substrate made of a porous sintered body, and a semiconductor element or a capacitor element is provided on the upper surface of the insulating substrate of the wiring substrate. , A resistor and the like are mounted, and the electrodes of the semiconductor element and the like are electrically connected to the circuit wiring.

【0003】かかる従来の混成集積回路装置等に使用さ
れる配線配線は一般に、セラミックスの積層技術及びス
クリーン印刷等の厚膜形成技術を採用することによって
製作されており、具体的には以下の方法によって製作さ
れる。
[0003] Wiring used in such conventional hybrid integrated circuit devices and the like is generally manufactured by employing a ceramic laminating technique and a thick film forming technique such as screen printing. Specifically, the following method is used. Produced by

【0004】即ち、 (1)まず、酸化アルミニウム(Al2 3 )、酸化珪
素(SiO2 )、酸化マグネシウム(MgO)、酸化カ
ルシウム(CaO)等から成るセラミックス原料粉末に
有機溶剤、溶媒を添加混合して泥漿物を作り、次にこれ
を従来周知のドクターブレード法やカレンダーロール法
等によりシート状に形成して複数枚のセラミックグリー
ンシート(セラミック生シート)を得る。そして各セラ
ミックグリーンシートに打ち抜き加工法及び孔あけ加工
法を施し所定位置に貫通孔を形成するとともに所定形状
に加工する。
[0004] (1) First, an organic solvent and a solvent are added to a ceramic raw material powder composed of aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), magnesium oxide (MgO), calcium oxide (CaO) and the like. The mixture is mixed to form a slurry, and then formed into a sheet by a conventionally known doctor blade method, calender roll method, or the like to obtain a plurality of ceramic green sheets (ceramic green sheets). Then, a punching method and a punching method are applied to each ceramic green sheet to form a through hole at a predetermined position and to process the ceramic green sheet into a predetermined shape.

【0005】(2)次に、前記セラミックグリーンシー
トの表面及び貫通孔内に、タングステンやモリブデン粉
末に有機溶剤、溶媒を添加混合して得た金属ペーストを
スクリーン印刷法により所定パターンに印刷塗布する。
(2) Next, a metal paste obtained by adding and mixing an organic solvent and a solvent to tungsten or molybdenum powder is printed and applied in a predetermined pattern on the surface of the ceramic green sheet and in the through holes by a screen printing method. .

【0006】(3)そして最後に前記金属ペーストを印
刷塗布した各セラミックグリーンシートを上下に積層す
るとともに還元雰囲気中、約1600℃の温度で焼成
し、セラミックグリーンシートと金属ペーストとを焼結
一体化することによって絶縁基体の内部及び表面に所定
パターンの回路基板を形成した配線基板が完成する。し
かしながら、この従来の配線基板においては、回路基板
が全て金属ペーストをスクリーン印刷することによって
形成されており、スクリーン印刷による回路配線の形成
は微細化が困難で、回路配線を高密度に形成することが
できないという欠点を有していた。
(3) Finally, the ceramic green sheets on which the metal paste is applied by printing are stacked one on top of the other and fired at a temperature of about 1600 ° C. in a reducing atmosphere, whereby the ceramic green sheets and the metal paste are sintered integrally. This completes a wiring board in which a circuit board of a predetermined pattern is formed inside and on the surface of the insulating base. However, in this conventional wiring board, the circuit board is entirely formed by screen-printing a metal paste, and it is difficult to form the circuit wiring by screen printing, and it is difficult to form the circuit wiring at a high density. Had the drawback that it could not be done.

【0007】そこで上記欠点を解消するために回路配線
を従来のスクリーン印刷等の厚膜形成技術に変えて微細
化が可能な薄膜形成技術を用いて形成する配線基板が提
案されている。
In order to solve the above-mentioned drawbacks, there has been proposed a wiring board in which circuit wiring is formed by using a thin film forming technique capable of miniaturization instead of a conventional thick film forming technique such as screen printing.

【0008】かかる回路配線を薄膜形成技術により形成
した配線基板は、酸化アルミニウム質焼結体等の電気絶
縁性の材料から成る絶縁基体の表面に、例えば、チタン
からから成る接着層と、金から成る主導体層とをイオン
プレーティング法やスパッタリング法、蒸着法等の薄膜
形成技術により層着し、しかる後、これらの層をフォト
リソグラフィー技術を採用し、所定パターンに加工して
回路配線とすることによって形成されている。
[0008] A circuit board in which such circuit wiring is formed by a thin film forming technique is composed of an insulating layer made of an electrically insulating material such as an aluminum oxide sintered body, and an adhesive layer made of, for example, titanium and a gold made of gold. The main conductor layer is formed by a thin film forming technique such as an ion plating method, a sputtering method, and an evaporation method, and thereafter, these layers are processed into a predetermined pattern by using a photolithography technique to form a circuit wiring. It is formed by.

【0009】なお、前記チタンから成る接着層は回路配
線を絶縁基体に強固に接着させる作用をなし、また金か
ら成る主導体層は電気信号を伝搬させるための伝搬路と
して作用する。
The adhesive layer made of titanium serves to firmly adhere the circuit wiring to the insulating base, and the main conductor layer made of gold serves as a propagation path for transmitting electric signals.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、この配
線基板は、絶縁基体表面に形成された回路配線に半導体
素子や容量素子、抵抗器等の電極を半田等の低融点ロウ
材を介して接続させる際、低融点ロウ材を溶融させる熱
が回路配線に印加されると該回路配線の主導体層を形成
している金が低融点ロウ材中に拡散して低融点ロウ材の
融点を高くしてしまい、その結果、低融点ロウ材の溶融
が不完全となり、絶縁基体表面に形成された回路配線に
半導体素子や容量素子、抵抗器等の電極を低融点ロウ材
を介して確実、強固に電気的接続させることがことでき
ないとう欠点を有していた。
However, in this wiring board, electrodes such as a semiconductor element, a capacitor element, and a resistor are connected to circuit wiring formed on the surface of the insulating base via a low melting point brazing material such as solder. When heat for melting the low melting point brazing material is applied to the circuit wiring, gold forming the main conductor layer of the circuit wiring diffuses into the low melting point brazing material to increase the melting point of the low melting point brazing material. As a result, the melting of the low melting point brazing material becomes incomplete, and the electrodes such as semiconductor elements, capacitance elements, and resistors are securely and firmly connected to the circuit wiring formed on the surface of the insulating base through the low melting point brazing material. It has a drawback that it cannot be electrically connected.

【0011】本発明は上記欠点に鑑み案出されたもの
で、その目的は回路配線を薄膜形成技術により形成し、
回路配線を高密度に形成するのを可能とするとともに、
回路配線に低融点ロウ材を介して半導体素子や容量素
子、抵抗器等の電極を確実、強固に電気的接続させるこ
とが配線基板を提供することにある。
The present invention has been made in view of the above-mentioned drawbacks, and has as its object to form circuit wiring by a thin film forming technique,
While enabling high-density circuit wiring,
It is an object of the present invention to provide a wiring board for reliably and firmly electrically connecting electrodes of a semiconductor element, a capacitor element, a resistor, and the like to circuit wiring via a low melting point brazing material.

【0012】[0012]

【課題を解決するための手段】本発明は、絶縁基体上
に、薄膜形成技術によって形成され、電子部品がロウ材
を介して接合される表面に金から成る主導体層を有する
回路配線を形成した配線基板であって、前記回路配線の
うち少なくとも電子部品がロウ材を介して接合される領
域に白金もしくはロジウムから成る厚さが10nm乃至
1500nmのバリア層を被着形成したことを特徴とす
るものである。
According to the present invention, a circuit wiring is formed on an insulating substrate by a thin film forming technique and has a main conductor layer made of gold on a surface to which electronic components are joined via a brazing material. Wherein a barrier layer made of platinum or rhodium and having a thickness of 10 nm to 1500 nm is applied to at least a region of the circuit wiring to which an electronic component is joined via a brazing material. Things.

【0013】本発明の配線基板によれば、絶縁基体上に
薄膜形成技術によって回路配線を形成したことから回路
配線の微細化が可能となり、回路配線を極めて高密度に
形成することが可能になる。
According to the wiring board of the present invention, since the circuit wiring is formed on the insulating base by the thin film forming technique, the circuit wiring can be miniaturized, and the circuit wiring can be formed at an extremely high density. .

【0014】また、本発明の配線基板は、回路配線のう
ち少なくとも電子部品がロウ材を介して接合される領域
に白金もしくはロジウムから成る厚さが10nm乃至1
500nmのバリア層を被着形成したことから回路配線
に半田等の低融点ロウ材を介して半導体素子や容量素
子、抵抗器等の電極を接続する際、回路配線の主導体層
を形成する金が低融点ロウ材中に拡散し、低融点ロウ材
の融点を高くすることはなく、その結果、低融点ロウ材
の溶融を完全として、半導体素子や容量素子、抵抗器等
の電極を回路配線に確実、強固に電気的接続することが
可能となる。
In the wiring board of the present invention, at least a region made of platinum or rhodium and having a thickness of 10 nm to 1 nm is formed at least in a region of the circuit wiring where an electronic component is joined via a brazing material.
When a 500 nm barrier layer is formed and adhered, when connecting electrodes such as semiconductor elements, capacitors, resistors and the like to circuit wiring via low melting point brazing material such as solder, gold forming the main conductor layer of circuit wiring is used. Does not diffuse into the low melting point brazing material, and does not increase the melting point of the low melting point brazing material. As a result, the melting of the low melting point brazing material is completed, and the electrodes of semiconductor elements, capacitors, resistors, etc. In this way, it is possible to reliably and firmly make an electrical connection.

【0015】[0015]

【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図1は、本発明の配線基板の一実施例
を示し、1は絶縁基体、2は回路配線である。
Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of the wiring board of the present invention, wherein 1 is an insulating base, and 2 is a circuit wiring.

【0016】前記絶縁基体1は酸化アルミニウム質焼結
体、ムライト質焼結体、表面に酸化物膜を有する窒化ア
ルミニウム質焼結体や炭化珪素質焼結体、ガラスセラミ
ック焼結体、サファイア、ガラス、石英、シリコン基板
等の電気絶縁性の材料から成り、例えば、酸化アルミニ
ウム質焼結体で形成されている場合には、酸化アルミニ
ウム、酸化珪素、酸化マグネシウム、酸化カルシウム等
の粉末原料に適当な有機溶剤、溶媒を添加混合して泥漿
状となすとともにこれを従来周知のドクターブレード法
やカレンダーロール法を採用することによってセラミッ
クグリーンシート(セラミック生シート)を形成し、し
かる後、前記セラミックグリーンシートに適当な打ち抜
き加工を施し、所定形状となすとともに高温(約160
0℃)で焼成することによって、或いは酸化アルミニウ
ム等の原料粉末に適当な有機溶剤、溶媒を添加混合して
原料粉末を調整するとともに該原料粉末をプレス成型機
によって所定形状に成形し、最後に前記形成体を約16
00℃の温度で焼成することによって製作される。
The insulating substrate 1 is made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body having an oxide film on its surface, a silicon carbide sintered body, a glass ceramic sintered body, sapphire, It is made of an electrically insulating material such as glass, quartz, or a silicon substrate. For example, when formed of an aluminum oxide-based sintered body, it is suitable for powdered materials such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide. A ceramic green sheet (green ceramic sheet) is formed by adding a suitable organic solvent and a solvent to form a slurry and employing a conventionally known doctor blade method or calender roll method. The sheet is subjected to an appropriate punching process to obtain a predetermined shape and a high temperature (about 160
0 ° C.) or by mixing a raw material powder such as aluminum oxide with a suitable organic solvent and a solvent to prepare the raw material powder and form the raw material powder into a predetermined shape by a press molding machine. About 16
It is manufactured by firing at a temperature of 00 ° C.

【0017】また前記絶縁基体1の上面には回路配線2
が薄膜形成技術によって被着形成されており、該回路配
線2は例えば、接着層3と、中間層4と、主導体層5の
3層構造を有している。
A circuit wiring 2 is provided on the upper surface of the insulating base 1.
The circuit wiring 2 has, for example, a three-layer structure of an adhesive layer 3, an intermediate layer 4, and a main conductor layer 5.

【0018】前記回路配線2の接着層3はチタン(T
i)、クロム(Cr)、ニッケルクロム合金(Ni−C
r)、タンタル(Ta)等から成り、蒸着法やイオンプ
レーティング法、スパッタリング法等の薄膜形成技術を
採用することにより絶縁基体1上に被着される。
The adhesive layer 3 of the circuit wiring 2 is made of titanium (T
i), chromium (Cr), nickel-chromium alloy (Ni-C
r), tantalum (Ta) or the like, and is deposited on the insulating substrate 1 by employing a thin film forming technique such as an evaporation method, an ion plating method, and a sputtering method.

【0019】前記接着層3は絶縁基体1と回路配線2と
の接合強度を上げる作用を為し、その厚みは0.05μ
m未満であると回路配線2を絶縁基体1に強固に接合さ
せるのが困難となる傾向にあり、また0.5μmを超え
ると接着層3を薄膜形成技術により形成する際に大きな
応力が発生するとともにこれが内部に内在し、該内在応
力によって絶縁基体1と接着層3との接合強度が低下し
てしまう傾向にある。
The adhesive layer 3 has the function of increasing the bonding strength between the insulating substrate 1 and the circuit wiring 2 and has a thickness of 0.05 μm.
If it is less than m, it tends to be difficult to firmly join the circuit wiring 2 to the insulating base 1, and if it exceeds 0.5 μm, a large stress is generated when the adhesive layer 3 is formed by the thin film forming technique. At the same time, this is present inside, and the inherent stress tends to reduce the bonding strength between the insulating base 1 and the adhesive layer 3.

【0020】従って、チタン等から成る接着層3はその
厚みを0.05μm〜0.5μmの範囲とすることが好
ましく、好適には0.1μm〜0.3μmの範囲とする
のがよい。
Therefore, the thickness of the adhesive layer 3 made of titanium or the like is preferably in the range of 0.05 μm to 0.5 μm, and more preferably in the range of 0.1 μm to 0.3 μm.

【0021】また前記接着層3の上面には中間層4が被
着されており、該中間層4は接着層3と主導体層5とを
強固に接合させるとともに接着層3と主導体層5との相
互拡散を防止する作用をなす。
On the upper surface of the adhesive layer 3, an intermediate layer 4 is adhered. The intermediate layer 4 firmly joins the adhesive layer 3 and the main conductor layer 5 while simultaneously bonding the adhesive layer 3 and the main conductor layer 5 to each other. And acts to prevent mutual diffusion.

【0022】前記中間層4は白金(Pt)、パラジウム
(Pd)、チタンタングステン(Ti−W)、ニッケル
−クロム(Ni−Cr)等から成り、蒸着法やイオンプ
レーティング法、スパッタリング法等の薄膜形成技術に
より接着層3の上面に被着される。
The intermediate layer 4 is made of platinum (Pt), palladium (Pd), titanium tungsten (Ti-W), nickel-chromium (Ni-Cr), or the like, and is formed by vapor deposition, ion plating, sputtering, or the like. It is applied on the upper surface of the adhesive layer 3 by a thin film forming technique.

【0023】前記中間層4はその厚みが0.05μm未
満であると接着層3と主導体層5との相互拡散を有効に
防止することができなくなる傾向にあり、また2.0μ
mを超えると中間層4を薄膜形成技術により被着させる
際に発生する応力によって接着層3と中間層4との接合
強度が低下してしまう傾向にある。従って、白金やニッ
ケルークロム等から成る中間層4はその厚みを0.05
μm〜2.0μmの範囲とすることが好ましく、好適に
は0.1μm〜1.0μmの範囲がよい。更に前記中間
層4の上面には主導体層5が蒸着法やイオンプレーティ
ング法、スパッタリング法等の薄膜形成技術により被着
されており、該主導体層5は主として電気信号を通す通
路として作用する。
If the thickness of the intermediate layer 4 is less than 0.05 μm, the interdiffusion between the adhesive layer 3 and the main conductor layer 5 tends to be unable to be effectively prevented.
If it exceeds m, the bonding strength between the adhesive layer 3 and the intermediate layer 4 tends to decrease due to the stress generated when the intermediate layer 4 is applied by the thin film forming technique. Therefore, the thickness of the intermediate layer 4 made of platinum, nickel-chromium, etc. is 0.05
The range is preferably from μm to 2.0 μm, and more preferably from 0.1 μm to 1.0 μm. Further, a main conductor layer 5 is applied on the upper surface of the intermediate layer 4 by a thin film forming technique such as a vapor deposition method, an ion plating method, and a sputtering method, and the main conductor layer 5 mainly functions as a passage for passing an electric signal. I do.

【0024】前記主導体層5は導通抵抗が極めて低い金
(Au)が使用され、その厚みは2.0μm未満である
と回路配線2の導通抵抗が高くなって配線基板としては
不向きとなる傾向にある。従って、前記金から成る主導
体層5はその厚みを2.0μm以上とすることが好まし
く、コストの点も考慮すると3.0μm〜7.0μmも
範囲が好適である。
The main conductor layer 5 is made of gold (Au) having an extremely low conduction resistance, and if its thickness is less than 2.0 μm, the conduction resistance of the circuit wiring 2 is high, and it tends to be unsuitable as a wiring board. It is in. Therefore, it is preferable that the thickness of the main conductor layer 5 made of gold is 2.0 μm or more, and a range of 3.0 μm to 7.0 μm is also preferable in consideration of cost.

【0025】前記絶縁基体1の上面にチタン等から成る
接着層3と白金やニッケル−クロム等から成る中間層4
と金から成る主導体層5の3層構造を有する回路配線2
を設けた配線基板は回路配線2を形成する接着層3、中
間層4及び主導体層5を各々が薄膜形成技術を採用する
ことによって形成されていることから回路配線2を極め
て微細に形成することが可能となり、これによって絶縁
基体1上に回路配線2を高密度に形成することができ
る。
An adhesive layer 3 made of titanium or the like and an intermediate layer 4 made of platinum or nickel-chromium on the upper surface of the insulating base 1.
Wiring 2 having a three-layer structure of main conductor layer 5 made of gold and gold
In the wiring board provided with the circuit wiring 2, the adhesive layer 3, the intermediate layer 4, and the main conductor layer 5 forming the circuit wiring 2 are each formed by employing the thin film forming technique, so that the circuit wiring 2 is formed extremely finely. This makes it possible to form the circuit wirings 2 on the insulating base 1 with high density.

【0026】また前記回路配線2はチタン等から成る接
着層3と金から成る主導体層5の間に両者に対し接合性
がよい白金やニッケル−クロム等から成る中間層4を配
したことから接着層3と主導体層5とは強固に接合し、
同時に回路配線2に半導体素子や容量素子、抵抗器記等
の電子部品Aを半田等の低融点ロウ材7を介して接続さ
せた場合、低融点ロウ材7を溶融させる熱が回路配線2
に印加され、接着層3と主導体層5との間に相互拡散が
起ころうとしてもその相互拡散は前記中間層4によって
有効に防止され、回路配線2の絶縁基体1への接合を強
固となすこともできる。
The circuit wiring 2 has an intermediate layer 4 made of platinum, nickel-chromium, or the like, which has good bonding properties between the adhesive layer 3 made of titanium or the like and the main conductor layer 5 made of gold. The bonding layer 3 and the main conductor layer 5 are firmly joined,
At the same time, when an electronic component A such as a semiconductor element, a capacitance element, and a resistor is connected to the circuit wiring 2 via a low melting point brazing material 7 such as solder, heat for melting the low melting point brazing material 7 is generated by the circuit wiring 2.
, And even if mutual diffusion between the adhesive layer 3 and the main conductor layer 5 is to occur, the mutual diffusion is effectively prevented by the intermediate layer 4, and the bonding of the circuit wiring 2 to the insulating base 1 is strengthened. You can do it.

【0027】更に前記回路配線2はその表面で少なくと
も電子部品Aがロウ材を介して接合される領域に白金
(Pt)もしくはロジウム(Rh)から成るバリア層6
が被着形成されている。
Further, the circuit wiring 2 has a barrier layer 6 made of platinum (Pt) or rhodium (Rh) at least in a region where the electronic component A is joined via a brazing material on the surface thereof.
Are formed.

【0028】前記バリア層6は回路配線2に半導体素子
や容量素子、抵抗器等電子部品Aの電極を半田等の低融
点ロウ材7を介して接続させる際、回路配線2の主導体
層5を形成する金(Au)が低融点ロウ材7中に拡散
し、低融点ロウ材7の融点を高くするのを有効に防止す
る作用をなし、これによって低融点ロウ材7は所定の低
い温度で完全に溶融し、半導体素子や容量素子、抵抗器
等の電子部品Aの電極を回路配線2に確実、強固に電気
的接続することができる。
The barrier layer 6 is used to connect the electrodes of the electronic component A such as semiconductor elements, capacitors, resistors and the like to the circuit wiring 2 via a low melting point brazing material 7 such as solder. Is effectively diffused into the low-melting brazing material 7 to effectively prevent the melting point of the low-melting brazing material 7 from being increased, whereby the low-melting brazing material 7 has a predetermined low temperature. Thus, the electrodes of the electronic component A such as a semiconductor element, a capacitance element, and a resistor can be securely and firmly electrically connected to the circuit wiring 2.

【0029】前記白金(Pt)またはロジウム(Rh)
から成バリア層6は、蒸着法やイオンプレーティング
法、スパッタリング法等の従来周知の薄膜配線技術を採
用することによって主導体層3の上面に厚みが10nm
乃至1500nmに被着される。
The above platinum (Pt) or rhodium (Rh)
The barrier layer 6 has a thickness of 10 nm on the upper surface of the main conductor layer 3 by employing a conventionally known thin-film wiring technique such as an evaporation method, an ion plating method, and a sputtering method.
~ 1500 nm.

【0030】なお、前記バリア層6はその厚みが10n
m未満となると回路配線2に半導体素子や容量素子等電
子部品Aの電極を半田等の低融点ロウ材7を介して接続
する際、回路回線2の主導体層5を形成する金(Au)
が低融点ロウ材7中に拡散するのを有効に防止すること
ができず、また1500nmを超えるとバリア層6を薄
膜形成技術により形成する際に大きな内在応力が発生
し、該内在応力がバリア層6内部に内在することによっ
て主導体層3との接合強度が低下してしまう。従って、
白金またはロジウムから成るバリア層6はその厚みが1
0nm乃至1500nmの範囲に限定される。
The barrier layer 6 has a thickness of 10 n.
When it is less than m, gold (Au) forming the main conductor layer 5 of the circuit line 2 when connecting the electrodes of the electronic component A such as a semiconductor element and a capacitor to the circuit wiring 2 via the low melting point brazing material 7 such as solder.
Cannot be effectively prevented from diffusing into the low melting point brazing material 7, and if it exceeds 1500 nm, a large intrinsic stress is generated when the barrier layer 6 is formed by the thin film forming technique, and the intrinsic stress is By being present inside the layer 6, the bonding strength with the main conductor layer 3 is reduced. Therefore,
The barrier layer 6 made of platinum or rhodium has a thickness of 1
It is limited to the range of 0 nm to 1500 nm.

【0031】かくして、本発明の配線基板によれば、絶
縁基体1に形成された回路配線2に半導体素子や容量素
子、抵抗器等の電子部品Aの電極を半田等の低融点ロウ
材7を介して接続させ、電子部品Aの電極を回路配線2
に電気的に接続させることによって半導体装置や混成集
積回路装置となり、回路配線2の一部を外部電気回路に
接続させれば前記電子部品Aが外部電気回路に電気的に
接続されることとなる。
Thus, according to the wiring board of the present invention, the electrodes of the electronic component A such as a semiconductor element, a capacitance element, and a resistor are provided on the circuit wiring 2 formed on the insulating base 1 with the low melting point brazing material 7 such as solder. To connect the electrodes of the electronic component A to the circuit wiring 2
The electronic component A is electrically connected to an external electric circuit if a part of the circuit wiring 2 is connected to an external electric circuit by electrically connecting the electronic component A to a semiconductor device or a hybrid integrated circuit device. .

【0032】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例におい
ては絶縁基体1の上面のみに配線回路2を被着させた
が、配線回路2を絶縁基体1の下面側のみに設けても、
上下の両主面に設けてもよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. Although the wiring circuit 2 is attached only to the upper surface of the insulating substrate 1, even if the wiring circuit 2 is provided only on the lower surface side of the insulating base 1,
It may be provided on both upper and lower main surfaces.

【0033】[0033]

【発明の効果】本発明の配線基板によれば、絶縁基体上
に薄膜形成技術によって回路配線を形成したことから回
路配線の微細化が可能となり、回路配線を極めて高密度
に形成することが可能になる。
According to the wiring board of the present invention, since the circuit wiring is formed on the insulating base by the thin film forming technique, the circuit wiring can be miniaturized, and the circuit wiring can be formed at an extremely high density. become.

【0034】また、本発明の配線基板は、回路配線のう
ち少なくとも電子部品がロウ材を介して接合される領域
に白金もしくはロジウムから成る厚さが10nm乃至1
500nmのバリア層を被着形成したことから回路配線
に半田等の低融点ロウ材を介して半導体素子や容量素
子、抵抗器等の電極を接続する際、回路配線の主導体層
を形成する金が低融点ロウ材中に拡散し、低融点ロウ材
の融点を高くすることはなく、その結果、低融点ロウ材
の溶融を完全として、半導体素子や容量素子、抵抗器等
の電極を回路配線に確実、強固に電気的接続することが
可能となる。
In the wiring board of the present invention, at least a region made of platinum or rhodium having a thickness of 10 nm to 1 nm is formed at least in a region of the circuit wiring to which the electronic component is joined via the brazing material.
When a 500 nm barrier layer is formed and adhered, when connecting electrodes such as semiconductor elements, capacitors, resistors and the like to circuit wiring via low melting point brazing material such as solder, gold forming the main conductor layer of circuit wiring is used. Does not diffuse into the low melting point brazing material, and does not increase the melting point of the low melting point brazing material. As a result, the melting of the low melting point brazing material is completed, and the electrodes of semiconductor elements, capacitors, resistors, etc. In this way, it is possible to reliably and firmly make an electrical connection.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の一実施例を示す断面図であ
る。
FIG. 1 is a sectional view showing one embodiment of a wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・絶縁基体 2・・・回路配線 3・・・接着層 4・・・中間層 5・・・主導体層 6・・・バリア層 7・・・低融点ロウ材 A・・・電子部品 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Circuit wiring 3 ... Adhesive layer 4 ... Intermediate layer 5 ... Main conductor layer 6 ... Barrier layer 7 ... Low melting point brazing material A ... Electronics parts

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基体上に、薄膜形成技術によって形成
され、電子部品がロウ材を介して接合される表面に金か
ら成る主導体層を有する回路配線を形成した配線基板で
あって、前記回路配線のうち少なくとも電子部品がロウ
材を介して接合される領域に白金もしくはロジウムから
成る厚さが10nm乃至1500nmのバリア層を被着
形成したことを特徴とする配線基板。
1. A wiring board formed on an insulating base by a thin film forming technique and having a circuit wiring having a main conductor layer made of gold on a surface to which an electronic component is joined via a brazing material, A wiring substrate, characterized in that a barrier layer made of platinum or rhodium and having a thickness of 10 nm to 1500 nm is formed on at least a region of a circuit wiring to which an electronic component is joined via a brazing material.
JP11694198A 1998-04-27 1998-04-27 Wiring board Pending JPH11307895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11694198A JPH11307895A (en) 1998-04-27 1998-04-27 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11694198A JPH11307895A (en) 1998-04-27 1998-04-27 Wiring board

Publications (1)

Publication Number Publication Date
JPH11307895A true JPH11307895A (en) 1999-11-05

Family

ID=14699513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11694198A Pending JPH11307895A (en) 1998-04-27 1998-04-27 Wiring board

Country Status (1)

Country Link
JP (1) JPH11307895A (en)

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