JPH11307677A - Wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of electrical connection by a flip-chip connection by setting the size and number of voids existing on the outermost surface of an Sn-plated layer on a flip connection type wiring board to be within a specified range. SOLUTION: This wiring board has an electrode pad group 11 for electrically connecting an integrated circuit chip of a flip-chip connection type and an Sn-plated layer 6 on the outermost surface of a conductor layer to be each electrode pad 11, the number of voids having the longest diameter of 0.3 μm or larger existing on the surface of the Sn-plated layer 6 is set to 50 or less per 100 μm<2> or less, the thickness of the void-controlled Sn-plated layer 6 is set to a range of 1-6 μm. The wiring board uses a ceramics wiring board. the electrode pads 11 consist of a plurality of Ti4a-Cu4b-Au5b thin films and plated film having a Cu5a-Au-Sn6 multilayer structure. As a result, a flip-chip connection having good bond strength is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board,
More specifically, the present invention relates to a wiring board having an electrode pad group (a large number of electrode pads) for electrically connecting flip-chip connection type semiconductor integrated circuit chips.

[0002]

2. Description of the Related Art In recent years, as electronic devices become smaller and thinner and signal processing speeds increase rapidly, the mounting technology of semiconductor integrated circuit chips (hereinafter simply referred to as chips) determines the performance of products. Up to now. recently,
2. Description of the Related Art A chip size package (CSP) and a multi-chip module (MCM) using flip chip mounting in which a chip is directly bonded to a substrate without using a package have been actively developed.

[0003] Among the chip mounting methods, the flip chip connection method electrically connects a chip having an electrode (input / output connection terminal) pad at a predetermined position on one main surface to each electrode pad of a wiring board. This is a method that can realize high density in terms of mounting area and mounting height. Since the connection between the chip and the wiring board can be made with the shortest distance, and the inductance component can be reduced as compared with the wire bonding method, it is advantageous for speeding up the signal processing and increasing the frequency. In a computer MPU package, the flip-chip connection method is said to be an indispensable mounting method when the clock operating frequency is 300 MHz or higher. Specifically, it is widely used for a wiring board (hereinafter, also simply referred to as a board) such as a ball grid array (BGA), a pin grid array (PGA), and a land grid array (LGA).

[0004] Such a wiring board and its electrode pads (hereinafter, also simply referred to as pads) are manufactured as follows in the case of a ceramic thin film wiring board made of, for example, alumina ceramic. That is, after drilling a via hole penetrating the front and back surfaces of the alumina green sheet using a mold or the like, filling the via hole with a metallizing paste mainly composed of a high melting point metal powder such as tungsten or molybdenum, and firing simultaneously. Then, a substrate having via conductors for electrically connecting both surfaces of the substrate is obtained.

After polishing and flattening both surfaces of the obtained substrate, a thin film layer is formed on one principal surface of the substrate by sputtering. A photosensitive resist is applied on the thin film layer to form a resist film, and the pattern is removed by photolithography. A wiring layer is formed by electroplating on the pattern cutout. Thereafter, the remaining resist layer is peeled off, and the thin film layers other than the wiring layer are removed by etching to obtain a thin film pattern. The same operation is performed on the other main surface of the substrate. However, in order to ensure electrical conduction to the pattern on the other main surface, the etching is performed after the plating of the other main surface is completed. After forming the thin film pattern on the front and back surfaces in this way, a photosensitive resist is applied again to form a plating resist layer, and this time, a portion required for flip chip connection is selectively cut out. After electrolytic copper plating is applied to the pattern opening, electrolytic gold plating is thinly applied for rust prevention. Further, at the time of flip chip connection, after tin plating for forming a low melting point alloy with the gold bump on the chip side is performed, the plating resist is peeled off, and the formation of the electrode pad is completed.

In the assembly using the flip chip connection method, as shown in FIGS. 1 to 3, the gold bumps 33 formed on the electrode pads 11 of the wiring board 1 and the electrode pads 32 of the chip 31 are connected to each other. And heated using a reflow furnace or the like, so that the tin plating layer 6 on the outermost surface of the electrode pad 11 of the wiring board 1 is formed.
And gold bump 3 formed on electrode pad 32 of chip 31
3 form a low melting point alloy and are soldered to make electrical connection between the pads 11 and 32.

[Problems to be solved by the invention]

However, recently, the tin plating layer 6 on the outermost layer of the pad 11 of the wiring board 1 and the gold bump 33 formed on the pad 32 of the chip 31 form a low melting point alloy and are soldered. Nevertheless, it has been pointed out that a desired bonding strength cannot be obtained and there is a problem in reliability of electrical connection between the pads 11 and 32.

Under these circumstances, the inventors of the present invention consider that the cause of the insufficient flip-chip connection strength is that organic residues such as a residual resist on the surface of the tin plating layer 6 of the pad 11 on the wiring board 1 are influential. When the surface condition of the pad 11 of the product after the process was analyzed and examined, it was confirmed that many voids were present on the surface of the tin plating layer 6 as shown in FIG.

In the conventional method of forming a tin plating layer, the current density of tin plating is set to 0.5 to 0.8 A / dm in order to stabilize the variation in plating thickness on electrode pads having a small area of, for example, 50 μm in diameter. ²
This was performed only in a relatively low range. As a result, the surface state of the obtained tin plating was relatively porous, and many voids having a longest diameter of 0.3 μm or more were present. When the bonding force test of the chip shown in FIGS. 6 and 7 is performed, the breaking mode when a normal bonding is obtained is a mode in which the thinning gold-plated copper plating layer 5 on the substrate side breaks as shown in FIG. Alternatively, the breaking mode using a gold bump of 33a is a breaking mode when a conventional tin-plated product in a porous state is used. As shown in FIG. 8, the gold bump 33 on the chip side and the tin plating layer on the substrate side are used as shown in FIG. This was a mode of breaking near the bonding region with No. 6 and was a result suggesting that the surface state of the tin plating affected the bonding strength of the chip. As a cause of the deterioration of the bonding strength of the chip, as shown in FIG. 10, the resist is trapped in the void 7 on the surface of the tin plating layer 6 to become an organic residue 8, and the solder wettability at the time of subsequent chip connection is deteriorated. It was speculated. Therefore, the inventors of the present invention changed the conditions of the tin plating process to produce samples in which the surface condition of the tin plating layer 6 was variously changed, and connected the chips to the samples by flip-chip bonding, repeatedly performed the bonding strength test, and performed the bonding. As a result of investigating the correlation between the strength and the surface state of the tin plating layer 6, when the dimensions and the number of the voids 7 existing on the surface of the tin plating layer 6 are set within a predetermined range, the bonding strength of the flip chip connection is reduced. I found that it can be significantly improved.

The present invention has been made on the basis of such knowledge, and it is an object of the present invention to provide a flip-chip connection type wiring board in which the outermost surface of a conductor layer forming an electrode pad is tin-plated. A wiring board capable of improving the reliability of electrical connection by flip-chip connection by setting the size and the number of voids present on the outermost surface of the tin plating layer within a predetermined range. It is in.

[0011]

According to the present invention, there is provided an electrode pad group for electrically connecting flip-chip connection type integrated circuit chips. In a wiring board having a tin plating layer on the outermost layer of a conductor layer, the number of voids having a longest diameter of 0.3 μm or more on the surface of the tin plating layer is set to 50 or less per 100 μm ^2. is there.

The dimensions of the above-mentioned electrode pads are usually small, such as 30 to 100 μm in diameter, and in particular, those having a diameter of about 50 μm are often used.
In the tin plating on the electrode pad having such a small area, even if there is a void which is not affected by a relatively large area pad having a diameter of 100 μm or more, for example, the solderability is deteriorated in the small area. The effect of doing so. This causes a deterioration in bonding strength between the gold bumps of the chip and the tin plating on the electrode pads of the substrate in flip chip connection. In order to obtain a stable bonding strength even in the case of an electrode pad having a small area, it is essential to control the quantity and quality of voids present on the surface of the tin plating layer more severely than in the normal case. In particular, the number of voids having the longest diameter of 0.3 μm or more is set to 100 μm ²
It is effective to reduce the number to 50 or less in order to obtain stable bonding strength. FIG. 5 shows a specific state of the surface of tin plating for obtaining good results.

Although the cause of the voids on the tin plating deteriorating the bonding strength of the flip chip connection is not necessarily clear, organic residues such as resist material trapped in the voids 7 on the surface 6a of the tin plating layer 6 as shown in FIG. 8
Is presumed to be the cause. The following are experimental data showing the basis. That is, the present inventors changed the conditions of the tin plating process to produce samples in which the surface condition of the tin plating layer 6 was variously changed, and connected the chips to the samples by flip chip bonding. As a result of investigating the correlation between the strength and the surface condition of the tin plating layer 6, when the size and the number of voids 7 existing on the surface 6 a of the tin plating layer 6 were set within a predetermined range, the bonding strength of the flip chip connection was determined. Was found to be significantly improved. In addition, for each surface state of the tin plating, the contents of tin, oxygen and carbon near the surface were analyzed by Auger electron analysis. As a result, the total of the atomic percentages of the three components tin, oxygen and carbon near the surface of the tin plating was 100%.
When the ratio of the atomic% of carbon to the atomic% of tin detected near the surface of the tin plating was 0.5 or less, excellent chip bonding strength was exhibited. This suggests that the adhesion of the organic substance near the tin-plated surface has a great effect on the chip bonding strength, and presumed that the point where the organic substance adheres is the void 7 on the tin-plated surface 6a.

By the way, the term "near the surface" as used herein means:
50 Å from the tin-plated surface (0.005
μm) and refers to a range of depths at which knowledge can be obtained by surface analysis using an Auger analyzer.
In effect, when the void diameter is 0.3 μm, it is considered that the organic residue is deeper than “near the surface”, that is, the organic residue is deeper than 50 Å from the tin-plated surface. The invention was defined using analytical results down to the surface and depth detectable by Auger analysis. This is because in flip-chip connection, the surface condition of the electrode pad has the greatest influence on connection reliability such as bonding strength.

The thickness of the tin plating with controlled voids is preferably in the range of 1 to 6 μm, particularly preferably 2 to 4 μm. Tin plating thickness 1μm
In the following, it is difficult to control voids on the plating. If the thickness of the tin plating is 6 μm or more, the stress of the plating film becomes large, which causes a decrease in the adhesion of the conductive thin film on the substrate side.

As the wiring board, a ceramic wiring board using a thin film or a thick film can be used. Although the material of the ceramic is not particularly limited, alumina, aluminum nitride, a ceramic-glass composite material in which a ceramic filler is added to glass (a so-called glass ceramic or low-temperature firing material), various dielectric materials, silicon carbide or silicon nitride Can be used.

In the ceramic thin film wiring board, as a wiring which becomes a base for tin plating of an electrode pad, a thin film conductor composed of three layers of titanium-copper-gold is formed in order from the substrate surface.
Those plated with two layers of copper and gold in this order from the thin film surface can be used. The layer structure of the thin film conductor in the present application is not limited to the three-layer structure of titanium-copper-gold, and any thin film having a layer structure capable of obtaining a chemical bonding force with the ceramic substrate can be used. It is. Similarly, the configuration of the underlying plating layer of the tin plating layer in the present application is not limited to the two-layer structure of copper-gold, but may be any combination such as only copper or copper-palladium.

Alternatively, a single-plate or multilayer ceramic thick-film wiring board can be used as the wiring board. In the case of a ceramic thick film wiring board, as a wiring to be a base for tin plating of an electrode pad, nickel is formed on a thick film conductor made of at least one metal of copper, silver, platinum, palladium, and gold in order from the thick film surface. -It is possible to use one plated with two layers of gold. The configuration of the plating layer underlying the tin plating layer in the present application is not limited to the two-layer structure of nickel-gold, but only nickel, nickel-palladium, nickel-copper, and nickel-gold.
Any combination such as copper-palladium or nickel-copper-gold is possible. Since noble metal-based thick film materials have low solder resistance except for palladium and platinum, it is preferable to apply nickel plating having high solder resistance to the first layer of plating. Nickel plating also includes Ni alloy plating such as Ni-B plating, Ni-P plating, and Ni-Co plating.

Further, a printed wiring board mainly composed of a heat-resistant resin such as BT (bismaleimide-triazine) or epoxy can be used as the wiring board. As a wiring serving as a base for tin plating of the electrode pad, a wiring formed by plating three layers of copper, nickel and gold in this order from the substrate surface can be used. The configuration of the plating layer underlying the tin plating layer in the present application is not limited to the three-layer structure of copper-nickel-gold, but may be copper-nickel-gold.
Any combination such as nickel-palladium or copper-nickel is possible. Incidentally, although copper has higher solder resistance than silver or gold, it is preferable to apply nickel plating having high solder resistance on copper as well. Nickel plating also includes Ni alloy plating such as Ni-B plating, Ni-P plating, and Ni-Co plating.

In forming the tin plating layer of the wiring board of the present invention, the current density applied to the tin plating bath is preferably set to 0.8 to 3.0 A / dm ² . When the current density is 0.8 A / dm ² or less, many voids are generated on the surface of the tin plating layer, and the reliability of flip-chip connection is reduced. On the other hand, when the current density is 3.0 A / dm ² or more, no void is generated on the surface of the tin plating layer.
Instead, abnormal growth of tin plating occurs, and a large number of projections such as bumps are generated on the tin plating surface. The use of such a current density is not preferable because the projections deteriorate the quality of the tin plating film.
If tin plating is performed at a current density in this range, the plating film becomes dense, the occurrence of voids and projections due to abnormal growth is suppressed, and organic residues such as resist hardly remain on the tin plating surface.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples. Production of ceramic thin film wiring board Using a well-known doctor blade method, a thickness of 480 μm was used.
m alumina green sheets are prepared. A via hole having a diameter of 150 μm is formed in the alumina green sheet using a mold according to a predetermined pattern. After filling the via hole with a metallized paste containing a tungsten powder as a conductive component, it is simultaneously fired at 1500 ° C. to obtain a ceramic substrate having a via conductor for electrically connecting both surfaces of the substrate.

After polishing and flattening both surfaces of the obtained ceramic substrate, a thin film layer having a two-layer structure was formed on the entire main surface of the substrate by sputtering in the order of titanium and palladium. A photosensitive resist was applied on the thin film layer using a spin coater to form a resist film. Using a glass mask representing the pattern of the wiring substrate including the surface mounting pattern, the substrate was exposed to ultraviolet light and exposed and developed to form a predetermined surface mounting pattern. A wiring layer is formed by electrolytic gold plating on the pattern cutout. Thereafter, the remaining resist layer is peeled off, and a thin film layer other than the wiring layer is etched and removed to obtain a desired thin film wiring pattern for surface mounting. This is performed after the electrolytic plating of one main surface is completed.

Similarly, for the other main surface of the substrate,
A thin film layer having a two-layer structure was formed on the whole by sputtering in the order of titanium and copper. A photosensitive resist was applied on the thin film layer using a spin coater to form a resist film. Using a glass mask representing the pattern of the wiring substrate including the surface mounting pattern, the substrate was exposed to ultraviolet light and exposed and developed to form a predetermined surface mounting pattern. A wiring layer is formed by electrolytic plating on the pattern cut portion in the order of copper and gold. Thereafter, the remaining resist layer is stripped.

A photosensitive resist is applied again to form a plating resist layer, and is exposed and developed by irradiating ultraviolet light using a glass mask representing a pattern of an electrode pad for flip chip connection. Only the portions required for chip connection were selectively extracted. Then, after electrolytic copper plating was applied to the pattern opening with a thickness of 3 μm, electrolytic gold plating was applied with a thickness of 0.1 μm for rust prevention. Thereafter, the remaining resist was peeled off, and the thin film layers other than the wiring layer were removed by etching to obtain a desired thin film wiring pattern for surface mounting. Apply a photosensitive resist again to form a plating resist layer, and irradiate with ultraviolet light using a glass mask showing the pattern of the electrode pad for flip chip connection, perform exposure and development, and use it for flip chip connection. Only the required sites were selectively extracted. Further, a current density of 0.2
Tin plating was performed by shaking in the range of 5 to 3.5 A / dm ² . The tin plating solution contained 30 g / l of first tin sulfate, 105 ml / l of concentrated sulfuric acid, and 20 g / g of a brightener (trade name: Tinglo Costar Co., Ltd. (Japan Metal)).
The one adjusted by adding 1 was used. After tin plating, the plating resist was peeled off to complete the formation of the electrode pad.

Flip Chip Connection Step An alumina ceramic thin film wiring board having dimensions of 10 mm square × 1.0 mm thickness and 13 columns × 13 rows, ie, 169, in a 1.6 mm square electrode pad having a diameter of 50 μm is prepared. did. The dimensions are 2.0 mm square x 0.5 thickness
mm, gold bumps with a diameter of 58 μm
A silicon chip having 3 columns × 13 rows, that is, 169 silicon chips was prepared. The electrode pads of the thin-film wiring board and the gold bumps formed on the respective electrode pads of the silicon chip were overlapped so as to coincide with each other, and heated and joined through a reflow furnace at a maximum temperature of 350 ° C. × 5 minutes.

Flip-Chip Bonding Force Test After the thin-film wiring board connected by flip-chip bonding and fixing to a ceramic plate with an adhesive, the ceramic plate was fixed to a stage of a push gauge. A shear force is applied to the flip-chip connection from the side of the silicon chip using a push gauge, and the strength when a break occurs at the chip connection and the fracture mode at which part of the connection occurs at the connection are measured. ·confirmed. The outline of the test is shown in FIGS. Table 1 also shows the results of the bonding strength test.

Method for measuring longest diameter of void The value of the current density applied to the tin plating bath is set to 0.25 to 3.
In order to investigate how the current density affects the surface condition of tin plating by shaking in the range of 5 A / dm ² , the surface condition of the tin-plated electrode pad is analyzed and confirmed as follows. did. That is, 100 μ
The number of voids having a longest diameter φmax of 0.3 μm or more on the tin-plated surface having an area of m ² was confirmed on a SEM photograph. Here, the “longest diameter” indicates the length of a portion where the largest dimension value is obtained in an irregular void. FIG. 11 shows a method of measuring the longest diameter φmax of the void.
It was shown to.

Auger electron analysis near tin-plated surface In order to investigate and confirm how the surface condition of the tin-plated layer affects the amount of organic residue and the degree of oxidation near the tin-plated surface, Auger electron analysis near the tin-plated surface was performed. Electronic analysis was performed. The analysis and measurement of each content of tin, oxygen and carbon by Auger electron analysis were performed under the following conditions. Analyzer: JAMP-30 (manufactured by JEOL) Acceleration voltage: 10 kV Irradiation current: 3 × 10 ⁻⁷ mA Spot diameter (analysis area): φ20 μm Under these measurement conditions, about 50 Å (0.005 μm) from the surface of the measurement material Information on the substance up to the depth of ()) can be obtained. The reason why the analysis region is limited to a depth of 50 angstroms (0.005 μm) is that the reliability of flip-chip connection largely depends on adhesion of foreign matter and oxidation near the surface of tin plating. The analysis results are shown in Table 1.

[0029]

[Table 1]

According to the results of the bonding strength test shown in Table 1, the longest diameter of the tin plating layer was 0.3 μm
The fracture mode in the bonding strength test of Sample Nos. 1 and 2 in which the number of voids is 50 or more per 100 μm ² is that the fracture occurs at the bonding interface between the tin plating layer on the wiring board side and the gold bump on the flip chip side. Mode. This fracture mode indicates that alloying sufficient to obtain sufficient bonding between the tin plating layer and the gold bump was not promoted. The bonding strength was also a low value of 2 kg or less.

On the other hand, on the surface of the tin plating layer, the number of voids having the longest diameter of 0.3 μm or more is 100 μm
The breaking mode in the bonding strength test of Sample Nos. 3 to 6 in which the number was 50 or less per ² was a breaking in the copper plating layer on the wiring board side. This fracture mode indicates that alloying that promotes sufficient bonding between the tin plating layer and the gold bump has been promoted. The bonding strength was also a high value of 3 kg or more. Comparing these results, it is clear that the bonding strength of the flip chip connection depends on the state of the voids in the tin plating layer.

The results of Auger electron analysis near the tin plating surface shown in Table 1 show that the number of voids having a longest diameter of 0.3 μm or more on the surface of the tin plating layer was 50 or more per 100 μm ^2. For certain sample numbers 1 and 2, the ratio of carbon content to tin content is 2 or more.

On the other hand, on the surface of the tin plating layer, the number of voids having the longest diameter of 0.3 μm or more is 100 μm
^For sample numbers 3 to 6 which are 50 or less per ²
The ratio of the carbon content to the tin content is 0.5 or less. Comparing these results shows that the rougher the surface state of the tin plating, the higher the tendency to take in organic residues.

Further, looking at the values of the current density shown in Table 1, it was found that Sample No. 3 in which good flip-chip connectivity was obtained was obtained.
6 that the current density was set in the range of 0.8 to 3.0 A / dm ² . When the current density is lower than the range of the present application, it can be seen that a large number of voids are generated on the tin-plated surface, which lowers the reliability of flip-chip connection.

On the other hand, when the current density is higher than the range of the present invention, the generation of voids on the tin plating surface can be suppressed, but the bump-like projections caused by the excessive current density abnormally grow on the tin plating surface, and the tin plating quality is reduced. Will deteriorate. From the above results, by performing the tin plating process at a current density within the range of the present application, a wiring board having good flip-chip connectivity can be obtained.

[0036]

As described above, in the wiring board of the present invention, the number of voids having the longest diameter of 0.3 μm or more on the outermost surface of the electrode pad to be flip-chip connected is 50 or less per 100 μm ^2. By performing tin plating as described in (1), flip-chip connection having good bonding strength can be achieved.

[0037]

[Brief description of the drawings]

FIG. 1 is an enlarged sectional view of a pad portion for explaining an embodiment of a wiring board according to the present invention.

FIG. 2 is an enlarged cross-sectional view illustrating a state before reflow in which a flip-chip connection type integrated circuit chip is positioned and mounted on a pad of the wiring substrate in FIG. 1;

FIG. 3 is an enlarged cross-sectional view illustrating a connection state between pads when the integrated circuit chip is flip-chip connected to electrode pads of a wiring board by reflow in FIG. 2;

FIG. 4 is an SEM photographic image showing the surface state of conventional tin plating.

FIG. 5 is an SEM photograph showing the surface state of tin plating in the present invention.

FIG. 6 is an explanatory diagram when a load is applied in a bonding strength test to an integrated circuit chip that is flip-chip connected to a wiring board.

FIG. 7 is an explanatory diagram when an integrated circuit chip is broken from a wiring board.

FIG. 8 is an explanatory view when an integrated circuit chip is cut off from a wiring board in a case where a conventional wiring board having tin plating in a surface state is used.

FIG. 9 is an explanatory view when the integrated circuit chip is broken from the wiring board in the case where the wiring board having tin plating in the surface state of the present invention is used.

FIG. 10 is an explanatory view showing a state in which organic residues are trapped in voids generated in tin plating formed on the outermost surface of an electrode pad in a conventional wiring board.

FIG. 11 is an explanatory view showing a method of measuring the longest diameter of a void on a tin plating surface according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Ceramic substrate 3 Via-hole conductor Thin film layer for electrode pads 4a Titanium thin film 4b Copper thin film Copper plating layer with thin gold plating 5a Copper plating layer 5b Gold plating layer 6 Tin plating layer 7 Tin plating surface void 8 Tin plating surface void Organic residue 11 Electrode pad for wiring board Flip-chip connection type integrated circuit chip Electrode pad for integrated circuit chip Gold bump

Claims (12)

[Claims] 1. A wiring board comprising an electrode pad group for electrically connecting flip-chip connection type integrated circuit chips, and having a tin plating layer on a conductor layer forming each electrode pad. Thus, on the surface of the tin plating layer, the number of voids having the longest diameter of 0.3 μm or more is 1
A wiring board, wherein the number of wiring boards is 50 or less per 00 μm ² . 2. The wiring board according to claim 1, wherein said tin plating layer has a thickness of 1 to 6 μm. 3. The wiring board according to claim 1, wherein the wiring board is a ceramic wiring board. 4. The wiring board according to claim 3, wherein the electrode pad is made of a metal selected from at least one of copper and gold. 5. The electrode pad according to claim 1, wherein the electrode pad has a multilayer structure of three layers of titanium-copper-gold in order from the substrate surface and a multilayer layer of three layers of copper-gold-tin in order from the sputtered film surface. The wiring board according to claim 3, comprising a plating film having a structure. 6. The electrode pad comprises: a thick film formed on a substrate surface and made of at least one metal of copper, silver, platinum, gold and palladium; and a nickel-gold-tin tin film sequentially from the thick film surface. 4. The wiring substrate according to claim 3, comprising a plating film having a multilayer structure composed of layers. 7. The electrode pad comprises: a thick film formed on a substrate surface and made of at least one metal of copper, silver, platinum, palladium, and gold; and two layers of nickel-tin in order from the thick film surface. 4. The wiring board according to claim 3, comprising a plating film having a multilayer structure. 8. The wiring board according to claim 1, wherein the wiring board is a printed wiring board containing a heat-resistant resin as a main component. 9. The wiring board according to claim 7, wherein the electrode pad is formed of a plating film having a multilayer structure including four layers of copper, nickel, gold, and tin in order from the substrate surface. 10. The wiring board according to claim 7, wherein the electrode pad is formed of a plating film having a multilayer structure composed of three layers of copper, nickel, and tin in order from the substrate surface. 11. When the total of the atomic percentages of the three components of tin, oxygen and carbon near the tin plating surface is 100%, the ratio of the atomic% of carbon to the atomic% of tin detected near the surface of the tin plating is The wiring board according to claim 1, wherein the value is 0.5 or less. 12. The method according to claim 1, wherein the current density applied to the tin plating bath in the tin plating step is 0.8 to 3.0 A / dm ² .