JPH11307627A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH11307627A
JPH11307627A JP10219334A JP21933498A JPH11307627A JP H11307627 A JPH11307627 A JP H11307627A JP 10219334 A JP10219334 A JP 10219334A JP 21933498 A JP21933498 A JP 21933498A JP H11307627 A JPH11307627 A JP H11307627A
Authority
JP
Japan
Prior art keywords
insulating film
step
groove
semiconductor substrate
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10219334A
Other languages
Japanese (ja)
Inventor
Yuuri Mizuo
有里 水尾
Original Assignee
Nippon Steel Corp
新日本製鐵株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP9-220815 priority Critical
Priority to JP22081597 priority
Priority to JP5624598 priority
Priority to JP10-56245 priority
Application filed by Nippon Steel Corp, 新日本製鐵株式会社 filed Critical Nippon Steel Corp
Priority to JP10219334A priority patent/JPH11307627A/en
Publication of JPH11307627A publication Critical patent/JPH11307627A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench type element isolation structure, wherein the electrical characteristics of the device are improved, and a method of manufacturing the device. SOLUTION: First grooves, which respectively have even slant surfaces 5 of a prescribed angle as the sidewalls thereof, are formed in a P-type silicon semiconductor substrate 1, and thereafter, the slant surfaces 5 are masked with a thermal oxide film 6. After that, the substrate 1 exposed through the bottoms of the grooves 4 is further removed, whereby second grooves 7 with the sidewalls roughly vertical with respect to the substrate 1 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of defining an element formation region on a semiconductor substrate, and more particularly to a semiconductor device having an element isolation region having a trench type element isolation structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art As one structure for achieving electrical isolation between elements on a semiconductor substrate, a trench-type element isolation structure is known. In the element isolation structure, for example, an insulating film layer made of an oxide film or the like is buried in a groove formed in a semiconductor substrate made of silicon to define an element active region.

In such a trench type element isolation structure, electric field concentration tends to occur at the end of the element isolation region.
A reduction in the threshold voltage of a MOS transistor has conventionally been a problem.

In order to solve this problem, the upper part of the side wall of the trench in the trench type element isolation structure is formed in a tapered shape, and the lower part is formed vertically so as to reduce the electric field concentration on the end of the element isolation region. The structure is disclosed in JP-A-63-30
No. 5,527 and JP-A-1-107554.

Japanese Patent Application Laid-Open No. Hei 6-177239 discloses a structure in which the entire trench from the upper side to the lower side of the trench in the trench type element isolation structure is formed in a tapered shape.

Further, Japanese Patent Application Laid-Open No. Hei 7-161808 discloses a method in which the angle of the side wall is reduced by wet etching at the upper end of the groove.

In the method disclosed in Japanese Patent Application Laid-Open No. Sho 63-305527, the inside of a groove formed on a semiconductor substrate is buried with an insulating film so as not to reach the surface of the semiconductor substrate. By removing the edge formed by the surface of the substrate by isotropic etching, a taper is formed at the upper end of the side wall of the groove.

In the method disclosed in Japanese Patent Application Laid-Open No. 1-107554, an oxide film is formed on a semiconductor substrate, and the oxide film is processed into a mask shape for forming a groove.
Before forming the grooves, isotropic plasma etching is performed.
In this way, a taper is formed in the upper end portion of the sidewall of the groove in advance, and then the groove is formed by performing anisotropic etching, thereby completing the groove having the taper at the upper end.

In the method disclosed in Japanese Patent Application Laid-Open No. 6-177239, dry etching using nitrogen gas and oxygen gas is performed using a cap oxide film as a mask to form a groove whose entire side wall is tapered. I have.

[0010]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. 63-3055
In the method disclosed in Japanese Patent Publication No. 27, since the process window of the etching conditions is narrow and the edges of the groove side walls and the surface of the semiconductor substrate are rounded by wet etching,
It was difficult to form a tapered surface having a constant slope.

In the method disclosed in Japanese Patent Application Laid-Open No. 1-107554, since a taper is formed by isotropic plasma etching, a desired slope cannot be formed. Further, since the groove is deepened by performing anisotropic etching as it is after forming the taper, there is a possibility that the shape of the taper becomes more uneven in this anisotropic etching step.

Further, the above-mentioned Japanese Patent Application Laid-Open No. Sho 63-30552
In the method disclosed in Japanese Patent Application Laid-Open No. 7-107554 and Japanese Patent Application Laid-Open No. 1-107554, after forming a taper, an oxide film is formed directly on a semiconductor substrate to fill the groove, and etched back to leave this oxide film in the groove. Therefore, there is a disadvantage that there is no effective stopper film at the time of etching back.

Therefore, the surface of the oxide film filling the trench after the etch back is formed on the same plane as the surface of the semiconductor substrate. Further, when the gate wiring of the MOS transistor is formed above the oxide film filling the trench, the distance between the gate wiring and the semiconductor substrate becomes short. There has been a problem that concentration occurs.

In the method disclosed in Japanese Patent Application Laid-Open No. Hei 7-161808, since the slope is formed at the upper end of the groove by wet etching, there is a problem that the groove width is unnecessarily enlarged and the element isolation area becomes large. Was. This not only hinders the miniaturization of semiconductor devices,
There is also a problem that the semiconductor substrate exposed in the groove is damaged.

As described above, in the above three conventional examples, the taper angle formed at the upper end of the groove cannot be controlled uniformly, and the surface of the element isolation region and the surface of the semiconductor substrate are formed on the same surface. Therefore, the concentration of the electric field at the end of the element isolation region cannot be effectively reduced.

Therefore, when a MOS transistor is formed by applying the trench type element isolation structure in the above two conventional examples, it is not possible to suppress the occurrence of variation in threshold voltage, and to reduce the threshold voltage. The decline was also an unavoidable problem.

In the method disclosed in JP-A-6-177239, the entire side wall of the groove is tapered, so that only the groove having a constant aspect ratio can be formed. That is, there has been a problem that the depth of the groove is naturally determined by the groove width. Therefore, in order to ensure sufficient element isolation performance, it is necessary to increase the width of the element isolation region, which has been a major obstacle to miniaturization of elements.

Further, as another problem of the trench type element isolation structure, when removing the laminated film serving as a mask for forming a groove or in a subsequent cleaning step, the end of the insulating film filled with the groove is removed. As a result, there has been a problem that the semiconductor device is lowered below the surface of the semiconductor substrate.

Then, M is straddled over the depressed portion.
When the gate electrode of the OS transistor is formed,
Electric field concentration occurs at the boundary between the insulating film and the semiconductor substrate, that is, at the element isolation end of the trench-type element isolation structure.

A method for preventing this problem is disclosed in JP-A-6-2.
No. 1210 or JP-A-7-273180.

According to the descriptions in these publications, after a laminated film serving as a mask for forming a groove is formed in a semiconductor substrate, a portion where the groove is to be formed is selectively removed to form an opening, A silicon oxide film is formed on the entire surface of the semiconductor substrate by the CVD method to temporarily fill the opening.

Then, the silicon oxide film on the stacked film is removed by anisotropic etching to form a side wall made of the silicon oxide film on the side wall of the stacked film at the opening. When forming a groove in the semiconductor substrate, etching is performed using the sidewall and the laminated film as a mask.

After forming the groove, a silicon oxide film is formed by the CVD method to fill the groove, and the silicon oxide film on the laminated film is removed. Then, the trench type element isolation structure is completed by removing the laminated film used as a mask.

According to this method, the opening is narrowed by an amount corresponding to the formation of the sidewalls compared with the laminated film. Therefore, when the laminated film is removed, the silicon oxide film buried in the groove is removed. A sidewall made of a silicon oxide film is also left at the side edge portion. Therefore, the formed trench-type element isolation structure is formed on the semiconductor substrate to be wider than the groove width by the width of the sidewall.

Therefore, at the time of removing the laminated film or at the time of the subsequent cleaning step, the sidewall is removed before the silicon oxide film filling the trench is removed. By serving as a protective film, it is possible to suppress the formation of the above-described depression at the element isolation end.

However, even if the side wall made of the silicon oxide film is formed as described above and the width of the trench type element isolation structure is widened, the silicon oxide film forming the side wall serves as a protective film against etching or cleaning. Did not perform well.

That is, in the above-described example, a silicon oxide film formed by a CVD method is used as a sidewall. Then, hot phosphoric acid is used to remove the silicon nitride film which is generally used as a mask film for forming a groove, and the silicon oxide film formed by the CVD method has a sufficient etching selectivity with respect to the silicon nitride film. I couldn't do that.

Similarly, the sidewall made of the silicon oxide film could not sufficiently protect the silicon oxide film in which the trench was buried even in cleaning in a later step.

Therefore, when the silicon nitride film is removed by hot phosphoric acid, or in the subsequent etching and cleaning steps, the sidewalls are completely removed, and the boundary between the silicon oxide film filled with the trench and the semiconductor substrate is removed. In this case, a problem that a depression is formed has occurred.

As a result, when the gate electrode of the MOS transistor is formed so as to straddle the depression, electric field concentration occurs at the element isolation end of the trench element isolation structure, lowering the threshold voltage of the transistor and reducing leakage. A problem such as an increase in current cannot be avoided.

The present invention has been made in order to solve such a problem. In a semiconductor device having a trench-type element isolation structure, electric field concentration at an element isolation end is suppressed, thereby achieving an electric connection. It is an object of the present invention to provide a semiconductor device having improved characteristics and reliability and a method for manufacturing the same.

[0032]

According to the present invention, there is provided a semiconductor device comprising:
A groove formed on the semiconductor substrate; and an insulating film filling the groove, wherein a side wall of the groove is formed on a slope having a predetermined angle with respect to a surface of the semiconductor substrate formed on an upper part and on a lower part. And a surface substantially perpendicular to the surface of the semiconductor substrate, and the bottom surface of the groove is formed flat.

In one embodiment of the semiconductor device of the present invention, the slope is formed to a depth approximately half of the groove.

In one embodiment of the semiconductor device of the present invention, the predetermined angle is 60 degrees with respect to the surface of the semiconductor substrate.
In the range of ° to 70 °.

In one embodiment of the semiconductor device of the present invention, the insulating film is formed so as to protrude from a surface of the semiconductor substrate, and a side edge portion of the insulating film on the semiconductor substrate is formed of polycrystalline silicon. It is covered with a thermal oxide film formed by thermally oxidizing the film.

In one embodiment of the semiconductor device of the present invention, a silicon oxide film formed by a CVD method is formed between the thermal oxide film and the insulating film.

In one embodiment of the semiconductor device of the present invention, the predetermined angle is formed near the surface of the semiconductor substrate so that the predetermined angle becomes small.

A semiconductor device according to the present invention is a semiconductor device having a trench-type element isolation structure comprising an insulating film filling a groove of a semiconductor substrate, wherein the insulating film is formed to protrude from the surface of the semiconductor substrate. A side edge portion of the insulating film on the semiconductor substrate is covered with a thermal oxide film formed by thermally oxidizing a polycrystalline silicon film.

In one embodiment of the semiconductor device of the present invention, a silicon oxide film formed by a CVD method is formed between the thermal oxide film and the insulating film.

In the method of manufacturing a semiconductor device according to the present invention, a first step of forming a first insulating film on a semiconductor substrate, and a step of selectively removing the first insulating film to form a first insulating film on the semiconductor substrate. A second step of exposing a portion, and removing the semiconductor substrate exposed according to the shape of the first insulating film to form a sidewall formed of a slope formed at a predetermined angle with respect to the surface of the semiconductor substrate. A third step of forming a first groove having a first groove, a fourth step of forming a second insulating film covering an inner wall surface of the first groove including the slope, and a step of forming a second insulating film covering a bottom surface of the first groove. A fifth step of removing the second insulating film and exposing the semiconductor substrate at the bottom surface of the first groove; and removing the semiconductor substrate exposed at the bottom surface of the first groove. A groove extending from a side wall of the first groove and substantially perpendicular to a surface of the semiconductor substrate; Step 6 of forming a second groove having a wall; and forming a third insulating film on the entire surface including the inside of the first groove and the inside of the second groove to form the first groove and the second groove. A seventh step of filling the trench, an eighth step of removing the third insulating film until the first insulating film is exposed, and a ninth step of removing the first insulating film. Have.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the angle of the slope of the first groove formed in the third step is 60 ° to 70 ° with respect to the surface of the semiconductor substrate. Within range.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the depth of the first groove formed in the third step and the depth of the second groove formed in the sixth step are described. Are almost the same.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the eighth step, the third step
Is polished and removed by a chemical mechanical polishing method.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a tenth step of forming a pad insulating film on the semiconductor substrate is provided before the first step,
Forming the first insulating film via the pad insulating film in the first step, and selectively removing the pad insulating film together with the first insulating film in the second step; The method further includes an eleventh step of removing the pad insulating film left on the semiconductor substrate after the ninth step.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a fourth insulating film covering an inner wall surface of the second groove is formed between the sixth step and the seventh step. There is further provided a twelfth step.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, in the third step, the semiconductor substrate is removed by performing dry etching in an atmosphere containing at least chlorine, and the sidewall formed by the slope is removed. Forming a first groove.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, in the third step, dry etching is performed in a mixed atmosphere of hydrogen bromide and chlorine.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, in the step (6), the semiconductor substrate is removed by performing dry etching in a mixed atmosphere of hydrogen bromide and oxygen. Form a groove.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the first insulating film is a silicon nitride film.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, in the fourth step, the first
The second insulating film is formed by thermally oxidizing the semiconductor substrate exposed in the groove.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the semiconductor substrate is thermally oxidized in a nitrogen-diluted atmosphere.

The method for manufacturing a semiconductor device according to the present invention comprises:
A first step of forming a first insulating film on a semiconductor substrate;
A second step of forming a second insulating film on the first insulating film, and forming an opening for exposing the first insulating film by selectively removing the second insulating film; A third step, a fourth step of forming an easily oxidizable film on the entire surface of the semiconductor substrate, and removing the easily oxidizable film until the first insulating film is exposed at the opening. A fifth step of forming a first sidewall made of the easily oxidizable film at a side wall portion of the second insulating film in the opening, and forming a third insulating film on the entire surface of the semiconductor substrate. A sixth step of forming, and removing the third insulating film until the semiconductor substrate is exposed in the opening, and forming a third insulating film formed of the third insulating film so as to cover the first sidewall. A second step of forming a second sidewall, the second insulating film and the second An eighth step of forming the groove in the semiconductor substrate by removing the semiconductor substrate exposed in the opening using the sidewall as a mask, and forming a fourth insulating film on the entire surface of the semiconductor substrate. A ninth step of filling the groove, a tenth step of removing the fourth insulating film until the second insulating film is exposed, and removing the first and second insulating films. An eleventh step of exposing the lower semiconductor substrate and a twelfth step of subjecting the semiconductor substrate to heat treatment to thermally oxidize the first sidewall made of the easily oxidizable film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the twelfth step, the first sidewall film is thermally oxidized and the semiconductor substrate surface is thermally oxidized. A gate oxide film on the surface of the substrate.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the tenth step, the fourth insulating film is removed by a chemical mechanical polishing method.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a fifth insulating film covering an inner wall surface of the groove is formed between the eighth and ninth steps. And further comprising the step of:

According to the method of manufacturing a semiconductor device of the present invention, a first step of forming a first insulating film on a semiconductor substrate and exposing the semiconductor substrate by selectively removing the first insulating film. A second step of forming an opening, a third step of forming an easily oxidized film on the entire surface of the semiconductor substrate, and a thermal oxidation of the easily oxidized film by performing a heat treatment on the semiconductor substrate. A fourth step of forming a film, and removing the thermal oxide film on the first insulating film to form a sidewall made of the thermal oxide film on a side wall portion of the first insulating film in the opening portion A fifth step of forming a groove in the semiconductor substrate by removing the semiconductor substrate exposed in the opening using the first insulating film and the sidewall as a mask; Forming a second insulating film on the entire surface of the semiconductor substrate, A seventh step of burying the groove, an eighth step of removing the second insulating film until the first insulating film is exposed, and a step of removing the first insulating film to remove the lower semiconductor. A ninth step of exposing the substrate.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the first step, the first insulating film is formed via a pad insulating film, and in the second step, the first insulating film is formed. The opening is formed by selectively removing the pad insulating film together with the first insulating film. In the ninth step, the pad insulating film is removed together with the first insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, after the ninth step, the surface of the semiconductor substrate is thermally oxidized to form a gate oxide film on the surface of the semiconductor substrate.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the eighth step, the second insulating film is removed by a chemical mechanical polishing method.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, a third insulating film covering an inner wall surface of the groove is formed between the sixth step and the seventh step. And further comprising the step of:

According to the method of manufacturing a semiconductor device of the present invention, a first step of forming a first insulating film on a semiconductor substrate and a second step of forming a second insulating film on the first insulating film are provided. Process and
A third step of selectively removing the second insulating film to form an opening exposing the first insulating film, and a fourth step of forming an easily oxidizable film on the entire surface of the semiconductor substrate. And removing the easily oxidizable film until the first insulating film is exposed in the opening, so that the easily oxidizable film is removed from the easily oxidizable film at a side wall portion of the second insulating film in the opening. A fifth step of forming a first sidewall, a sixth step of forming a third insulating film over the entire surface of the semiconductor substrate, and a step of forming a third insulating film on the entire surface of the semiconductor substrate until the semiconductor substrate is exposed in the opening. Removing a third insulating film and the first insulating film to form a second sidewall made of the third insulating film so as to cover the first sidewall; The opening is formed using the second insulating film and the second sidewall as a mask. An eighth step of removing the semiconductor substrate exposed in the step (a) and forming a first groove having a sidewall formed of a slope formed at a predetermined angle with respect to the surface of the semiconductor substrate; and A ninth step of forming a fourth insulating film on the inner wall surface of the first groove, and removing the fourth insulating film on the bottom surface of the first groove to form the semiconductor on the bottom surface of the first groove. First to expose the substrate
Step 0, and removing the semiconductor substrate exposed at the bottom surface of the first groove, and having a groove extending from the side wall of the first groove and substantially perpendicular to the surface of the semiconductor substrate. An eleventh step of forming a second groove, and forming a fifth insulating film on the entire surface including the inside of the first groove and the second groove, and forming the first groove and the second groove A twelfth step of embedding, a thirteenth step of removing the fifth insulating film until the second insulating film is exposed, and a step of removing the first and second insulating films to remove the lower semiconductor layer. Fourteenth exposing the substrate
And a fifteenth step of performing a heat treatment on the semiconductor substrate to thermally oxidize the first sidewall made of the easily oxidizable film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the angle of the slope of the first groove formed in the eighth step is 60 ° to 70 ° with respect to the surface of the semiconductor substrate. Within range.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the thirteenth step, the fifth insulating film is polished and removed by a chemical mechanical polishing method.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, in the eighth step, the semiconductor substrate is removed by performing dry etching in an atmosphere containing at least chlorine, and the sidewall formed by the slope is removed. Forming a first groove.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a sixth insulating film covering an inner wall surface of the second groove is formed between the eleventh step and the twelfth step. There is further provided a sixteenth step.

In the method of manufacturing a semiconductor device according to the present invention, a first step of forming a first insulating film on a semiconductor substrate, and the semiconductor substrate is exposed by selectively removing the first insulating film. A second step of forming an opening, a third step of forming an easily oxidized film on the entire surface of the semiconductor substrate, and a thermal oxidation of the easily oxidized film by performing a heat treatment on the semiconductor substrate. A fourth step of forming a film, and removing the thermal oxide film until the surface of the semiconductor substrate is exposed in the opening, thereby forming a sidewall portion of the first and second insulating films in the opening. A fifth step of forming a sidewall made of the thermal oxide film, and removing the semiconductor substrate exposed at the opening using the first insulating film and the sidewall as a mask. Form at a predetermined angle to the surface First with sidewalls made of the slope
A sixth step of forming a groove, and the first step including the slope.
A seventh step of forming a second insulating film on the inner wall surface of the groove,
An eighth step of removing the second insulating film on the bottom surface of the first groove to expose the semiconductor substrate on the bottom surface of the first groove; and exposing the semiconductor substrate on the bottom surface of the first groove. A step of removing the semiconductor substrate to form a second groove having a side wall substantially perpendicular to a surface of the semiconductor substrate, the second groove continuing from a side wall of the first groove; A tenth step of forming a third insulating film on the entire surface including the inside of the groove and the second groove to bury the first groove and the second groove, and exposing the first insulating film Up to the eleventh step of removing the third insulating film and a twelfth step of removing the first insulating film.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the angle of the slope of the first groove formed in the sixth step is 60 ° to 70 ° with respect to the surface of the semiconductor substrate. Within range.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the eleventh step, the third insulating film is polished and removed by a chemical mechanical polishing method.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the sixth step, the semiconductor substrate is removed by performing dry etching in an atmosphere containing at least chlorine, and the sidewall formed by the slope is removed. Forming a first groove.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a fourth insulating film covering an inner wall surface of the second groove is formed between the ninth step and the tenth step. The method further includes a thirteenth step.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the first step, the first insulating film is formed via a pad insulating film, and in the second step, the first insulating film is formed. The opening is formed by selectively removing the pad insulating film together with the first insulating film;
In the step, the pad insulating film is removed together with the first insulating film.

[0072]

In the present invention, after a first groove having a slope having a uniform side wall is formed in a semiconductor substrate, only the slope is covered with a second insulating film and etching is performed to thereby expose the semiconductor exposed at the bottom. The substrate is removed to form a second groove. Therefore, a groove having a slope formed uniformly at a predetermined angle with respect to the surface of the semiconductor substrate can be formed in the upper half, and a groove having a substantially vertical side wall can be formed in the lower half with good controllability.

When forming the first groove, dry etching is preferably performed in a chlorine atmosphere or a mixed atmosphere of hydrogen bromide and chlorine, so that the side wall of the first groove is stably formed as a slope. be able to. When forming the second groove, dry etching is performed in a mixed atmosphere of hydrogen bromide and oxygen to make the side wall of the second groove almost perpendicular to the surface of the semiconductor substrate. Can be.

As described above, by forming a uniform slope at the upper end of the side wall of the groove, even if an electric field is generated at the end of the element isolation region, the electric field is stepwise formed by the slope formed with good controllability. Can be dispersed, so that the concentration of the electric field can be reduced.

Since the lower half of the side wall of the groove is formed perpendicular to the surface of the semiconductor substrate, the depth of the groove can be made sufficient. Therefore, it is possible to reliably perform element isolation.

Further, in the present invention, when forming the trench type element isolation structure, a mask film having an opening and an easily oxidized film (first side wall) formed on the side wall of the opening are used. A groove is formed in the semiconductor substrate using the second sidewall to be used as a mask. Then, after filling the groove with the insulating film, the mask film is removed. This makes it possible to leave an easily oxidizable film on the semiconductor substrate at the side edge portion of the insulating film filling the trench via the second sidewall. Then, by thermally oxidizing the easily oxidized film, the side edge portion of the insulating film filling the groove can be covered and protected by the thermal oxide film.

Further, according to the present invention, when forming the trench type element isolation structure, a mask film having an opening and a side wall made of a thermal oxide film formed in the opening are used as masks to form a semiconductor substrate. Form a groove. Then, after filling the groove with the insulating film, the mask film is removed. Thereby, the side edge portion of the insulating film filling the groove on the semiconductor substrate can be protected by covering with the thermal oxide film.

In this case, a polycrystalline silicon film is preferably used as an easily oxidizable film. Since the etching rate of the thermal oxide film formed by thermally oxidizing the polycrystalline silicon film is as small as 1/6 of the silicon oxide film formed by the CVD method,
It is hardly removed by etching, cleaning, or the like. This can prevent the thermal oxide film from functioning as a protective film and removing the insulating film in the trench in the mask film removing step or the etching and cleaning steps in the subsequent steps.

[0079]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A structure and a manufacturing method of an nMOS transistor to which a trench type element isolation structure according to the present invention is applied will be described below with reference to FIGS.

First, as shown in FIG. 1A, the surface of a p-type silicon semiconductor substrate 1 is thermally oxidized to form a thermal oxide film 2 having a thickness of about 300 °. Then, a silicon nitride film 3 having a thickness of about 2000.degree.

Next, as shown in FIG. 1B, an opening 26 for exposing the p-type silicon semiconductor substrate 1 in a region to be element-isolated is formed by photolithography and subsequent dry etching. The silicon nitride film 3 and the thermal oxide film 2 are removed.

Subsequently, as shown in FIG. 2A, dry etching is performed in a chlorine (Cl 2 ) atmosphere using the silicon nitride film 3 as a mask to remove the p-type silicon semiconductor substrate 1 in the opening 26. A first groove 4 having a depth of about 2000 ° is formed.

In forming the first groove 4, instead of dry etching in a chlorine atmosphere, hydrogen bromide (HB
Dry etching may be performed in a mixed atmosphere of r) and chlorine.

By performing dry etching under such conditions, as shown in FIG. 2A, a uniform slope 5 having an angle (θ) of about 70 ° with respect to the surface of the p-type silicon semiconductor substrate 1 is formed. It can be formed as a side wall of the first groove 4.

As described above, by forming the slope 5 in the first groove 4 and performing element isolation, even if an electric field is generated near the slope 5 of the p-type silicon semiconductor substrate 1, the depth along the slope is increased. It becomes possible to disperse stepwise in the vertical direction.

Moreover, since the slope 5 having a predetermined angle can be formed with high precision by the dry etching as described above, it is more effective to reduce the electric field concentration. If the angle (θ) of the slope is smaller than 60 °, the groove width becomes unnecessarily large, and if it is larger than 70 °, the electric field concentration increases. Therefore, by forming the angle (θ) of the slope in the range of 60 ° to 70 °, it is possible to miniaturize the element and obtain an optimal structure in which the concentration of the electric field is suppressed.

If the angle (θ) of the slope 5 is 70 ° or more, a kink current occurs in the characteristic diagram of the drain current (I d −V g ) with respect to the gate voltage of the MOS transistor, and the electrical characteristics of the MOS transistor Becomes more remarkable. By forming the angle (θ) of the slope 5 to 70 ° or less as in the present embodiment, it is possible to suppress the generation of a kink current and to form a MOS transistor having good I d -V g characteristics. It is.

As described above, the depth of the first groove 4 is set to about 2000 ° and the angle of the slope 5 is set to 60 ° or more, so that the horizontal distance of the side wall portion of the first groove 4 is reduced to 0 °. 2 μm or more can be secured. As a result, the electric field concentration can be reduced to suppress the leak,
In addition, it is possible to reduce the element isolation area by minimizing the overhang of the slope 5 in the horizontal direction.

Next, as shown in FIG. 2B, by performing a thermal oxidation treatment, p exposed on the inner wall surface of the first groove 4 is formed.
A thermal oxide film 6 having a thickness of about 500 ° is formed in the surface region of the silicon semiconductor substrate 1.

Next, as shown in FIG. 3A, the thermal oxide film 6 is removed only on the bottom surface of the first groove 4. Here, by performing anisotropic etching, only the thermal oxide film 6 formed on the bottom surface of the first groove 4 can be removed. Therefore, the thermal oxide film 6 is left on the slope 5 which is the side wall of the first groove 4, and the surface of the p-type silicon semiconductor substrate 1 can be covered as it is.

Next, as shown in FIG. 3B, a mixture of hydrogen bromide (HBr) and oxygen (O 2 ) is formed using the silicon nitride film 3 and the thermal oxide film 6 left on the slope 5 as a mask. Dry etching is performed in an atmosphere to form a second groove 7 extending from the first groove 4 in the depth direction.

The gas flow ratio between hydrogen bromide and oxygen in the dry etching is HBr: O 2 = 20: 1 to 20
About 0: 1 is appropriate.

By performing dry etching under such conditions, the side wall 8 of the second groove 7 is formed at an angle of about 80 ° to 90 ° with respect to the surface of the p-type silicon semiconductor substrate 1.

As described above, the side wall 8 is formed almost perpendicular to the surface of the p-type silicon semiconductor substrate 1, so that the second
The groove width of the groove 7 does not decrease with the depth. Therefore, element separation can be reliably performed by making the second groove 7 sufficiently deep.

Here, the depth of the second groove 7 is 2000 mm.
It is preferable to form it to such an extent. Therefore, the total depth of the groove including the depth of the first groove 4 is about 4000 ° from the surface of the p-type silicon semiconductor substrate 1.

Next, as shown in FIG. 4A, the surface region of the p-type silicon semiconductor substrate 1 exposed on the inner wall surface of the second groove 7 is subjected to a thermal oxidation treatment, so that the thermal oxidation is performed to a thickness of about 200 °. Membrane 9
To form This thermal oxide film 9 prevents diffusion of a damaged layer formed in the surface region of the inner wall of the second groove 7 by etching.

Next, as shown in FIG.
By the D method, the entire surface including the inside of the first groove 4 and the second groove 7 is
A silicon oxide film 10 having a thickness of about 7000 ° is formed.
Thereby, the first groove 4 and the second groove 7 are completely filled with the silicon oxide film 10.

Next, as shown in FIG. 5A, the silicon oxide film 10 is polished and removed by a chemical mechanical polishing (CMP) method. Then, when the silicon nitride film 3 is exposed, polishing is stopped using the silicon nitride film 3 as a stopper.

Next, as shown in FIG. 5B, the silicon nitride film 3 is removed by anisotropic dry etching or wet etching. When the silicon oxide film 10 is formed of an HTO film having high wet etching resistance, the silicon nitride film 3 can be removed by wet etching. Subsequently, the thermal oxide film 2 is removed by wet etching using hydrogen fluoride or dry etching. Thereby, the first groove 4 and the second groove 7
The trench type element isolation structure 11 is completed with the silicon oxide film 10 left inside. An element formation region 12 is defined by the trench type element isolation structure 11.

Next, as shown in FIG. 6A, after a thermal oxide film 13 is formed on the element formation region 12 by thermal oxidation, an impurity such as phosphorus (P) is added to the entire surface by low-pressure CVD. Then, a polycrystalline silicon film 14 having conductivity is formed.

Next, after a silicon oxide film 15 is formed on the polycrystalline silicon film 14, the silicon oxide film 15 is formed by photolithography and subsequent dry etching.
And patterning the polycrystalline silicon film 14, FIG.
A gate electrode 17 made of the polycrystalline silicon film 14 is formed as shown in FIG.

Next, as shown in FIG. 7A, using the trench-type element isolation structure 11 and the silicon oxide film 15 as a mask, arsenic (an n-type impurity) is formed in the surface region of the p-type silicon semiconductor substrate 1. As) is ion-implanted at a low concentration to form a low-concentration impurity diffusion layer 19.

Next, a silicon oxide film is formed on the entire surface by low-pressure CVD. Then, as shown in FIG. 7B, a side wall insulating film 20 made of the silicon oxide film is formed on the side surfaces of the gate electrode 17 and the silicon oxide film 15 by photolithography and subsequent anisotropic dry etching. . At the same time, the thermal oxide film 13 is
Then, the gate oxide film 16 is formed by being removed under the side wall insulating film 20 to form a gate oxide film 16.

Next, as shown in FIG. 7C, using the trench type element isolation structure 11, the silicon oxide film 15 and the side wall insulating film 20 as a mask, an n-type is formed on the surface region of the p-type silicon semiconductor substrate 1. Arsenic (As) or phosphorus (P) as an impurity is ion-implanted at a high concentration to form a high-concentration impurity diffusion layer 21. Thereafter, heat treatment is performed to activate the impurities in the low concentration impurity diffusion layer 19 and the high concentration impurity diffusion layer 21.

Next, as shown in FIG.
After the PSG film 22 is deposited thick, a reflow process is performed. Then, contact holes 23 and 24 reaching the high concentration impurity diffusion layer 21 and the gate electrode 17 are opened.

Then, an aluminum wiring 25 is deposited by sputtering, the contact holes 23 and 24 are filled and patterned on the BPSG film 22 to complete the nMOS transistor as shown in FIG. 8B.

As described above, in this embodiment, the slope 5 can be stably formed on the side wall of the first groove 4 by performing dry etching in a chlorine atmosphere. The slope 5 prevents concentration of an electric field near the slope 5 of the p-type silicon semiconductor substrate 1 and suppresses formation of a parasitic transistor extending over the trench-type element isolation structure 1.

Therefore, the threshold voltage of the nMOS transistor can be kept constant, and the variation of the threshold voltage can be minimized.

Further, by performing dry etching in a mixed atmosphere of hydrogen bromide (HBr) and oxygen, the side wall 8 of the second groove 7 can be formed substantially perpendicular to the surface of the p-type silicon semiconductor substrate 1. it can. Thereby, the depth of the second groove 7 can be made sufficiently large, and electrical separation between adjacent element formation regions can be reliably performed.

Therefore, an nMOS transistor having extremely excellent electric characteristics is formed on the element forming region 12 defined by the trench type element isolation structure 11 having the first groove 4 and the second groove 7. be able to.

(Modification) Hereinafter, a modification of the first embodiment will be described. In this modification, in the manufacturing process of the nMOS transistor according to the first embodiment, the first
The step of oxidizing the inner wall surface of the first groove 4 after the formation of the groove 4 is different.

FIG. 9A is a schematic sectional view of a process corresponding to FIG. 2A in the first embodiment in this modification.

In the first embodiment, the thermal oxide film 6 is formed by performing a thermal oxidation process after the formation of the first groove 4. However, in a modification, the thermal oxidation condition is changed to change the thermal oxidation film 6. The slope of the first groove 4 is machined into a shape that can alleviate the electric field concentration.

That is, after the first groove 4 is formed, the oxygen concentration is set to 15% or less in a nitrogen-diluted atmosphere,
The inner wall surface of the first groove 4 is oxidized by performing the oxidation treatment at about 000 ° C. to 1100 ° C. for 1 hour or more. Thereby, it is possible to form the thermal oxide film 6 ′ having a thickness of about 150 ° and to round the edge of the upper end of the slope 5 of the first groove 4 as shown in FIG. 9A. .

As described above, the shape of the upper end of the slope 5 can be changed to a shape more suitable for alleviating the electric field concentration only by changing the oxidation conditions. Since the edge of the slope 5 is rounded, the electric field concentration of the p-type silicon semiconductor substrate 1 at the edge portion can be reduced and the edge can be dispersed in the surface direction of the rounded edge.

The subsequent steps are performed in the same manner as in the first embodiment, and as shown in FIG.
Complete the MOS transistor.

(Second Embodiment) The structure and manufacturing method of an nMOS transistor according to a second embodiment of the present invention will be described below with reference to FIGS. In these drawings, the same components as those in the first embodiment are denoted by the same reference numerals.

First, as shown in FIG. 10A, the surface of a p-type silicon semiconductor substrate 1 is thermally oxidized to form a thermal oxide film 2 having a thickness of about 300.degree. ,
A silicon nitride film 3 having a thickness of about 2000 ° is formed by low pressure CVD. Here, the thermal oxide film 2 functions as a pad insulating film for relieving stress generated in the p-type silicon semiconductor substrate 1 and the silicon nitride film 3.

Next, as shown in FIG. 10B, an opening 26 for exposing the p-type silicon semiconductor substrate 1 in a region to be element-isolated is formed by photolithography and subsequent dry etching. The silicon nitride film 3 is removed.

Next, as shown in FIG. 11A, a polycrystalline silicon film 31 having a thickness of about 300 ° is formed on the entire surface of the p-type silicon semiconductor substrate 1. Thereby, the opening 26
Is covered with a polycrystalline silicon film 31.

Next, as shown in FIG. 11B, the polycrystalline silicon film 31 is removed by anisotropic etching until the thermal oxide film 2 is exposed at the opening 26. That is,
Anisotropic etching is performed using the thermal oxide film 2 as an end point of the etching. Thereby, the polycrystalline silicon film 31 is formed in the opening 2
6 only remains on the side wall portions of the silicon nitride film 3;
A sidewall 32 made of the polycrystalline silicon film 31 is formed.

Next, as shown in FIG. 12A, a silicon oxide film 33 is formed on the entire surface of the p-type silicon semiconductor substrate 1 by the CVD method.

Next, as shown in FIG. 12B, the silicon oxide film 33 is removed by anisotropic etching until the p-type silicon semiconductor substrate 1 is exposed in the opening 26. That is, anisotropic etching is performed using the p-type silicon semiconductor substrate 1 as the end point of the etching. As a result, the silicon oxide film 33 remains so as to cover the sidewall 32, and the sidewall 34 made of the silicon oxide film 33 is formed.
Is formed.

Subsequently, as shown in FIG. 13A, dry etching is performed in a chlorine (Cl 2 ) atmosphere using the silicon nitride film 3 as a mask to remove the p-type silicon semiconductor substrate 1 in the opening 26. The first about 2000mm deep
Is formed.

In forming the first groove 4, instead of dry etching in a chlorine atmosphere, hydrogen bromide (HB
Dry etching may be performed in a mixed atmosphere of r) and chlorine.

By performing dry etching under such conditions, as shown in FIG. 13A, a uniform slope 5 having an angle (θ) of about 70 ° with respect to the surface of the p-type silicon semiconductor substrate 1 is formed. It can be formed as a side wall of the first groove 4.

As described above, by forming the slope 5 in the first groove 4 and performing element isolation, even if an electric field is generated in the vicinity of the slope 5 of the p-type silicon semiconductor substrate 1, the depth along the slope is increased. It becomes possible to disperse stepwise in the vertical direction.

In addition, since the inclined surface 5 having a predetermined angle can be formed with high precision by the dry etching as described above, it is more effective to reduce the electric field concentration. If the angle (θ) of the slope is smaller than 60 °, the groove width becomes unnecessarily large, and if it is larger than 70 °, the electric field concentration increases. Therefore, by forming the angle (θ) of the slope in the range of 60 ° to 70 °, it is possible to miniaturize the element and obtain an optimal structure in which the concentration of the electric field is suppressed.

Next, as shown in FIG. 13B, a thermal oxidation treatment is performed so that the surface region of the p-type silicon semiconductor substrate 1 exposed on the inner wall surface of the first groove 4 has a thickness of 500.degree.
A thermal oxide film 6 of a degree is formed.

Next, as shown in FIG. 14A, the thermal oxide film 6 is removed only on the bottom surface of the first groove 4. Here, by performing anisotropic etching, only the thermal oxide film 6 formed on the bottom surface of the first groove 4 can be removed. Therefore,
The thermal oxide film 6 is left on the slope 5 which is the side wall of the first groove 4 so that the surface of the p-type silicon semiconductor substrate 1 can be covered as it is.

Next, as shown in FIG. 14B, a mixture of hydrogen bromide (HBr) and oxygen (O 2 ) is formed using the silicon nitride film 3 and the thermal oxide film 6 left on the slope 5 as a mask. Dry etching is performed in an atmosphere to form a second groove 7 extending from the first groove 4 in the depth direction.

The gas flow ratio between hydrogen bromide and oxygen in this dry etching is HBr: O 2 = 20: 1 to 20
About 0: 1 is appropriate.

By performing dry etching under such conditions, the side wall 8 of the second groove 7 is formed at an angle of about 80 ° to 90 ° with respect to the surface of the p-type silicon semiconductor substrate 1.

As described above, since the side wall 8 is formed substantially perpendicular to the surface of the p-type silicon semiconductor substrate 1, the second side wall 8 is formed.
The groove width of the groove 7 does not decrease with the depth. Therefore, element separation can be reliably performed by making the second groove 7 sufficiently deep.

Here, the depth of the second groove 7 is 2000 mm.
It is preferable to form it to such an extent. Therefore, the total depth of the groove including the depth of the first groove 4 is about 4000 ° from the surface of the p-type silicon semiconductor substrate 1.

Next, as shown in FIG. 15A, the surface region of the p-type silicon semiconductor substrate 1 exposed on the inner wall surface of the second groove 7 is subjected to a thermal oxidation treatment, so as to have a thermal oxidation thickness of about 200 °. A film 9 is formed. This thermal oxide film 9 prevents diffusion of a damaged layer formed in the surface region of the inner wall of the second groove 7 by etching.

Next, as shown in FIG.
A silicon oxide film 35 having a thickness of about 7000 ° is formed on the entire surface including the inside of the first groove 4 and the second groove 7 by the VD method. Thus, the first groove 4 and the second groove 7 are completely filled with the silicon oxide film 35.

Next, as shown in FIG. 16A, the silicon oxide film 10 is polished and removed by a chemical mechanical polishing (CMP) method. Then, when the silicon nitride film 3 is exposed, polishing is stopped using the silicon nitride film 3 as a stopper.

Next, as shown in FIG. 16B, the silicon nitride film 3 is removed by anisotropic dry etching, and then the thermal oxide film 2 is removed by wet etching with hydrogen fluoride or dry etching. I do. Thereby, the silicon oxide film 3 is formed in the first groove 4 and the second groove 7.
5, the trench type element isolation structure 11 is completed.
An element formation region 12 is defined by the trench type element isolation structure 11.

At this time, the side wall 3 is formed on the side edge of the silicon oxide film 35 in which the first groove 4 and the second groove 7 are buried.
2, 34 are exposed. Then, as is clear from FIG. 16B, the sidewalls 32 and 34 are formed outside the first groove 4.

Next, as shown in FIG. 17A, the entire surface of the p-type silicon semiconductor substrate 1 is subjected to a heat treatment so that the side wall 32 of the polycrystalline silicon film 31 is thermally oxidized. Is done. As a result, the outer side wall 32 of the side walls 32 and 34 becomes the thermal oxide film 36.

Since the thermal oxide film 36 having a small etching rate can be formed so as to cover the outside of the silicon oxide film 35 constituting the trench type element isolation structure 11, the trench type element isolation structure 11 is etched. The structure can be reinforced against Therefore, even if etching or cleaning is performed in a later step, the trench-type element isolation structure 11 can be surely protected by the thermal oxide film 36, and the removal of the trench-type element isolation structure 11 is suppressed. Can be.

At the same time as the formation of the thermal oxide film 36, the exposed p
The surface of type silicon semiconductor substrate 1 is thermally oxidized to form gate oxide film 15.

Thereafter, after the gate electrode 16 is formed and patterned, an impurity diffusion layer 21 is formed in the surface region of the p-type silicon semiconductor substrate 1 on both sides of the gate electrode 16 by ion implantation.

Thereafter, a BPSG film 22 is deposited, contact holes 23 and 24 are opened, and an aluminum wiring 2 is formed.
By forming No. 5, as shown in FIG.
The nMOS transistor is completed.

As described above, in the second embodiment of the present invention, the sidewall 34 made of the polycrystalline silicon film 31 can be formed on the outer edge of the trench type element isolation structure 11. Then, by performing heat treatment, the sidewalls 34 are thermally oxidized to form the thermal oxide film 36.

Thus, the trench type element isolation structure 11
Is covered with the thermal oxide film 36 having a low etching rate. Then, it is possible to form the trench-type element isolation structure 11 that is reinforced against etching or cleaning in a later step.

Therefore, since the trench-type element isolation structure 11 is not removed and is not depressed below the surface of the p-type silicon semiconductor substrate 1, the gate electrode extends from the trench-type element isolation structure 11 to the element active region. Even if formed
Electric field concentration at the element isolation end can be suppressed.

Further, similarly to the first embodiment, by forming the slope 5 on the side wall of the first groove 4, concentration of the electric field near the slope 5 of the p-type silicon semiconductor substrate 1 is prevented.
It is possible to suppress formation of a parasitic transistor extending over the trench-type element isolation structure 11.

Therefore, the threshold voltage of the nMOS transistor can be kept constant, and the variation of the threshold voltage can be minimized.

Further, by performing dry etching in a mixed atmosphere of hydrogen bromide (HBr) and oxygen, the side wall 8 of the second groove 7 can be formed substantially perpendicular to the surface of the p-type silicon semiconductor substrate 1. it can. Thereby, the depth of the second groove 7 can be made sufficiently large, and electrical separation between adjacent element formation regions can be reliably performed.

Therefore, an nMOS transistor having extremely excellent electric characteristics is formed on the element forming region 12 defined by the trench type element isolation structure 11 having the first groove 4 and the second groove 7. be able to.

As a result, it is possible to form a MOS transistor in which a decrease in threshold voltage is suppressed and a leak current is minimized.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings. FIG.
24 to 24 are schematic cross-sectional views illustrating a method of manufacturing a MOS transistor according to the third embodiment in the order of steps.

First, as shown in FIG. 18A, the surface of a p-type silicon semiconductor substrate 41 is thermally oxidized to form a thermal oxide film 42 having a thickness of about 300 °. Then, a silicon nitride film 43 having a thickness of about 2000 ° is formed on the thermal oxide film. Here, the thermal oxide film 42 is formed on the p-type silicon semiconductor substrate 4.
1 and functions as a pad insulating film for relaxing the stress generated in the silicon nitride film 43.

Next, as shown in FIG. 18B, an opening 44 is formed by selectively removing the silicon nitride film 43 in a range to be an element isolation region by photolithography and subsequent dry etching. I do.

Next, as shown in FIG. 19A, a polycrystalline silicon film 45 having a thickness of about 300 ° is formed on the entire surface of the p-type silicon semiconductor substrate 41. Thereby, the opening 4
4 is covered with a polycrystalline silicon film 45.

Next, as shown in FIG. 19B, the polycrystalline silicon film 45 is removed by anisotropic etching until the thermal oxide film 42 is exposed at the opening 44. That is, anisotropic etching is performed using the thermal oxide film 42 as the end point of the etching. As a result, the polycrystalline silicon film 45 remains only at the side wall portion of the silicon nitride film 43 in the opening portion 44, and a sidewall 46 made of the polycrystalline silicon film 45 is formed.

Next, as shown in FIG. 20A, a silicon oxide film 47 is formed on the entire surface of the p-type silicon semiconductor substrate 41 by the CVD method.

Next, as shown in FIG. 20B, the silicon oxide film 47 is removed by anisotropic etching until the p-type silicon semiconductor substrate 41 is exposed at the opening 44. That is, anisotropic etching is performed using the p-type silicon semiconductor substrate 41 as an etching end point. This allows
The silicon oxide film 47 remains so as to cover the sidewall 46, and the sidewall 4 made of the silicon oxide film 47 is formed.
8 are formed.

Next, as shown in FIG. 21A, etching is performed using the sidewalls 46 and 48 and the silicon nitride film 43 as a mask, so that the depth is approximately 4000 ° perpendicular to the surface of the p-type silicon semiconductor substrate 41. Is formed.

Here, since sidewalls 48 of polycrystalline silicon film 45 are covered by sidewalls 48 of silicon oxide film 47, sidewalls 46 are removed even if p-type silicon semiconductor substrate 1 is removed. Never.

Next, as shown in FIG. 21B, in order to take in a damaged layer formed on the inner wall surface of the formed groove 50, the inner wall surface of the groove is thermally oxidized to a thermal oxide film having a thickness of about 200 °. 51 are formed.

Next, as shown in FIG.
A silicon oxide film 52 having a thickness of about 8000 ° is formed by the method. Thereby, the groove 50 is completely buried.

Next, as shown in FIG. 22B, the silicon oxide film 52 is polished and removed by chemical mechanical polishing (CMP) until the silicon nitride film 43 is exposed. At this time, the silicon nitride film 43 functions as a polishing stopper. As a result, the silicon oxide film 52 remains in the groove 50.

Next, as shown in FIG. 23A, the silicon nitride film 43 used as a mask for forming the groove 50 is removed by wet etching with hot phosphoric acid. Thereafter, the thermal oxide film 42 is removed using hydrofluoric acid or the like to expose the surface of the p-type silicon semiconductor substrate 41. Then, a trench type element isolation structure 53 composed of the silicon oxide film 52 is formed. At this time, the side walls 46 and 48 are exposed at the side edges of the silicon oxide film 52 filling the trench 50.
Then, as is clear from FIG. 23A, the sidewalls 46 and 48 are formed outside the groove 50.

Next, as shown in FIG. 23B, the entire surface of the p-type silicon semiconductor substrate 41 is subjected to a heat treatment,
Polycrystalline silicon film 45 out of sidewalls 46 and 48
Is thermally oxidized. Thus, the outer one of the side walls 46, 48 becomes the thermal oxide film 54.

Since the thermal oxide film 54 having a small etching rate can be formed so as to cover the outside of the silicon oxide film 52 constituting the trench type element isolation structure 53, the trench type element isolation structure 53 is etched. The structure can be reinforced against Therefore, even if etching or cleaning is performed in a later step, the trench-type element isolation structure 53 can be surely protected by the thermal oxide film 54, and the removal of the trench-type element isolation structure 53 is suppressed. Can be.

At the same time as the formation of the thermal oxide film 54, the exposed p
The surface of type silicon semiconductor substrate 41 is thermally oxidized to form gate oxide film 55.

Next, as shown in FIG. 24A, a polycrystalline silicon film 56 doped with impurities is formed on the entire surface.
Then, the polycrystalline silicon film 56 and the thermal oxide film 55 are formed by photolithography and subsequent dry etching.
Is patterned into a gate electrode shape.

Next, as shown in FIG. 24B, arsenic, which is an n-type impurity, is ion-implanted using trench type element isolation structure 53 and polycrystalline silicon film 56 serving as a gate electrode as a mask. Then, a pair of impurity diffusion layers 57 serving as a source / drain are formed in the surface region of the p-type silicon semiconductor substrate 1 on both sides of the polycrystalline silicon film 56 serving as the gate electrode by performing a heat treatment.

A BPS as an interlayer insulating film is formed on the entire surface.
After a G film 58 is formed and planarized by reflow, a contact hole reaching the impurity diffusion layer 57 is formed in the BPSG film 58. Thereafter, an aluminum film 59 is formed by a sputtering method, a contact hole reaching the impurity diffusion layer 57 is filled, and the aluminum film 59 is patterned to form an n film as shown in FIG.
Complete the MOS transistor.

As described above, in the third embodiment of the present invention, the sidewall 46 made of the polycrystalline silicon film 45 can be formed at the outer edge of the trench type element isolation structure 53. Then, by performing a heat treatment, the sidewall 46 is thermally oxidized to form the thermal oxide film 54.

Thus, the trench type element isolation structure 53
Is covered with the thermal oxide film 54 having a low etching rate. Then, it is possible to form the trench-type element isolation structure 53 which is strengthened against etching or cleaning in a later step.

Therefore, since the trench-type element isolation structure 53 is not removed and is not depressed below the surface of the p-type silicon semiconductor substrate 1, the gate electrode extends from the trench-type element isolation structure 53 so as to straddle the element active region. Even if formed
Electric field concentration at the element isolation end can be suppressed.

As a result, it is possible to form a MOS transistor in which a decrease in threshold voltage is suppressed and a leak current is minimized.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG.
31 to 31 are schematic cross-sectional views showing a method for manufacturing a MOS transistor according to the fourth embodiment in the order of steps.

First, as shown in FIG. 25A, the surface of a p-type silicon semiconductor substrate 61 is thermally oxidized to form a thermal oxide film 62 having a thickness of about 300 °. Then, a silicon nitride film 63 having a thickness of about 2000 ° is formed on the thermal oxide film 62. Here, the thermal oxide film 62 is formed on the p-type silicon semiconductor substrate 6.
1 and a function as a pad insulating film for relaxing the stress generated in the silicon nitride film 63.

Next, as shown in FIG. 25 (b), the silicon nitride film 63 and the thermal oxide film 62 in the range to become the element isolation region are selectively removed by photolithography and subsequent dry etching. An opening 64 exposing the p-type silicon semiconductor substrate 61 is formed.

Next, as shown in FIG. 26A, a polycrystalline silicon film 76 having a thickness of about 500 ° is formed on the entire surface of the p-type silicon semiconductor substrate 61. Then, by performing a heat treatment on the entire surface of the p-type silicon semiconductor substrate 61, the polycrystalline silicon film 76 is thermally oxidized to form a thermal oxide film 65 having a thickness of about 750 °. This state is shown in FIG.

Next, as shown in FIG. 27A, the thermal oxide film 65 is removed by anisotropic etching until the p-type silicon semiconductor substrate 61 is exposed at the opening 64. That is, anisotropic etching is performed using the p-type silicon semiconductor substrate 61 as the end point of the etching. As a result, the thermal oxide film 65 remains only in the side wall portions of the silicon nitride film 63 and the thermal oxide film 62 in the opening 64, and a sidewall 66 made of the thermal oxide film 65 is formed.

Next, as shown in FIG. 27B, etching is performed using the sidewall 66 and the silicon nitride film 63 as a mask, thereby forming the p-type silicon semiconductor substrate 6.
A groove 67 having a depth of about 4000 ° is formed vertically on the surface of the substrate 1.

Next, as shown in FIG. 28A, in order to take in a damaged layer formed on the inner wall surface of the formed groove 67, the inner wall surface of the groove is thermally oxidized to a thermal oxide film having a thickness of about 200 °. 68 are formed.

Next, as shown in FIG.
A silicon oxide film 69 having a thickness of about 8000 ° is formed by the method. Thereby, the groove 67 is completely buried.

Next, as shown in FIG. 29A, the silicon oxide film 69 is polished and removed by chemical mechanical polishing (CMP) until the silicon nitride film 63 is exposed. At this time, the silicon nitride film 63 functions as a polishing stopper. As a result, the silicon oxide film 69 remains in the groove 67.

Next, as shown in FIG. 29B, the silicon nitride film 63 used as a mask for forming the groove 67 is removed by wet etching using hot phosphoric acid. Thereafter, the thermal oxide film 62 is removed using hydrofluoric acid or the like to expose the surface of the p-type silicon semiconductor substrate 61. Then, a trench type element isolation structure 70 made of the silicon oxide film 69 is formed. At this time, the sidewall 66 is exposed at the side edge of the silicon oxide film 69 filling the groove 67. Then, as is clear from FIG. 29B, the sidewall 66 is formed outside the groove 67.

As described above, the side wall 66 made of the thermal oxide film 65 having a small etching rate can be formed so as to cover the outside of the silicon oxide film 69 constituting the trench type element isolation structure 70. The isolation structure 70 can be a structure reinforced with respect to etching. Therefore, even if etching or cleaning is performed in a later step, the trench-type element isolation structure 70 can be reliably protected by the thermal oxide film 65, and the removal of the trench-type element isolation structure 70 is suppressed. Can be.

Next, as shown in FIG. 30A, the exposed surface of the p-type silicon semiconductor substrate 61 is thermally oxidized to form a gate oxide film 71. Thereafter, a polycrystalline silicon film 72 doped with impurities is formed on the entire surface. And
The polycrystalline silicon film 72 and the gate oxide film 31 are patterned into a gate electrode shape by photolithography and subsequent dry etching.

Next, as shown in FIG. 30B, arsenic, which is an n-type impurity, is ion-implanted using the trench-type element isolation structure 70 and the polycrystalline silicon film 72 serving as a gate electrode as a mask. Then, by performing heat treatment, a pair of impurity diffusion layers 73 serving as a source / drain are formed in the surface regions of the p-type silicon semiconductor substrate 61 on both sides of the polycrystalline silicon film 72 serving as the gate electrode.

Then, a BPS as an interlayer insulating film is formed on the entire surface.
After a G film 74 is formed and planarized by reflow, a contact hole reaching the impurity diffusion layer 73 is formed. Thereafter, an aluminum film 75 is formed by sputtering, a contact hole reaching the impurity diffusion layer 73 is filled, and the aluminum film 75 is patterned to complete an nMOS transistor as shown in FIG.

As described above, in the fourth embodiment of the present invention, the side wall 66 made of the thermal oxide film 65 can be formed on the outer edge of the trench type element isolation structure 70.

Thus, the trench type element isolation structure 70
Is covered with a thermal oxide film 65 having a low etching rate. Then, it is possible to form the trench-type element isolation structure 70 which is reinforced with respect to etching or cleaning in a later step.

Therefore, the trench-type element isolation structure 70 is not removed and is not depressed below the surface of the p-type silicon semiconductor substrate 61.
Even if the gate electrode is formed so as to straddle the element active region, the electric field concentration at the element isolation end can be suppressed.

As a result, it is possible to form a MOS transistor in which a decrease in threshold voltage is suppressed and a leak current is minimized.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described in detail with reference to the drawings. FIG.
38 are schematic cross-sectional views illustrating a method of manufacturing a MOS transistor according to the fifth embodiment in the order of steps. The fourth
The same reference numerals are given to the same components as those of the embodiment.

First, as shown in FIG. 32A, the surface of a p-type silicon semiconductor substrate 81 is thermally oxidized to form a thermal oxide film 82 having a thickness of about 300 °. Then, a silicon nitride film 83 having a thickness of about 2000 ° is formed on the thermal oxide film 82. Here, the thermal oxide film 82 is formed on the p-type silicon semiconductor substrate 8.
1 and functions as a pad insulating film for relaxing the stress generated in the silicon nitride film 83.

Then, an opening for exposing the p-type silicon semiconductor substrate 81 by selectively removing the silicon nitride film 83 and the thermal oxide film 82 in a range to be an element isolation region by photolithography and subsequent dry etching. A portion 84 is formed.

Next, as shown in FIG. 32 (b), a polycrystalline silicon film 87 having a thickness of about 500 ° is formed on the entire surface of the p-type silicon semiconductor substrate 81. Then, heat treatment is performed on the entire surface of the p-type silicon semiconductor substrate 81 to thermally oxidize the polycrystalline silicon film 87 to form a thermal oxide film 85 having a thickness of about 750 °. This state is shown in FIG.

Next, as shown in FIG. 33B, the thermal oxide film 85 is removed by anisotropic etching until the p-type silicon semiconductor substrate 81 is exposed at the opening 84. That is, anisotropic etching is performed using the p-type silicon semiconductor substrate 81 as an etching end point. As a result, the thermal oxide film 85 remains only at the side wall portions of the silicon nitride film 83 and the thermal oxide film 82 in the opening 84, and the sidewall 86 made of the thermal oxide film 85 is formed.

Subsequently, as shown in FIG. 34A, dry etching is performed in a chlorine (Cl 2 ) atmosphere using the silicon nitride film 83 and the sidewalls 86 as a mask, and the p-type silicon semiconductor substrate 81 in the opening 84 is formed. Is removed to form a first groove 88 having a depth of about 2000 °.

In forming the first groove 88, instead of dry etching in a chlorine atmosphere, hydrogen bromide (HB
Dry etching may be performed in a mixed atmosphere of r) and chlorine.

By performing dry etching under such conditions, as shown in FIG. 34A, a uniform inclined surface 89 having an angle (θ) of about 70 ° with respect to the surface of the p-type silicon semiconductor substrate 81 is formed. It can be formed as a side wall of the first groove 88.

As described above, by forming the inclined surface 89 in the first groove 88 and performing element isolation, even if an electric field is generated near the inclined surface 89 of the p-type silicon semiconductor substrate 81, the depth along the inclined surface is reduced. It becomes possible to disperse stepwise in the vertical direction.

Further, since the inclined surface 89 having a predetermined angle can be formed with high precision by the dry etching as described above, it is more effective to reduce the electric field concentration. If the angle (θ) of the inclined surface 89 is smaller than 60 °, the groove width becomes larger than necessary, and if it is larger than 70 °, the electric field concentration increases. Therefore, by forming the angle (θ) of the inclined surface 89 in the range of 60 ° to 70 °, it is possible to miniaturize the element and obtain an optimal structure in which the concentration of the electric field is suppressed.

Next, as shown in FIG. 34 (b), a thermal oxidation process is performed so that the surface region of the p-type silicon semiconductor substrate 81 exposed on the inner wall surface of the first groove 88 has a thickness of 50 μm.
A thermal oxide film 90 of about 0 ° is formed.

Next, as shown in FIG. 35A, the thermal oxide film 90 is removed only on the bottom surface of the first groove 88. here,
By performing the anisotropic etching, only the thermal oxide film 90 formed on the bottom surface of the first groove 88 can be removed.
Therefore, the thermal oxide film 90 is left on the slope 89 as the side wall of the first groove 88, and the surface of the p-type silicon semiconductor substrate 81 can be covered as it is.

Next, as shown in FIG. 35B, a mixture of hydrogen bromide (HBr) and oxygen (O 2 ) is formed using the silicon nitride film 83 and the thermal oxide film 90 left on the slope 89 as a mask. By performing dry etching in an atmosphere, the first groove 88 is formed.
A second groove 91 extending in the depth direction is formed.

The gas flow ratio between hydrogen bromide and oxygen in this dry etching is HBr: O 2 = 20: 1 to 20
About 0: 1 is appropriate.

By performing dry etching under such conditions, the side wall 92 of the second groove 91 is formed at an angle of about 80 ° to 90 ° with respect to the surface of the p-type silicon semiconductor substrate 91.

As described above, since side wall 92 is formed substantially perpendicular to the surface of p-type silicon semiconductor substrate 91,
The groove width of the second groove 91 does not decrease with the depth. Therefore, element isolation can be reliably performed by making the second groove 91 sufficiently deep.

Here, the depth of the second groove 92 is 2000
It is preferable to form it to about Å. Therefore, the first groove 88
The total depth of the groove, together with the depth, is about 4000 ° from the surface of the p-type silicon semiconductor substrate 81.

Next, as shown in FIG. 36A, the p-type silicon semiconductor substrate 81 exposed on the inner wall surface of the second groove 91 is formed.
Is thermally oxidized to form a thermal oxide film 93 having a thickness of about 200 °. This thermal oxide film 93 prevents diffusion of a damaged layer formed in the surface region of the inner wall of the second groove 91 by etching.

Next, as shown in FIG.
A silicon oxide film 94 having a thickness of about 7000 ° is formed on the entire surface including the inside of the first groove 88 and the second groove 91 by the VD method. Thus, the first groove 88 and the second groove 91 are completely filled with the silicon oxide film 94.

Next, as shown in FIG. 37A, the silicon oxide film 94 is polished and removed by a chemical mechanical polishing (CMP) method. Then, when the silicon nitride film 83 is exposed, the polishing is stopped using the silicon nitride film 83 as a stopper.

Next, as shown in FIG. 37B, the silicon nitride film 8 is wet-etched with hot phosphoric acid.
3 is removed. Thereafter, the thermal oxide film 82 is formed using hydrofluoric acid or the like.
Is removed to expose the surface of the p-type silicon semiconductor substrate 81. Here, the silicon oxide film 94 and the sidewall 8
6 are formed.
At this time, the sidewall 86 is exposed at the side edge of the silicon oxide film 94 in which the first groove 88 and the second groove 91 are buried. Then, as is clear from FIG. 37B, the side wall 86 is formed outside the first groove 88.

As described above, the side wall 86 made of the thermal oxide film 85 having a small etching rate can be formed so as to cover the outside of the silicon oxide film 94 constituting the trench type element isolation structure 95. The isolation structure 95 can be a structure strengthened against etching. Therefore, even if etching or cleaning is performed in a later step, the trench element isolation structure 95 can be reliably protected by the sidewall 86 (thermal oxide film 85), and the trench element isolation structure 95 is removed. Can be suppressed.

Thereafter, through the same steps as in the fourth embodiment, an nMOS transistor as shown in FIG. 38 is completed.

As described above, in the fourth embodiment of the present invention, the sidewall 66 made of the thermal oxide film 65 can be formed on the outer edge of the trench type element isolation structure 70.

Thus, the trench type element isolation structure 70
Is covered with a thermal oxide film 65 having a low etching rate. Then, it is possible to form the trench-type element isolation structure 70 which is reinforced with respect to etching or cleaning in a later step.

Therefore, since trench-type element isolation structure 70 is not removed and does not sink below the surface of p-type silicon semiconductor substrate 41, trench-type element isolation structure 70
Even if the gate electrode is formed so as to straddle the element active region, the electric field concentration at the element isolation end can be suppressed.

Further, similarly to the first embodiment, by forming the slope 89 on the side wall of the first groove 88, concentration of the electric field near the slope 89 of the p-type silicon semiconductor substrate 81 is prevented, and the trench is formed. It is possible to suppress the formation of a parasitic transistor extending over the pattern element isolation structure 95.

Therefore, the threshold voltage of the nMOS transistor can be kept constant, and variation in the threshold voltage can be minimized.

Further, by performing dry etching in a mixed atmosphere of hydrogen bromide (HBr) and oxygen, the side wall 92 of the second groove 91 can be formed substantially perpendicular to the surface of the p-type silicon semiconductor substrate 81. it can. Accordingly, the depth of the second groove 91 can be made sufficiently large, and electrical isolation between adjacent element formation regions can be reliably performed.

Therefore, the first groove 88 and the second groove 9
An nMOS transistor having extremely excellent electrical characteristics can be formed on the element formation region defined by the trench-type element isolation structure 95 having a value of 1.

As a result, it is possible to form a MOS transistor in which a decrease in threshold voltage is suppressed and a leak current is minimized.

The groove formed at a predetermined angle described in the above-described embodiment may be applied to a buried type field shield element isolation structure. Similarly, the present invention may be applied to an embedded memory capacitor.

[0227]

According to the present invention, in a semiconductor device having a trench type element isolation structure, generation of electric field concentration at an element isolation end can be suppressed. Therefore, a semiconductor device with improved electrical characteristics and reliability and a method for manufacturing the same can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method for manufacturing an nMOS transistor according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a method of manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a schematic cross-sectional view showing a method of manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 9 shows an nMO according to a modification of the first embodiment of the present invention.
FIG. 3 is a schematic sectional view showing an S transistor.

FIG. 10 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 11 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 12 is a schematic cross-sectional view showing a method of manufacturing an nMOS transistor according to a second embodiment of the present invention in the order of steps.

FIG. 13 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 14 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 15 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 16 is a schematic cross-sectional view showing a method of manufacturing the nMOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 17 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 18 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the third embodiment of the present invention in the order of steps.

FIG. 19 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the third embodiment of the present invention in the order of steps.

FIG. 20 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the third embodiment of the present invention in the order of steps.

FIG. 21 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the third embodiment of the present invention in the order of steps.

FIG. 22 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the third embodiment of the present invention in the order of steps.

FIG. 23 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the third embodiment of the present invention in the order of steps.

FIG. 24 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the third embodiment of the present invention in the order of steps.

FIG. 25 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fourth embodiment of the present invention in the order of steps.

FIG. 26 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fourth embodiment of the present invention in the order of steps.

FIG. 27 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fourth embodiment of the present invention in the order of steps.

FIG. 28 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fourth embodiment of the present invention in the order of steps.

FIG. 29 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fourth embodiment of the present invention in the order of steps.

FIG. 30 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fourth embodiment of the present invention in the order of steps.

FIG. 31 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fourth embodiment of the present invention in the order of steps.

FIG. 32 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fifth embodiment of the present invention in the order of steps.

FIG. 33 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fifth embodiment of the present invention in the order of steps.

FIG. 34 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fifth embodiment of the present invention in the order of steps.

FIG. 35 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fifth embodiment of the present invention in the order of steps.

FIG. 36 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fifth embodiment of the present invention in the order of steps;

FIG. 37 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fifth embodiment of the present invention in the order of steps;

FIG. 38 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the fifth embodiment of the present invention in the order of steps.

[Explanation of symbols]

1,41,61,81 p-type silicon semiconductor substrate 2,6,6 ', 9,13,36,42,51,54,6
2, 65, 68, 82, 85, 90, 93 Thermal oxide film 3, 43, 63, 83 Silicon nitride film 4, 88 First groove 5, 89 Slope 7, 91 Second groove 8, 92 Side wall 10, 15, 33, 35, 47, 52, 69, 94 Silicon oxide film 11, 53, 70, 95 Trench type element isolation structure 12 Element formation region 14, 31, 45, 56, 76, 72, 87 Polycrystalline silicon film 16 , 17 Gate electrode 19 Low-concentration impurity diffusion layer 20 Side wall insulating film 21, 57, 73 High-concentration impurity diffusion layer 22, 58, 74 BPSG film 23, 24 Contact hole 25 Aluminum wiring 26, 44, 64, 84 Opening 32, 34, 46, 48, 66, 86 Side walls 50, 67 Grooves 55, 71 Gate oxide film 59, 75 Aluminum film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 29/786 H01L 29/78 621

Claims (40)

[Claims]
1. A groove formed on a semiconductor substrate, and an insulating film embedded in the groove, wherein a side wall of the groove has a slope having a predetermined angle with respect to a surface of the semiconductor substrate formed thereon. And a surface substantially perpendicular to the surface of the semiconductor substrate formed below, and the bottom surface of the groove is formed flat.
2. The semiconductor device according to claim 1, wherein said slope is formed to a depth approximately half of said groove.
3. The semiconductor device according to claim 1, wherein the predetermined angle is in a range of 60 ° to 70 ° with respect to a surface of the semiconductor substrate.
4. The semiconductor device according to claim 1, wherein the insulating film is formed so as to protrude from a surface of the semiconductor substrate, and a side edge portion of the insulating film on the semiconductor substrate is formed by thermally oxidizing a polycrystalline silicon film. The semiconductor device according to claim 1, wherein the semiconductor device is covered with an oxide film.
5. A CVD method between the thermal oxide film and the insulating film.
5. The semiconductor device according to claim 4, wherein a silicon oxide film formed by a method is formed.
6. The semiconductor device according to claim 1, wherein the predetermined angle is formed to be smaller in the vicinity of the surface of the semiconductor substrate.
7. A semiconductor device having a trench-type element isolation structure comprising an insulating film filling a groove of a semiconductor substrate, wherein the insulating film is formed so as to protrude from a surface of the semiconductor substrate. A side edge portion of the insulating film is covered with a thermal oxide film formed by thermally oxidizing a polycrystalline silicon film.
8. A CVD method between said thermal oxide film and said insulating film.
8. The semiconductor device according to claim 7, wherein a silicon oxide film formed by a method is formed.
9. A first step of forming a first insulating film on a semiconductor substrate, and a second step of selectively removing the first insulating film to expose a part of the semiconductor substrate And removing the semiconductor substrate exposed according to the shape of the first insulating film to form a first groove having a sidewall formed of a slope formed at a predetermined angle with respect to the surface of the semiconductor substrate. A third step, a fourth step of forming a second insulating film covering an inner wall surface of the first groove including the slope, and removing the second insulating film on a bottom surface of the first groove. A fifth step of exposing the semiconductor substrate at the bottom surface of the first groove; and removing the semiconductor substrate exposed at the bottom surface of the first groove, and continuing from a side wall of the first groove. Forming a second groove having a side wall substantially perpendicular to the surface of the semiconductor substrate; A step of forming a third insulating film on the entire surface including the inside of the first groove and the second groove, and embedding the first groove and the second groove; 8. A method of manufacturing a semiconductor device, comprising: an eighth step of removing the third insulating film until the first insulating film is exposed; and a ninth step of removing the first insulating film. Method.
10. The semiconductor device according to claim 9, wherein an angle of a slope of the first groove formed in the third step is in a range of 60 ° to 70 ° with respect to a surface of the semiconductor substrate. The manufacturing method of the semiconductor device described in the above.
11. The depth of the first groove formed in the third step and the depth of the second groove formed in the sixth step are substantially the same. 11. The method for manufacturing a semiconductor device according to 9 or 10.
12. The semiconductor device according to claim 9, wherein in the eighth step, the third insulating film is polished and removed by a chemical mechanical polishing method. Production method.
13. The method according to claim 10, further comprising: before the first step, a tenth step of forming a pad insulating film on the semiconductor substrate. Forming an insulating film; in the second step, selectively removing the pad insulating film together with the first insulating film; and the pad insulating film left on the semiconductor substrate after the ninth step The method for manufacturing a semiconductor device according to claim 9, further comprising an eleventh step of removing an impurity.
14. A twelfth step of forming a fourth insulating film covering an inner wall surface of the second groove between the sixth step and the seventh step. Claim 9
14. The method of manufacturing a semiconductor device according to any one of items 13 to 13.
15. The method according to claim 15, wherein in the third step, the semiconductor substrate is removed by performing dry etching in an atmosphere containing at least chlorine.
The method of manufacturing a semiconductor device according to claim 9, wherein the groove is formed.
16. The method according to claim 15, wherein, in the third step, dry etching is performed in a mixed atmosphere of hydrogen bromide and chlorine.
17. The method according to claim 9, wherein in the step (6), the semiconductor substrate is removed by performing dry etching in a mixed atmosphere of hydrogen bromide and oxygen to form the second groove. 17. The method for manufacturing a semiconductor device according to any one of items 16.
18. The method according to claim 9, wherein the first insulating film is a silicon nitride film.
19. The semiconductor device according to claim 9, wherein, in the fourth step, the second insulating film is formed by thermally oxidizing the semiconductor substrate exposed in the first groove. 9. The method for manufacturing a semiconductor device according to claim 1.
20. The method according to claim 19, wherein the semiconductor substrate is thermally oxidized in a nitrogen dilution atmosphere.
21. A first step of forming a first insulating film on a semiconductor substrate; a second step of forming a second insulating film on the first insulating film; A third step of selectively removing a film to form an opening exposing the first insulating film, and a fourth step of forming an easily oxidizable film on the entire surface of the semiconductor substrate.
Removing the easily oxidizable film until the first insulating film is exposed in the opening, and forming the second insulating film on the side wall portion of the second insulating film in the opening from the easily oxidizable film. The first
Forming a third insulating film on the entire surface of the semiconductor substrate;
And removing the third insulating film until the semiconductor substrate is exposed at the opening, and forming a second sidewall made of the third insulating film so as to cover the first sidewall. A seventh step of forming a groove in the semiconductor substrate by removing the semiconductor substrate exposed in the opening using the second insulating film and the second sidewall as a mask; Forming a fourth insulating film on the entire surface of the semiconductor substrate and filling the groove; and removing the fourth insulating film until the second insulating film is exposed. A tenth step, an eleventh step of removing the first and second insulating films and exposing the underlying semiconductor substrate, and performing a heat treatment on the semiconductor substrate to form the easily oxidizable film. Thermal oxidation of the first sidewall The method of manufacturing a semiconductor device, characterized in that it comprises a twelfth step that.
22. In the twelfth step, the first
22. The method according to claim 21, wherein a gate oxide film is formed on the surface of the semiconductor substrate by thermally oxidizing the sidewall film and thermally oxidizing the surface of the semiconductor substrate.
23. The method according to claim 21, wherein in the tenth step, the fourth insulating film is removed by a chemical mechanical polishing method.
24. A method of forming a fifth insulating film covering an inner wall surface of the groove between the eighth step and the ninth step.
3. The method according to claim 2, further comprising a third step.
3. The method for manufacturing a semiconductor device according to claim 3.
25. A first step of forming a first insulating film on a semiconductor substrate, and a second step of selectively removing the first insulating film to form an opening exposing the semiconductor substrate. Forming an easily oxidizable film on the entire surface of the semiconductor substrate.
Performing a heat treatment on the semiconductor substrate to form a thermal oxide film made of the easily oxidizable film; removing the thermal oxide film on the first insulating film; A fifth step of forming a sidewall made of the thermal oxide film at a side wall portion of the first insulating film in the opening; exposing the opening to the opening using the first insulating film and the sidewall as a mask; A sixth step of removing the semiconductor substrate and forming a groove in the semiconductor substrate; a seventh step of forming a second insulating film on the entire surface of the semiconductor substrate and filling the groove; An eighth step of removing the second insulating film until the first insulating film is exposed; and a ninth step of removing the first insulating film and exposing the underlying semiconductor substrate. A method for manufacturing a semiconductor device, comprising:
26. The method according to claim 26, wherein in the first step, the first insulating film is formed via a pad insulating film, and in the second step, the pad insulating film is selectively formed together with the first insulating film. 26. The method according to claim 25, wherein the opening is formed by removing the pad insulating film together with the first insulating film in the ninth step.
13. The method for manufacturing a semiconductor device according to item 5.
27. After the ninth step, a gate oxide film is formed on the surface of the semiconductor substrate by thermally oxidizing the surface of the semiconductor substrate.
7. The method for manufacturing a semiconductor device according to item 6.
28. The method according to claim 25, wherein, in the eighth step, the second insulating film is removed by a chemical mechanical polishing method.
29. A method of forming a third insulating film covering an inner wall surface of the groove between the sixth step and the seventh step.
3. The method according to claim 2, further comprising the step of:
9. The method for manufacturing a semiconductor device according to claim 8.
30. A first step of forming a first insulating film on a semiconductor substrate; a second step of forming a second insulating film on the first insulating film; A third step of selectively removing a film to form an opening exposing the first insulating film, and a fourth step of forming an easily oxidizable film on the entire surface of the semiconductor substrate.
Removing the easily oxidizable film until the first insulating film is exposed in the opening, and forming the second insulating film on the side wall portion of the second insulating film in the opening from the easily oxidizable film. The first
Forming a third insulating film on the entire surface of the semiconductor substrate;
Removing the third insulating film and the first insulating film until the semiconductor substrate is exposed in the opening, and covering the first sidewall with the third insulating film. A seventh step of forming a second sidewall made of a semiconductor substrate; removing the semiconductor substrate exposed at the opening using the second insulating film and the second sidewall as a mask; An eighth step of forming a first groove having a sidewall formed of a slope formed at a predetermined angle with respect to the surface of the first groove, and forming a fourth insulating film on an inner wall surface of the first groove including the slope A ninth step of removing the fourth insulating film at the bottom of the first groove to expose the semiconductor substrate at the bottom of the first groove; The semiconductor substrate exposed at the bottom of the groove is removed. An eleventh step of forming a second groove having a side wall substantially perpendicular to the surface of the semiconductor substrate, the second groove being a groove continuing from a side wall of the first groove, A twelfth step of forming a fifth insulating film on the entire surface including the inside of the second groove and embedding the first groove and the second groove, and the fifth step until the second insulating film is exposed. A thirteenth step of removing the insulating film, a fourteenth step of removing the first and second insulating films and exposing the underlying semiconductor substrate, and performing a heat treatment on the semiconductor substrate, A fifteenth step of thermally oxidizing the first sidewall made of a film that is easily oxidized.
31. The semiconductor device according to claim 30, wherein the angle of the slope of the first groove formed in the eighth step is within a range of 60 ° to 70 ° with respect to the surface of the semiconductor substrate. The manufacturing method of the semiconductor device described in the above.
32. In the thirteenth step, the fifth step
32. The method according to claim 30, wherein the insulating film is polished and removed by a chemical mechanical polishing method.
33. In the eighth step, the semiconductor substrate is removed by performing dry etching in an atmosphere containing at least chlorine, and the first substrate having the sidewall formed of the slope is removed.
33. The method of manufacturing a semiconductor device according to claim 30, wherein a groove is formed.
34. A method according to claim 16, further comprising a sixteenth step of forming a sixth insulating film covering an inner wall surface of said second groove between said eleventh step and said twelfth step. A method for manufacturing a semiconductor device according to any one of claims 30 to 33.
35. A first step of forming a first insulating film on a semiconductor substrate, and a second step of selectively removing the first insulating film to form an opening exposing the semiconductor substrate. Forming an easily oxidizable film on the entire surface of the semiconductor substrate.
A fourth step of performing a heat treatment on the semiconductor substrate to form a thermal oxide film made of the easily oxidizable film; and a thermal oxide film until the surface of the semiconductor substrate is exposed at the opening. A fifth step of forming a sidewall made of the thermal oxide film in a side wall portion of the first and second insulating films in the opening portion; and removing the first insulating film and the sidewall. A sixth step of removing the semiconductor substrate exposed in the opening using the mask as a mask to form a first groove having a sidewall formed of a slope formed at a predetermined angle with respect to the surface of the semiconductor substrate; Forming a second insulating film on the inner wall surface of the first groove including the slope, removing the second insulating film on the bottom surface of the first groove, and removing the first insulating film from the first groove; The semiconductor substrate at the bottom of the groove of Eighth step of removing, removing the semiconductor substrate exposed on the bottom surface of the first groove, and forming a groove extending from a side wall of the first groove and substantially perpendicular to the surface of the semiconductor substrate. Step 9 of forming a second groove having a side wall; and forming a third insulating film on the entire surface including the inside of the first groove and the second groove, and forming the first groove and the second groove. A tenth step of filling the groove, an eleventh step of removing the third insulating film until the first insulating film is exposed, and a twelfth step of removing the first insulating film. A method for manufacturing a semiconductor device, comprising:
36. The method according to claim 35, wherein an angle of a slope of the first groove formed in the sixth step is in a range of 60 ° to 70 ° with respect to a surface of the semiconductor substrate. The manufacturing method of the semiconductor device described in the above.
37. In the eleventh step, the third step
37. The method according to claim 35, wherein the insulating film is polished and removed by a chemical mechanical polishing method.
38. In the sixth step, the semiconductor substrate is removed by performing dry etching in an atmosphere containing at least chlorine, and the first substrate having a sidewall including the slope is formed.
38. The method of manufacturing a semiconductor device according to claim 35, wherein a groove is formed.
39. The method according to claim 39, further comprising a thirteenth step of forming a fourth insulating film covering an inner wall surface of the second groove between the ninth step and the tenth step. A method for manufacturing a semiconductor device according to claim 35.
40. In the first step, the first insulating film is formed via a pad insulating film, and in the second step, the pad insulating film is selectively formed together with the first insulating film. The method according to claim 3, wherein the opening is formed by removing the pad insulating film together with the first insulating film in the twelfth step.
The method for manufacturing a semiconductor device according to any one of claims 5 to 39.
JP10219334A 1997-08-01 1998-08-03 Semiconductor device and manufacture thereof Pending JPH11307627A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP9-220815 1997-08-01
JP22081597 1997-08-01
JP5624598 1998-02-20
JP10-56245 1998-02-20
JP10219334A JPH11307627A (en) 1997-08-01 1998-08-03 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10219334A JPH11307627A (en) 1997-08-01 1998-08-03 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH11307627A true JPH11307627A (en) 1999-11-05

Family

ID=27295855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10219334A Pending JPH11307627A (en) 1997-08-01 1998-08-03 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH11307627A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004274031A (en) * 2003-03-11 2004-09-30 Hynix Semiconductor Inc Method of manufacturing semiconductor device
KR100707899B1 (en) * 2004-03-23 2007-04-16 가부시끼가이샤 도시바 Semiconductor device and manufacturing method thereof
KR100835472B1 (en) 2002-06-29 2008-06-04 주식회사 하이닉스반도체 A method for forming a field oxide of semiconductor device
US7902597B2 (en) 2006-03-22 2011-03-08 Samsung Electronics Co., Ltd. Transistors with laterally extended active regions and methods of fabricating same
JP2011243638A (en) * 2010-05-14 2011-12-01 Sharp Corp Method for manufacturing semiconductor device
JP2012169606A (en) * 2011-01-26 2012-09-06 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method of the same
WO2018107429A1 (en) * 2016-12-15 2018-06-21 深圳尚阳通科技有限公司 Super junction component and manufacturing method therefor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100835472B1 (en) 2002-06-29 2008-06-04 주식회사 하이닉스반도체 A method for forming a field oxide of semiconductor device
JP2004274031A (en) * 2003-03-11 2004-09-30 Hynix Semiconductor Inc Method of manufacturing semiconductor device
KR100707899B1 (en) * 2004-03-23 2007-04-16 가부시끼가이샤 도시바 Semiconductor device and manufacturing method thereof
US7781293B2 (en) 2004-03-23 2010-08-24 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same including trenches of different aspect ratios
US7902597B2 (en) 2006-03-22 2011-03-08 Samsung Electronics Co., Ltd. Transistors with laterally extended active regions and methods of fabricating same
US8133786B2 (en) 2006-03-22 2012-03-13 Samsung Electronics Co., Ltd. Transistors with laterally extended active regions and methods of fabricating same
JP2011243638A (en) * 2010-05-14 2011-12-01 Sharp Corp Method for manufacturing semiconductor device
JP2012169606A (en) * 2011-01-26 2012-09-06 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method of the same
US10069014B2 (en) 2011-01-26 2018-09-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2018107429A1 (en) * 2016-12-15 2018-06-21 深圳尚阳通科技有限公司 Super junction component and manufacturing method therefor

Similar Documents

Publication Publication Date Title
US6642105B2 (en) Semiconductor device having multi-gate insulating layers and methods of fabricating the same
US7326975B2 (en) Buried channel type transistor having a trench gate and method of manufacturing the same
US7183154B2 (en) Nonvolatile memory cells having split gate structure and methods of fabricating the same
JP5075320B2 (en) Method for manufacturing MOS transistor having channel of three-dimensional structure
US6420250B1 (en) Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates
US6620703B2 (en) Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer
US6350661B2 (en) Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
US7675110B2 (en) Semiconductor device and method of manufacturing the same
US6963094B2 (en) Metal oxide semiconductor transistors having a drain punch through blocking region and methods for fabricating metal oxide semiconductor transistors having a drain punch through blocking region
KR100616390B1 (en) Semiconductor device and manufacturing method thereof
TWI396284B (en) Field effect transistor and method for manufacturing the same
JP4947931B2 (en) Semiconductor device
JP3725708B2 (en) Semiconductor device
KR101083644B1 (en) Semiconductor device and method for manufacturing the same
KR100629263B1 (en) MOS transistor having a recessed gate electrode and fabrication method thereof
KR100496891B1 (en) Silicon fin for finfet and method for fabricating the same
US6743692B2 (en) Semiconductor device manufacturing method
TWI249774B (en) Forming method of self-aligned contact for semiconductor device
US6069058A (en) Shallow trench isolation for semiconductor devices
US7288470B2 (en) Semiconductor device comprising buried channel region and method for manufacturing the same
KR100584776B1 (en) Method of forming active structure, isolation and MOS transistor
KR0174314B1 (en) Manufacturing Method of Semiconductor Device
JP3941133B2 (en) Semiconductor device and manufacturing method thereof
JP2901444B2 (en) Semiconductor device and manufacturing method thereof
JP4913336B2 (en) Semiconductor device