JPH11307587A - Manufacture of chip-size package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a chip-size package, which is able to provide a large amount of the chip size packages at the more inexpensive cost. SOLUTION: The manufacturing method of a chip-size package comprises the processes for preparing a work 3 made of a semiconductor device, wherein a plurality of integrated circuits are formed and a bump for external connection is formed on an external connecting pad, the process, which applies liquid sealing material on the bump-forming surface of the work 3, a process, which laminates a flexible wiring substrate 2 on the resin applied surface of the work, a process, which performs flip-chip connection to the work 3 by heating and compression, and the process, which cuts out the semiconductor package from the work at the individual integrated-circuit unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a package having substantially the same area as a semiconductor device, that is, a chip size package (CSP).

[0002]

2. Description of the Related Art Generally, a semiconductor device is mounted on a flip-chip by positioning a bump 11 of an individual flip-chip element 1 on which a bump has been formed, with an electrode 21 of a wiring board 2 as shown in FIG. The flip chip element 1 is mounted on a printed circuit board 2 and the solder is melted by reflow to complete the flip chip connection. At this time, the solder may be the bump itself or may be a solder pre-coated on the substrate side. The element 1 mounted on the substrate 2 in this manner is provided with an underfill material for the purpose of reducing the small stress applied to the bump 11, protecting the element 1 from external humidity and impact, and ensuring sufficient reliability. Liquid material 5a called
Is injected between the element 1 and the substrate 2. In the figure, reference numeral 5b denotes a liquid material injection device.

[0003] The underfill material has the following problems because it is filled in the gap between the chip and the substrate by utilizing the capillary phenomenon. Since the gap is small, a long time is required for filling and the productivity is low. Depending on the bump pattern, air may be trapped in the void 51 (see FIG. 7) to reduce the reliability.

In some cases, a large chip cannot be completely sealed and cannot be sealed. In order to fill in a short time, it is necessary to use a resin having a low viscosity.Therefore, a resin having a low filler content and not having sufficient physical properties such as heat resistance which has an important effect on reliability has to be used. Not get. As a result, the sealing reliability is unsatisfactory.

[0005] The total mounting process is complicated and the cost is higher than the wire bonding method. Improvements have been strongly demanded for these problems. That is, a sealing material that can exhibit high reliability without containing voids and the like with high productivity,
The emergence of a sealing method is desired.

In order to solve this problem, a so-called "non-flow" type underfill method has been proposed in which a liquid resin serving as an underfill material is preliminarily applied to the substrate side and the semiconductor element is positioned from above. I have. According to this method, a certain improvement effect can be obtained for the above-mentioned drawbacks. However, if the above-described alignment and the amount of applied resin are not strictly controlled, inconveniences such as the resin overflowing from under the semiconductor element occur, and the process becomes difficult. It was still unsatisfactory in terms of simplification.

[0007] Such a problem in the mounting technology is desired to be solved not only in the bare chip mounting on the module substrate but also in the packaging in the CSP.

[0008]

The object of the present invention is to provide a CS
It is an object of the present invention to provide a method of manufacturing a chip size package that can provide P in large quantities and at lower cost.

[0009]

In order to solve the above-mentioned problems, a method of manufacturing a chip-size package according to the present invention includes forming a plurality of integrated circuits, and forming external connection bumps on external connection pads. Step (i) of preparing a work made of the formed semiconductor substrate, step (ii) of applying a liquid sealing material to the bump forming surface of the work, and laminating a flexible wiring board on the resin applied surface of the work Step (iii) and heating and laminating the work after lamination.
Performing a flip-chip connection by applying pressure and gelling the liquid sealing material (iv), and cutting out a chip-size package from the work after flip-chip connection in individual integrated circuit units (v). Including.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method of manufacturing a chip size package according to the present invention, as shown in FIG. 1, a step of preparing a work 3 made of a semiconductor substrate having a bump forming surface.
(i), a step (ii) of applying a liquid thermosetting resin 32 as a sealing material to the bump forming surface of the work 3, and a step (iii) of laminating the flexible wiring board 2 on the resin applied surface of the work 3 A step (iv) of performing flip-chip connection to the work 3 after lamination by heating and pressurizing, and a step (v) of cutting out a chip size package B from the work 3 after the flip-chip connection in individual integrated circuit units. including.
In this case, the workpiece 3 may be used as it is, or may be a workpiece that has been previously diced (half-cut) in which an incision is made halfway in an individual element unit as shown in a dashed-dotted circle in the figure. .

Hereinafter, this will be described in detail. [Semiconductor Substrate Work Preparation Step (i)] The work used in the method of the present invention comprises a semiconductor substrate in which a plurality of integrated circuits are formed and external connection bumps are formed on external connection pads. As such a work, a silicon wafer (a wafer on which a circuit has been formed) obtained after the integrated circuit forming step is most preferable in terms of productivity, although not limited thereto. However, the wafer may be cut into several pieces depending on the size of the flexible wiring board 2 and the like. In short, it is important and necessary to manufacture a chip-size package in units of a plurality of integrated circuits instead of individual integrated circuit elements as in the conventional method.
In the description below, the work is basically described by using a wafer as a representative, but a work that is not a wafer itself can be substantially similarly described.

There is no limitation on the method and material for forming the bumps on the work. For example, solder or gold is used as a known material for the bumps. As solder bumps,
For example, a so-called C formed through a barrier metal
Four bumps, those formed by a stud bump method using solder wires, those formed by a plating method, and the like are used. As the gold bump, a bump formed by a stud bump method or a plating method is used. [Liquid encapsulant coating step (ii)] Examples of the liquid encapsulant used here include a liquid thermosetting resin used for a conventional underfill material. It is a resin for ensuring the properties. The liquid sealing material such as a thermosetting resin is a resin that is liquid at room temperature and has a melt viscosity of 10 to 1000 poise at room temperature, has good flow characteristics when applied, and entraps air around bumps. This is preferable in that no voids are generated.

The layer of the thermosetting resin 32 is formed, for example, by coating. The coating may be performed at room temperature or under heating. Although the thickness is not particularly limited, the height is arbitrarily selected depending on the height of the bump (generally, 30 to 120 μm, but the shape and material of the bump, and further, the material of the electrode to be joined). -30 μm to +20
It is preferable that the film is formed as uniformly as possible in the range of μm. If the coating thickness is too thin, voids are formed around the bump periphery at the time of bump connection, and the sealing reliability is reduced. If the coating thickness is too large, the connection between the bump and the substrate electrode becomes insufficient due to the pressure applied during the connection of the bump, resulting in poor connection reliability.

The application of the thermosetting resin 32 is performed by ordinary means. Specific examples include screen printing,
This is a method of applying a liquid resin by a roller coating method, a curtain coating method, a doctor blade method, a dispenser method, a spin coating method, or the like. [Laminating step (iii)] Although there is no limitation on the structure of the flexible wiring board 2 used in this case, in view of the object of the present invention of producing a chip size package at low cost, the solder ball mounting portion is pre-drilled. (Those indicated by reference numeral 29 in FIG. 2 are through holes formed by drilling), and a single-sided plate having a circuit portion on the element side is preferable. In order to withstand the temperature in the flip chip connection step, the film substrate of the flexible wiring board is preferably a polyimide film. In order to insulate the element and the circuit, it is preferable that the circuit not connected to the flip chip is protected by the coverlay layer.

In order to perform the solder melting for the flip-chip connection with the solder on the flexible wiring board 2 side and to further improve the reliability of the solder connection, at least the flip-chip connection portion of the surface circuit portion is required. It is preferable that the solder is pre-coated. Solder pre-coating can be performed, for example, by an SSD method such as a super solder method or a super Jafit method, in addition to a solder plating method or a solder dip method.

If the flexible wiring board 2 is continuously supplied from a take-up reel and is continuously transferred to the subsequent steps, it is possible to make the chip size package production continuous (reel-to-reel). Therefore, further cost reduction can be realized. In this case, continuous continuation is good, but after winding once, after-curing, ball mounting, and punching may be performed.

The flexible wiring board 2 is laminated with its connection portions aligned with the bumps of the semiconductor element. The lamination is preferably performed under reduced pressure to prevent air bubbles from being entrained. The reduced pressure condition is, for example, 500 Torr or less, preferably 100 Torr or less. If the degree of pressure reduction is insufficient, voids may be involved during connection, and sealing reliability may be reduced. [Flip Chip Connection Step (iv)] After lamination, electrical connection between the semiconductor circuit and the wiring board circuit is performed by flip chip connection. Flip chip connection is performed by, for example, a method of melting solder bumps, a method of connecting a gold bump and a solder precoat by melting a solder precoat, a method of mechanically connecting a gold bump by pressure, a method of connecting with a silver paste, and the like. . In the present invention, from the viewpoint of connection reliability, it is preferably achieved through a solder melting process. As the solder melting method,
Although there is a method of melting the solder using solder reflow, in the present invention, the sealing material is already filled in a laminated state, and the connection reliability is reduced by the solder reflow method. It is necessary to perform flip chip connection by pressure and heating. This pressurization / heating is performed by a method such as using a bonder.

This step will be described in detail with reference to FIG. This step (flip chip bonding) is characterized by flip chip connection by bumps by heating while applying pressure. This will be described in order. First, in the above-described process, the bumps 11 of the work 3 and the connection electrodes 21 on the flexible wiring board 2 are aligned so as to face each other. Heating is performed while applying pressure as indicated by thick arrows. Pressurization condition is
Although not particularly limited, it is preferable to be about 0.1 to 100 g per bump. After the contact between the bump 11 and the substrate electrode 21 is completed, the electrical connection is completed by melting the solder by further raising the temperature or the like. In the molten solder state, it is substantially unnecessary to apply pressure and it is preferable to keep the clearance constant. However, if necessary, the pressure may be continued.

In the present invention, the thermosetting resin layer has reached a gelled state due to the heating during the above-described series of flip chip connections. If the gelled state has not been reached, the required reliability cannot be obtained or a problem will occur in a later step. The requirements to reach the gel state are resin composition, heating temperature,
The optimum conditions are not unique because they depend on the heating time and the like.

The flip chip connecting step of the present invention is preferably performed under reduced pressure. This is because voids caused by contact between the bump coating resin layer and the substrate surface can be reduced. Decompression condition is 500 Torr or less, preferably 100 To
rr or less. If the pressure reduction is insufficient, a void may be involved at the time of connection, and the sealing reliability may decrease.

In the case where the thermosetting resin has not reached the gelled state only by pressurizing and heating at the time of flip chip connection,
After the flip chip connection step, after-curing of the sealing material resin is performed.Even when the gelling state is reached, after-curing may be performed to further enhance the effect of fixing the bumps by the sealing resin. preferable. The curing conditions and after-curing conditions are not limited, but are usually from 100 to 160 ° C. for 30 minutes to 3 hours. [Chip size package cutting process (v) Other processes]
Through the above steps, a work in which a plurality of integrated circuits are collectively connected to the flexible wiring board is obtained. The step of cutting the work into packages for each element and the step of forming solder balls for external connection are continuously performed.
There is no limitation on the order of these two steps, and either one may be performed first and the other performed later, and if possible, both steps may be performed simultaneously.

As a chip size package, usually,
Solder balls are attached in consideration of reliability during mounting.
The solder ball mounting step can be performed by a known method. In the step of cutting into individual package units, a method using a so-called mechanical cutting machine such as a tying saw or a diamond cutter and a cutting method using a laser are performed individually or in combination.

FIG. 3 is a sectional view of a CSP obtained by the method of manufacturing a chip size package according to the present invention. The method of manufacturing a chip size package according to the present invention includes forming an external connection bump on an external connection pad of a semiconductor substrate on which a plurality of integrated circuits are formed, applying a liquid sealing material to the bump formation surface, Since the wiring board is laminated,
A plurality of chip size packages can be formed at once using a semiconductor substrate having a plurality of integrated circuits. Since individual packages can be formed by cutting out the substrate, it is possible to greatly simplify the process, and it becomes unnecessary to fill an underfill material at the time of mounting, thereby achieving high reliability. Enables flip-chip connection.

As shown in FIG. 3, in the chip size package B obtained in the above process, external connection bumps are formed on external connection pads of a semiconductor substrate on which a plurality of integrated circuits are formed. Is formed with a thermosetting resin layer. The bump of this semiconductor element is
Is flip-chip connected to the semiconductor connection electrode pattern 21 formed on the surface of the substrate. Solder ball connection pads are provided on the back surface of the wiring board 2, and these are electrically connected to the semiconductor connection pattern 21 through through holes (indicated by reference numeral 29 in FIG. 2) of the flexible wiring board 2. .

Reference numeral 12 in the figure indicates a thermosetting resin layer for sealing. By using the method of manufacturing a chip size package developed by the present inventors, the entire CSP manufacturing process can be simplified and the cost can be reduced. -Specific Example of Chip Size Package Manufacturing Process- FIGS. 4 and 5 show a continuous type manufacturing example. FIG. 4 shows the entire structure, FIG. 5A shows a part of a cross section of the coater, and FIG.
(B) shows an enlarged portion from the coater to the laminate. Wafer 3 with bumps on the rightmost preparation table
Are successively transferred onto a constant speed conveyor 82 by a suction type hoist 81. The constant speed conveyor 82 is installed in the guide groove 61. In the guide groove 61, the wafer 3 with bumps flows on the constant-speed conveyor 82 one after another. First, the coater 62 is supplied with the liquid thermosetting resin 32 supplied from the hopper H.
Is applied to the bump formation surface of the wafer 3. On the downstream side, the flexible wiring board 2 to which the laminating roll 63 is continuously supplied from the reel R is laminated on the thermosetting resin coating layer of the wafer 3. Further downstream,
The cutter 85 cuts out the flexible wiring board 2. After further heating and pressurizing, the cutter 64 cuts out the individual chip size package B to obtain a final product.

FIG. 6 shows a production example of a batch type. The suction type hoist 71 transfers the bumped wafers 3 placed on the rightmost preparation table to the coating preparation table one after another. Coater 72
Applies the thermosetting resin 32 supplied from the hopper H to the bump forming surface of the wafer 3. The suction type hoist 73 transfers the coated wafer 3 to the lamination preparation table one after another. Then, the flexible wiring board 2 supplied from the reel R by the laminating roll 74 is laminated on the thermosetting resin coating layer of the wafer 3. Finally, the cutter 75 cuts out the flexible wiring board 2. After further heating and pressurizing, an individual chip size package B is cut out to obtain a final product.

[0027]

The present invention will be described in more detail with reference to the following examples. -Example 1- An aluminum wiring pattern on the surface layer and one element unit is 8 × 9
4 inch (4 mm)
inch) A silicon wafer was prepared. Each element on this wafer had 160 external connection eutectic solder bumps on the external connection pads at four peripheral portions, and the solder bump height was 70 μm. The solder bump is formed by forming a solder stud bump at 80 μmφ using a 30 μmφ solder wire and performing a flattening process to a height of 70 μm. Dicing this wafer,
24 mm x with 30 element units in 3 rows x 10 rows
A 90 mm work was cut out.

On the other hand, a 0.3 mmφ hole was previously drilled in the solder ball mounting portion of the final package using a polyimide material as a base, and a flexible wiring board having a width of 35 mm was manufactured through a normal TAB process. On the circuit surface of this flexible wiring board, the circuit part other than the part to be flip-chip connected is covered and protected with a coverlay layer made of polyimide-based resist, and the circuit part to be flip-chip connected is solder pre-coated (Super Jafit method, (Thickness: 20 μm).

A commercially available underfill material CV5183F (liquid thermosetting resin at room temperature, manufactured by Matsushita Electric Works, Ltd.) was roller-coated on the bump forming surface of the work. When the coating thickness was measured, it was in the range of 70 to 120 μm, and the average value was 80 μm. Underfill material coated work and flexible wiring board
Laminating was performed while aligning with the AB sprocket guide. During this time, excess resin was extruded backward through a clearance roll.

The obtained laminate is pressed at 140 ° C. under a pressure of 5 g / bump using a bonding apparatus capable of pressing a parallel plate.
The solder bump was brought into contact with the substrate side electrode by heating and pressing for 0 seconds to press the solder bump against the substrate side electrode. Heating was performed at 220 ° C. for 30 seconds while maintaining the clearance in this contact state. By this operation, the thermosetting sealing resin layer was in a gel state. The whole was put in a dryer at 150 ° C. for 2 hours, and after-cured. After forming a 0.3mmφ solder ball on the obtained product surface using a ball mounter,
The CSP was obtained by cutting into individual chip size packages using a diamond cutter. Each CSP
Was electrically tested and all flip chip connections were normal.

Example 2 A CSP was obtained in the same manner as in Example 1, except that the step of forming solder balls with a ball mounter was performed after individual cutting with a diamond cutter. Example 3 24 mm diced as a work in Example 1
Use a 4-inch wafer as it is in place of the × 90mm one, and use a through-hole type double-sided flexible circuit board instead of the polyimide-based flexible wiring board, apply underfill, and stack the flexible circuit boards. A CSP was obtained in the same manner as in Example 1 except that the thickness control and lamination were performed simultaneously using a roller.

Example 4 A 25 μm Au wire was used instead of the bump forming method of Example 1, the bump diameter was 60 μm, and the bump height after the flattening treatment was 60 μm. CSP was obtained. -Example 5-A CSP was obtained in the same manner as in Example 1 except that the substrate side was not solder precoated and the connection temperature was changed from 220 ° C to 280 ° C.

Example 6 The procedure of Example 1 was repeated, except that the resin coating thickness was changed from 40 μm to 90 μm and the average value was changed to 50 μm by changing the roller coating conditions.
P was obtained. The average value of this coating thickness of 50 μm is
It is -20 μm with respect to the solder bump height (70 μm).

Example 7 In the same manner as in Example 1, except that the resin coating thickness was changed to 80 μm to 130 μm and the average value to 90 μm by changing the roller coating conditions,
CSP was obtained. Average value of this coating thickness 90μm
Is +20 μm with respect to the solder bump height (70 μm)
Met.

Example 8 In Example 3, the lamination by a roller was performed for 100 hours.
A CSP was obtained in the same manner as in Example 3 except that the CSP was performed under reduced pressure of Torr. Table 1 shows the results of the electrical connection check performed on the effective CSPs (partial CSPs that were not subjected to the bad mark in the initial wafer stage) obtained in Examples 1 to 8 above. This electrical connection check
By checking the connection of the bumps, it was determined that the bumps were non-defective on the basis that all the formed bumps were conducting as designed.

[0036]

[Table 1]

In Table 1, the better the number of non-defective products is closer to the number of effective CSPs, the better the package is, and the best package is the same as the effective CSP.

[0038]

According to the first to eleventh aspects of the present invention, a plurality of integrated circuits are collectively processed in manufacturing a chip size package. The package can be manufactured with high productivity and high yield.

According to the third aspect of the present invention, in addition to the above-described effects, an effect that the production cost can be further reduced can be obtained. According to the fifth to eighth aspects of the present invention, in addition to the above-described effects, an effect is obtained that a highly reliable and high-quality chip size package can be obtained.
According to the invention of claim 8, in particular, there is obtained an effect that the gap between the semiconductor substrate and the flexible wiring board is more reliably sealed, and furthermore, it is difficult to cause a poor electrical connection between the bump and the substrate electrode. Can be

According to the eleventh aspect of the present invention, in addition to the above effects, an effect that a chip size package can be manufactured efficiently can be obtained.

[Brief description of the drawings]

FIG. 1 is a process chart illustrating an embodiment of a method for manufacturing a chip size package according to the present invention.

FIG. 2 is a side sectional view showing a flip chip process in the present invention.

FIG. 3 is a sectional view showing a specific example of a chip size package obtained by the present invention.

FIG. 4 is a process chart showing a specific example of the present invention.

FIG. 5 is a front sectional view (a) and a side sectional view (b) of the specific example.

FIG. 6 is a process chart showing another specific example of the present invention.

FIG. 7 is a side sectional view showing a conventional method for mounting a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor element 11 Bump 12 Thermosetting resin layer 2 Flexible wiring board 21 Electrode 3 Work consisting of a semiconductor substrate

Claims (11)

[Claims] A step of preparing a work comprising a semiconductor substrate on which a plurality of integrated circuits are formed and having external connection bumps formed on external connection pads; and (i) preparing a work on a bump formation surface of the work. Step of applying liquid sealing material
(ii), a step (iii) of laminating a flexible wiring board on the resin-coated surface of the work, and performing a flip-chip connection by heating and pressurizing the work after lamination, and gelling the liquid sealing material. (Iv), and a step (v) of cutting out a chip size package in individual integrated circuit units from the work after flip chip connection,
And a method for manufacturing a chip size package. 2. The method according to claim 1, further comprising a step of mounting a solder ball after the step (iv) and before the step (v). 3. The method according to claim 1, wherein said workpiece is a silicon wafer itself obtained after an integrated circuit forming step. 4. The method for manufacturing a chip-size package according to claim 1, wherein a single-sided board in which a solder ball mounting portion is pre-drilled is used as the flexible wiring board. 5. The chip size package according to claim 1, wherein a circuit other than a portion to be flip-chip connected in a surface circuit portion of the flexible wiring board is protected by a coverlay layer. Production method. 6. The method of manufacturing a chip-size package according to claim 1, wherein at least a portion of the surface circuit portion of the flexible wiring board where flip-chip connection is to be performed is pre-coated with solder. . 7. The method according to claim 1, wherein the average coating thickness of the liquid sealing material is in the range of −30 μm to +20 μm with respect to the bump height.
7. The method for manufacturing a chip-size package according to any one of items 1 to 6. 8. The method according to claim 1, wherein the lamination of the flexible wiring board is performed under reduced pressure. 9. The method according to claim 1, wherein the flip-chip connection is achieved by melting solder. 10. The liquid sealing material applied is gelled by heating and pressing in the flip chip connecting step.
10. The method for manufacturing a chip size package according to any one of items 1 to 9. 11. The laminating step (iii), wherein the flexible wiring substrate is continuously supplied from a take-up reel and is continuously transferred to a subsequent step.
0. The method for manufacturing a chip size package according to any one of 0 to 0.