JPH11307539A - Semiconductor protecting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor protective region which is integrated on a semiconductor substrate forming a semiconductor integrated circuit, while having high surge voltage resistance. SOLUTION: An (n) collector region 2 is formed on the surface layer of a (p) substrate 1, a (p) base region 3 is formed on the surface layer of the (n) collector region 2, an (n) emitter region 4 is formed on the surface layer of the (p) base region 3, a (p) base pick-up region 5 is formed away from the (n) emitter region 4 on the surface layer of the (p) base region 3, an (n) collector pick-up region 6 is formed away from the (p) base region 3 on the surface layer of the (n) collector region 2, a (p) substrate pickup region 7 is formed away from the (p) collector region 2 on the surface layer of the (p) substrate 1, the (n) emitter region 4 and the (p) base pick-up region 5 are connected to an output terminal 12, the (n) collector pick-up region 6 is connected to a power supply terminal 13, and the (p) substrate pick-up region 7 is connected to a GND terminal 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor protection element for protecting a semiconductor device such as a semiconductor integrated circuit from a surge voltage such as static electricity.

[0002]

2. Description of the Related Art As a semiconductor protection device for protecting a semiconductor integrated circuit from a surge voltage, a method in which a deep junction pn diode is formed in a semiconductor substrate on which a semiconductor integrated circuit is formed, and the diode is used as the semiconductor protection device. And C
MOSFET that composes MOS (complementary MOSFET)
And the like, using a parasitic diode as a semiconductor protection element. In addition to the above, there is a method of externally attaching a surge voltage absorbing chip separately from a semiconductor substrate forming a semiconductor integrated circuit. This external method is useful for absorbing a surge voltage (static electricity) of a high voltage of about 6 kV.

FIG. 7 is an example of a conventional semiconductor protection element, and is a cross-sectional view of a main part of the element. In this example, a CMOS integrated circuit including a CMOS circuit is formed on a semiconductor substrate.
This is a case where a semiconductor protection element is formed by a process. A p-well region 102 and an n-well region 103 are formed on a surface layer of a p-substrate 101, and n-well region 103 is formed on a surface layer of the p-well region 102.
⁺ Source region 104, n ⁺ drain region 105 and p
^{+ A} pickup area 106 is formed. Further, p ⁺ source region 108, p ⁺ drain region 109 and n ⁺ pickup region 110 are formed in the surface layer of n well region 103. n ⁺ source region 104 and n ⁺ drain region 10
The gate oxide film 13 is formed on the p-well region 102
The nMOS gate electrode 107 is formed with 1 therebetween.
Further, the p ⁺ source region 108 and the p ⁺ drain region 109
Gate oxide film 132 on n-well region 103 sandwiched between
, A pMOS gate electrode 111 is formed.

A drain electrode 122 of an nMOS and a drain electrode 125 of a pMOS are formed on the n ⁺ drain region 105 and the p drain region 109. This nMO
S drain electrode 122 and pMOS drain electrode 12
5 is connected to the output terminal 112. Further, a p ⁺ pickup electrode 123 and a source electrode 121 of an nMOS are formed on the p ⁺ pickup region 106 and the n ⁺ source region 104. The p ⁺ pickup electrode 123, the source electrode 121 of the nMOS, and the gate electrode 107 of the nMOS are connected to the GND terminal 113.

[0005] In addition, the n ⁺ pickup region 110 and p
⁺ N ⁺ pickup electrode 126 on source region 108
And a pMOS source electrode 124 is formed. The n ⁺ pickup electrode 126, the source electrode 124 of the pMOS, and the gate electrode 111 of the pMOS are connected to the power supply terminal 114. Note that nMOS is an n-channel MOSFET,
pMOS is a p-channel MOSFET. CMOS (complementary MOSFET) using this nMOS and pMOS
Are formed, and the p-well region 102 and the n ⁺
The semiconductor protection element is constituted by a pn diode formed by a pn junction of the drain region 105 and a pn diode formed by a pn junction of the n-well region 103 and the p ⁺ drain region 109.

FIG. 8 is a diagram for explaining the operation of the semiconductor protection device of FIG. For example, several hundred
It is assumed that a surge voltage of 0 V (such as a surge voltage due to static electricity) is applied. Since the voltage between the power supply terminal 114 and the GND terminal 113 is more than ten volts, the potential of the output terminal 112 may be at the ground potential for a surge voltage of several thousand volts.

When a positive surge voltage is introduced into the output terminal 122, a current 142 caused by the surge voltage is generated.
Flows from the output terminal 112 to the n ⁺ pickup region 110 through the pn diode 122 formed by the p ⁺ drain region 109 and the n-well region 103, and the power supply terminal 11
Flows out from 4 On the other hand, when a negative surge voltage is introduced, the current 14
1 is a p ⁺ pickup area 10 from the GND terminal 113
6 and p well region 102 and n ⁺ drain region 105
Flows to the drain electrode 122 through the pn diode 121 formed by the above, and flows out from the output terminal 112 to the outside.
Thus, when the surge voltage is introduced into the semiconductor integrated circuit, the current 1 due to the surge voltage is applied to this semiconductor protection element.
The surge voltage is absorbed by energizing 41 and 142.

[0008]

However, miniaturization of a semiconductor integrated circuit is progressing year by year, and when a semiconductor protection element is formed on the same semiconductor substrate as a semiconductor integrated circuit by a miniaturized CMOS process, manufacturing cost and cost are reduced. While this is advantageous in the manufacturing process, the diffusion depth of the source region and the drain region of the MOSFET constituting the CMOS becomes smaller.

Accordingly, the n ⁺ drain region 1
The diffusion depth of 05 and p ⁺ drain region 109 becomes shallow, the curvature of the pn junction to form a pn diode 121 and 122 radially decreases. When the radius of curvature is small, the current flowing due to the surge voltage tends to concentrate on the curvature portion, and the semiconductor protection element is broken. In particular, the human body mode high electrostatic breakdown withstand voltage (an example of the withstand voltage test conditions: applied voltage of 6 kV, capacitor capacity of 100 pF, and limiting resistance of 1.5 kΩ), which is a severe withstand voltage among surge voltage withstand voltages, is reduced. In addition, when the surge voltage absorbing chip is externally attached as described above, the number of components increases and the manufacturing cost increases.

[0010] An object of the present invention is to solve the above-mentioned problems, and to be integrated on a semiconductor substrate forming a semiconductor integrated circuit,
An object of the present invention is to provide a semiconductor protection element having a large surge voltage resistance.

[0011]

In order to achieve the above-mentioned object, a second conductive layer is selectively formed on a surface layer of a semiconductor substrate of a first conductivity type.
Forming a first region of a conductivity type, selectively forming a second region of the first conductivity type on a surface layer of the first region, and forming a third region of a second conductivity type on a surface layer of the second region; , The semiconductor substrate is GN
It is configured to be connected to a D (ground) terminal, the first region is connected to a power terminal, and the second region and the third region are connected to an output terminal.

A first conductivity type substrate pickup region is selectively formed on the surface layer of the semiconductor substrate of the first conductivity type separately from the first region, and selectively formed on the surface layer of the first region separately from the second region. A collector pickup region of the second conductivity type, a base pickup region of the first conductivity type selectively formed on the surface layer of the second region separately from the third region, and a substrate pickup electrode on the substrate pickup region. Forming a collector pickup electrode on the collector pickup area,
An emitter electrode is formed on the third region, a base-up electrode is formed on the base pickup region, a substrate pickup electrode is connected to a GND (ground) terminal, a collector pickup electrode is connected to a power supply terminal, and the emitter electrode and the base are connected. It is preferable that the up electrode be connected to the output terminal.

With the above configuration, even when the diffusion depth of the third region (that is, the emitter region) is small, the pn diode formed by the second region and the third region and the first region, the second region, The transistor formed in the third region can absorb a high surge voltage. A first region of the second conductivity type is selectively formed on a surface layer of the semiconductor substrate of the first conductivity type, and a second region of the first conductivity type is selectively formed on a surface layer of the first region.
Forming a region, forming a third region of the second conductivity type on the surface layer of the second region, and selectively forming a fourth region of the second conductivity type on the surface layer of the semiconductor substrate apart from the first region; And selectively forming a fifth region of the first conductivity type on the surface layer of the fourth region, connecting the semiconductor substrate and the fifth region to a GND (ground) terminal, and connecting the first region to a power supply terminal. , Second area, third
It is preferable that the region and the fourth region be connected to the output terminal.

A substrate pick-up region of the first conductivity type is selectively formed on the surface layer of the semiconductor substrate of the first conductivity type separately from the first region, and selectively formed on the surface layer of the first region separately from the second region. A collector pickup region of the second conductivity type, a base pickup region of the first conductivity type selectively formed on the surface layer of the second region separately from the third region, and a fifth region on the surface layer of the fourth region. Selectively forming a sixth region of the second conductivity type apart from the region, forming a substrate pickup electrode on the substrate pickup region, forming a collector pickup electrode on the collector pickup region, and forming an emitter electrode on the third region Is formed, a base-up electrode is formed on the base pickup region, a first electrode is formed on the fifth region, a second electrode is formed on the sixth region, and the substrate pickup electrode and the first electrode are connected to GND ( ground Connected to a terminal, it may connect the collector pickup electrodes to the power supply terminal, a configuration for connecting the emitter electrode and the base-up electrode and the second electrode to the output terminal.

With the above configuration, even if the diffusion depth of the fifth region is small, the diode formed by the fourth region and the fifth region can absorb a high surge voltage. It is preferable to form a CMOS circuit (an integrated circuit composed of a plurality of complementary MOSFETs) on the surface layer of the semiconductor substrate of the first conductivity type. By forming the CMOS circuit and the semiconductor protection element on the same semiconductor substrate, the number of components can be reduced as compared with the case where the semiconductor protection element is externally mounted.

[0016]

FIG. 1 shows a first embodiment of the present invention.
It is principal part sectional drawing of a semiconductor protection element. The specific resistance is 15Ω
cm, a surface concentration of 3 × 10 ¹⁶ c
An n collector region 2 having a depth of about m ⁻³ and a diffusion depth XJ of about 4 μm is formed. A p base region 3 having a surface concentration of about 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth XJ of about 1 μm is formed in the surface layer of the n collector region 2. An n emitter region 4 having a surface concentration of about 1 × 10 ²¹ cm ⁻³ and a diffusion depth XJ of about 0.2 μm is formed in the surface layer of the p base region 3. The surface concentration and the diffusion depth Xj are the same as the manufacturing conditions for forming a miniaturized CMOS circuit. The semiconductor protection element is formed in a surface layer of a semiconductor substrate (here, p substrate 1) on which a CMOS circuit is formed by a CMOS process.

On the surface layer of the p base region, a p base pickup region 5 is formed apart from the n emitter region 4, and on the surface layer of the n collector region 2, an n collector pickup region 6 is formed on the surface layer of the p base region 3. To form a p-substrate 1
The p substrate pickup region 7 is formed on the surface layer of the substrate, away from the p collector region 2. An emitter electrode 8 is formed on the n-emitter region 4 and a p-type
The base pickup electrode 9 is formed, the n-collector pickup electrode 10 is formed on the n-collector pickup area 6, and the p-substrate pickup electrode 11 is formed on the p-substrate pickup area 7.

The emitter electrode 8 and the p base pickup electrode 9 are connected to an output terminal 12, the n collector pickup electrode 10 is connected to a power supply terminal 13, and the p substrate pickup electrode 11 is connected to a GND (ground) terminal 14.
The output terminal 12, the power supply terminal 13, the GND terminal 1
Reference numeral 4 is a terminal used in a CMOS circuit. The electrodes 8, 9, 10, and 11 are often connected to the terminals 12, 13, and 14 via bonding pads (not shown).

The operation of the semiconductor protection device will be described below. FIG. 2 is a diagram for explaining the operation when a positive voltage pulse is applied to the output terminal of the semiconductor protection device of FIG. The pn diode 21 formed by the p base region 3 and the n collector region 2 is forward biased, and the current 41 flows from the p base pickup region 5 to the n collector pickup region 6 as shown by an arrow. When the current 41 flows, the surge voltage is absorbed.

FIG. 3 is a diagram for explaining the operation when a negative voltage pulse is applied to the output terminal of the semiconductor protection device of FIG. The applied voltage is clamped by the collector-emitter breakdown voltage BVCEO of the npn transistor 22 composed of the n-emitter region 4, the p-base region 3 and the n-collector region 2, and is formed by the p-base region 3 and the n-collector region 2. The pn junction of the pn diode 21 breaks down, and a breakdown current 42 indicated by an arrow flows.
As shown in the figure, by forming an n-collector pickup region 6 on the opposite side of the p-base pickup region 7 across the n-emitter region 4, the parasitic resistance 23 (lateral resistance) of the p-base region 3 is reduced. The breakdown current 42 flows, and a voltage drop occurs in the parasitic resistance 23.

Due to this voltage drop, the pn junction of the n-emitter region 4 and the p-base region 3 is forward-biased, electrons are injected from the n-emitter region 4 into the p-base region 3, and the npn transistor 22 operates. When the npn transistor 22 operates, a collector current 43 flows from the n collector region 2 to the n emitter region 4 through the p base region 3. The collector current 43 is a product of the breakdown current 32 and the current amplification factor of the npn transistor 22, and is a large current. Therefore, by flowing this large current, the surge voltage is absorbed.

FIG. 4 is a sectional view of a main part of a semiconductor protection device according to a second embodiment of the present invention. The npn transistor section is the same as that of FIG. 1 and differs from FIG. 1 in that a semiconductor protection element unit composed of a Zener diode is formed on the surface layer of p substrate 1 sandwiched between n collector region 2 and p substrate pickup region 7. Surface concentration of 3 × 10 ¹⁸ c on the surface layer of p substrate 1
m ^-3 about the diffusion depth XJ forms the n cathode region 31 of about 2.5 [mu] m, the surface layer of the n cathode region 31, 1 × 10 ²⁰ cm ^-3 about the surface concentration, the diffusion depth XJ 0 .4
A p-anode region 32 is formed with a thickness of μm. Since this pn junction has a high surface concentration, it becomes a Zener junction. On the surface layer of n cathode region 31, n cathode pickup region 33 is formed apart from p anode region 32. The anode electrode 34 and the n-cathode pickup electrode 3 are formed on the p-anode region 32 and the n-cathode pickup region 33.
5 is formed. The n cathode pickup electrode 35 and the output terminal 36 are connected, and the anode electrode 34 and the GND terminal 37 are connected.
Connect.

The Zener diode formed by the n-cathode region 31 and the p-anode region 32 serves as a semiconductor protection device unit. The npn transistor formed on the surface layer of the n-collector region 2 also has the same structure as the semiconductor protection device unit. Becomes A semiconductor protection element is formed from these two units. Next, the operation of the semiconductor protection device will be described.

FIG. 5 is a diagram for explaining the operation when a positive voltage pulse is applied to the output terminal of the semiconductor protection device of FIG. The Zener diode 41 is reverse-biased, but is clamped by the Zener voltage, and the surge voltage is absorbed by the Zener current 51. FIG. 6 is a diagram for explaining the operation when a negative voltage pulse is applied to the output terminal of the semiconductor protection device of FIG.

The Zener diode 41 is forward biased, and the surge voltage is absorbed by the forward current 52. In this figure, the operation of the pnp transistor section is the same as that described with reference to FIGS. Naturally, when the operation of the pnp transistor section is added to the operation of the zener diode section and a surge voltage is applied, a large current flows through the semiconductor protection element, and the surge voltage is absorbed. By this operation, it is possible to obtain a semiconductor protection element having a high electrostatic breakdown strength in the human body mode.

[0026]

According to the present invention, finely processed CM
Even when a semiconductor protection element is formed on a semiconductor substrate under the same manufacturing conditions as a semiconductor integrated circuit having an OS circuit, a semiconductor protection element having a high surge voltage resistance can be obtained. In addition, a semiconductor integrated circuit that can withstand a human body mode high electrostatic breakdown resistance test can be provided. Further, by integrating the semiconductor protection element on the same semiconductor substrate as the semiconductor integrated circuit, an external surge voltage absorbing chip is not required, and the number of components can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor protection element according to a first embodiment of the present invention;

FIG. 2 is a diagram for explaining an operation when a positive voltage pulse is applied to an output terminal of the semiconductor protection device of FIG. 1;

FIG. 3 is a diagram for explaining an operation when a negative voltage pulse is applied to an output terminal of the semiconductor protection element in FIG. 1;

FIG. 4 is a sectional view of a main part of a semiconductor protection element according to a second embodiment of the present invention;

FIG. 5 is a diagram for explaining an operation when a positive voltage pulse is applied to an output terminal of the semiconductor protection element in FIG. 4;

FIG. 6 is a diagram for explaining an operation when a negative voltage pulse is applied to an output terminal of the semiconductor protection element in FIG. 4;

FIG. 7 is an example of a conventional semiconductor protection element, and is a cross-sectional view of a main part of the element.

FIG. 8 is a diagram for explaining the operation of the semiconductor protection device of FIG. 7;

[Description of Signs] 1 p substrate 2 n collector region 3 p base region 4 n emitter region 5 p base pickup region 6 n collector pickup region 7 p substrate pickup region 8 n emitter electrode 9 p base pickup electrode 10 n collector pickup electrode 11 p substrate pickup electrode 12 output terminal 13 power supply terminal 14 GND terminal 21 pn diode 22 pn diode 23 parasitic resistance 31 n cathode region 32 p anode region 33 n cathode pickup region 34 p anode electrode 35 n cathode pickup electrode 36 output terminal 37 GND terminal 41 Zener diode 51 Zener current 52 Forward current 61 Current 62 Breakdown current 63 Collector current 101 p substrate 102 p-well region 103 n-well region 104 n ⁺ source region 105 n ⁺ drain region 106 p ⁺ pickup region 107 nMOS gate electrode 108 p ⁺ source region 109 p ⁺ drain region 110 n ⁺ pickup region 111 pMOS gate electrode 112 output terminal 113 GND terminal 114 power supply terminal 121 pn Diode 122 pn diode 131 gate oxide film 132 gate oxide film 141 current 142 current

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 9, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

In order to achieve the above-mentioned object, a second conductive layer is selectively formed on a surface layer of a semiconductor substrate of a first conductivity type.
Forming a first region of a conductivity type, selectively forming a second region of the first conductivity type on a surface layer of the first region, and forming a third region of a second conductivity type on a surface layer of the second region; Forming, connecting the semiconductor substrate to a GND (ground) terminal, connecting the first region to a power terminal, connecting the second region and the third region to an output terminal, and connecting the first region to the second region. The breakdown current flowing through the junction with the region causes a voltage drop in the parasitic resistance of the second region below the third region, and the voltage drop forward-biases the junction between the second region and the third region, First
The transistor including the region, the second region, and the third region is configured to be conductive.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

A first conductivity type substrate pickup region is selectively formed on the surface layer of the semiconductor substrate of the first conductivity type, separately from the first region, and is selectively formed on the surface layer of the first region, separately from the second region. Forming a collector pickup region of the second conductivity type, selectively forming a base pickup region of the first conductivity type separately from the third region on a surface layer of the second region, and forming a substrate on the substrate pickup region; Forming a pick-up electrode; forming a collector pick-up electrode on the collector pick-up area; forming an emitter electrode on the third area; forming a base pick-up electrode on the base pick-up area;
It is preferable that a connection is made to a D (ground) terminal, the collector pickup electrode is connected to a power supply terminal, and the emitter electrode and the base pickup electrode are connected to an output terminal.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

With the above configuration, even when the diffusion depth of the third region (that is, the emitter region) is shallow, the pn diode formed by the second region and the third region, the first region, and the second region The transistor formed by the region and the third region can absorb a high surge voltage. Further, the first conductive type semiconductor substrate is selectively formed on the surface layer of the first conductive type semiconductor substrate.
Forming a region, selectively forming a second region of the first conductivity type on a surface layer of the first region, and forming a second region on the surface layer of the second region.
Forming a third region of a conductivity type, selectively forming a fourth region of a second conductivity type on the surface layer of the semiconductor substrate apart from the first region, and selectively forming a fourth region of the surface layer of the fourth region; Fifth of one conductivity type
Forming a region, and connecting the semiconductor substrate and the fifth region to GND.
(Ground) terminal, the first region is connected to a power supply terminal, the second region, the third region, and the fourth region are connected to output terminals, and a junction between the first region and the second region is connected. The flowing breakdown current causes a voltage drop in the parasitic resistance of the second region below the third region, and the voltage drop causes the junction between the second region and the third region to be forward-biased, so that the first region and the second region The transistor including the region and the third region is preferably turned on.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

A first conductivity type substrate pickup region is selectively formed on the surface layer of the semiconductor substrate of the first conductivity type separately from the first region, and is selectively formed on the surface layer of the first region separately from the second region. Forming a collector pickup region of the second conductivity type, selectively forming a base pickup region of the first conductivity type separately from the third region on a surface layer of the second region, and forming a surface pickup layer of the fourth region on the surface layer of the fourth region; Forming a sixth region of the second conductivity type selectively away from the fifth region, forming a substrate pickup electrode on the substrate pickup region, forming a collector pickup electrode on the collector pickup region, Forming an emitter electrode on the third region, forming a base pickup electrode on the base pickup region, forming a first electrode on the fifth region, forming a second electrode on the sixth region, Base A pickup electrode and the first electrode connected to the GND (ground) terminal, and connecting the collector pickup electrodes to a power supply terminal, the emitter electrode, may be configured to connect the base pick-up electrode and the second electrode to the output terminal.

Claims (5)

[Claims] A first region of a second conductivity type is selectively formed on a surface layer of a semiconductor substrate of a first conductivity type, and a second region of the first conductivity type is selectively formed on a surface layer of the first region. Forming a third region of the second conductivity type on the surface layer of the second region, connecting the semiconductor substrate to a GND (ground) terminal, connecting the first region to a power supply terminal, and connecting the second region and the second region. A semiconductor protection element, wherein the three regions are connected to an output terminal. 2. A first conductivity type substrate pick-up region is selectively formed on a surface layer of a semiconductor substrate of a first conductivity type separately from a first region, and separated from a second region on a surface layer of the first region. A collector pickup region of the second conductivity type is selectively formed, a base pickup region of the first conductivity type is selectively formed on the surface layer of the second region separately from the third region, and a substrate pickup is formed on the substrate pickup region. Forming an electrode, forming a collector pickup electrode on the collector pickup area,
An emitter electrode is formed on the third region, a base-up electrode is formed on the base pickup region, a substrate pickup electrode is connected to a GND (ground) terminal, a collector pickup electrode is connected to a power supply terminal, and the emitter electrode and the base are connected. 2. The semiconductor protection device according to claim 1, wherein the up electrode is connected to an output terminal. 3. A first region of a second conductivity type is selectively formed on a surface layer of a semiconductor substrate of a first conductivity type, and a second region of the first conductivity type is selectively formed on a surface layer of the first region. Forming a third region of the second conductivity type on the surface layer of the second region; and selectively forming a fourth region of the second conductivity type on the surface layer of the semiconductor substrate apart from the first region.
Forming a region, selectively forming a fifth region of the first conductivity type on a surface layer of the fourth region, connecting the semiconductor substrate and the fifth region to a GND (ground) terminal, and connecting the first region to a power terminal. And a second region, a third region, and a fourth region, and an output terminal. 4. A first conductivity type substrate pickup region is selectively formed on a surface layer of a semiconductor substrate of the first conductivity type, separately from the first region, and separated from the second region on a surface layer of the first region. A collector pickup region of the second conductivity type is selectively formed, a base pickup region of the first conductivity type is selectively formed on the surface layer of the second region separately from the third region, and formed on a surface layer of the fourth region. A sixth region of the second conductivity type is selectively formed apart from the fifth region, a substrate pickup electrode is formed on the substrate pickup region, a collector pickup electrode is formed on the collector pickup region, and a third region is formed on the third region. An emitter electrode is formed, a base-up electrode is formed on a base pickup region, a first electrode is formed on a fifth region, a second electrode is formed on a sixth region, and a substrate pickup electrode and a first electrode are formed. GND (Ground Connected to a terminal, a collector connected pickup electrodes to a power supply terminal, the semiconductor protection element according to claim 3, characterized in that to connect the emitter electrode and the base-up electrode and the second electrode to the output terminal. 5. An integrated circuit (CMOS) comprising a plurality of complementary MOSFETs on a surface layer of a semiconductor substrate of a first conductivity type.
5. The semiconductor protection device according to claim 1, wherein an integrated circuit is formed.