JPH11307462A - Chemical vapor deposition method whose process conditions are optimized - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a chemical vapor deposition method for forming a film wherein defect generation is restrained on a semiconductor wafer. SOLUTION: An inside of a deposition chamber is preliminarily stabilized by introducing gas which is chemically stable to a semiconductor wafer into a process chamber, while keeping the same process conditions as deposition process for depositing a specified matter on a semiconductor wafer. A matter is deposited on a semiconductor wafer by introducing raw gas to an inside of a deposition chamber which is preliminarily stabilized. As a result, defect of particle of a matter deposited on a semiconductor wafer is remarkably reduced and process efficiency of a semiconductor manufacturing process is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical vapor deposition method for manufacturing a semiconductor device, and more particularly, to a chemical vapor deposition method for reducing defects when a film is formed on a semiconductor wafer.

[0002]

2. Description of the Related Art As semiconductor devices are highly integrated, particles of a material deposited on a semiconductor wafer are important variables that determine the efficiency of a semiconductor device manufacturing process.

Various methods have been proposed for depositing materials on top of semiconductor wafers. The deposition method is divided according to temperature or pressure. The present invention relates to a low pressure chemical vapor deposition (LPCVD) method.

According to the low pressure chemical vapor deposition method, a deposition chamber capable of simultaneously performing a deposition process on a plurality of semiconductor wafers is used according to a trend of mass production of a semiconductor manufacturing process. A typical configuration of the deposition chamber is a vertical type. A plurality of semiconductor wafers are vertically formed inside the vertical deposition chamber and mounted so as to be arranged side by side. The deposition chamber includes a heating unit so as to surround the semiconductor wafer. The heating unit heats the deposition source gas flowing into the deposition chamber at a deposition process temperature. The deposition process is performed while maintaining the process pressure in the deposition chamber at a low pressure.

On the other hand, a deposition source gas to be deposited on a semiconductor wafer is selected through a flow rate control device mounted outside the deposition chamber, and the flow rate and content of the deposition source gas are controlled while controlling the inside of the deposition chamber. To be introduced. As a specific example, silane (silane: SiH ₄ ) gas is selected and used to deposit polysilicon on a semiconductor wafer. In order to deposit silicon oxide or silicon nitride, a deposition source gas suitable for each purpose is selected and a deposition process is performed.

However, according to the conventional semiconductor manufacturing process, a large number of particles are generated in the vapor deposition material layer as the integration density of the semiconductor device increases. A large number of particles generated in the deposition material layer are defects that hinder the reliability of the semiconductor device.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a method for forming a predetermined substance on a semiconductor wafer by a chemical vapor deposition method, wherein the formation of particles on the deposition substance on the semiconductor wafer can be suppressed. To provide a phase deposition method

[0008]

SUMMARY OF THE INVENTION The present invention comprises a step of pre-stabilizing the inside of a deposition chamber before depositing a predetermined substance on a semiconductor wafer mounted therein, and the step of pre-stabilizing the inside of the deposition chamber. A step of introducing a gas to be deposited thereon and depositing the gas on a semiconductor wafer.

Preferably, the pre-stabilization step and the material deposition step are performed under the same process conditions.

The pre-stabilization step is preferably performed while introducing a predetermined gas into the chemical vapor deposition chamber.

Preferably, the step of depositing the material is performed while flowing a deposition source gas selected according to a material to be deposited on the semiconductor wafer.

In the pre-stabilization step and the material deposition step, at least one of the process conditions may be the same among the flow rate of the gas introduced into the deposition chamber and the process pressure in the deposition chamber in each step. It is preferred to perform each step while maintaining.

It is preferable that the pre-stabilization step and the material deposition step are performed while maintaining the flow rate of each gas introduced into the deposition chamber within a range of ± 10 SCCM with reference to 500 SCCM.

Preferably, the step of depositing the substance is performed while maintaining the content of gas introduced into the deposition chamber at 50%.

The pre-stabilization step and the material deposition step may be performed while maintaining the process pressure in the deposition chamber within a deviation range of ± 0.015 Torr based on 0.25 Torr.

Preferably, the pre-stabilization step is performed while introducing the gas into the deposition chamber using nitrogen gas.

It is preferable that the predetermined material is any one selected from the group consisting of polysilicon, silicon oxide, and silicon nitride.

In the step of depositing the material, it is preferable to use a silane gas as a source gas to be introduced into the deposition chamber to deposit polysilicon on the semiconductor wafer.

Preferably, the pre-stabilization step and the material deposition step are performed in each step while maintaining a plurality of process conditions the same.

The pre-stabilization step and the material deposition step each include at least one of the flow rates of nitrogen gas and silane gas flowing into the deposition chamber and the process pressure inside the deposition chamber in each step. It is preferable to perform each step while maintaining the same process conditions.

In each of the pre-stabilization step and the material deposition step, the flow rates of the nitrogen gas and the silane gas flowing into the deposition chamber in each step are ± 10 S based on 500 SCCM.
Preferably, each step is performed while maintaining the CCM within the deviation range.

Preferably, the step of depositing the substance is performed while maintaining the content of silane gas introduced into the deposition chamber at 50%.

The pre-stabilization step and the material deposition step may be performed while maintaining the process pressure in the deposition chamber within a deviation range of ± 0.015 Torr based on 0.25 Torr.

According to the present invention, since the generation of particles generated in the substance deposited on the semiconductor wafer is suppressed, the reliability and yield of the semiconductor device are improved. Further, the efficiency of the whole process of manufacturing the semiconductor device is improved.
In addition, the present invention can contribute to mass production of the semiconductor manufacturing process, and thus has an advantage that the manufacturing cost of the semiconductor device can be reduced.

[0025]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in various other forms, and it should not be construed that the scope of the present invention is limited to the embodiments described in detail below. The embodiments of the present invention described with reference to the following drawings are provided to more completely explain the present invention to those skilled in the art related to the present invention. Like reference numerals in the drawings denote like elements.

<Embodiment> FIGS. 1 to 3 are a graph and a scanning electron microscope (hereinafter referred to as "SEM") photograph for explaining an embodiment of the present invention. Hereinafter, the step of depositing polysilicon on a semiconductor wafer will be specifically described.

FIG. 1 is a graph for explaining one embodiment of the chemical vapor deposition method of the present invention. The vertical axis indicates the process (processing) temperature, and the horizontal axis indicates the process (processing) time. .

Implementation of the present invention with the process conditions shown in FIG. 1 proceeds as follows. First, a semiconductor wafer is mounted inside the evaporation chamber. Thereafter, when the process temperature reaches ± 3 ° C. with reference to 620 ° C., the inside of the deposition chamber is maintained in a vacuum state (0 Torr) for a predetermined time (t ₁ ). Subsequently, a mass flow controller (MFC: Mass Flow Control)
a predetermined flow rate, for example, 500 SCCM (Stan).
± 10S based on dard Cubic Centimeter per Minute)
Nitrogen gas having a flow rate adjusted within the deviation range of the CCM is flowed or allowed to flow inside the deposition chamber for a predetermined time period (t ₂ ), thereby preliminarily stabilizing the inside of the deposition chamber. At this time, the inside of the deposition chamber is maintained at a predetermined process pressure, for example, a process pressure adjusted within a deviation range of ± 0.015 Torr based on 0.25 Torr (Torr). Subsequently, a predetermined flow rate, for example, 500 SCC
A flow rate adjusted within a deviation range of ± 10 SCCM with respect to the flow rate of M and a silane gas, which is 50% (%) of a gas flow rate of 500 ± 10 SCCM, is introduced into the deposition chamber. Then, polysilicon is deposited on the semiconductor wafer. At this time, the process pressure in the deposition chamber is the same as the pressure in the pre-stabilization stage of the deposition chamber, that is, the process pressure is adjusted within a deviation range of ± 0.015 Torr based on 0.25 Torr. To maintain. Thus, polysilicon can be deposited on the semiconductor wafer.

On the other hand, when a plurality of semiconductor wafers are simultaneously subjected to a vapor deposition process in the same vertical type vapor deposition chamber, each of the semiconductor wafers positioned on the uppermost and lowermost semiconductor wafers is deposited. A deviation may occur in the number of particles generated in polysilicon. In order to reduce such deviations, special attention is required for controlling the process temperature. For this reason, in the embodiment, the temperature deviation between the uppermost part and the lowermost part in the chamber is 10 ° C. to 5 ° C.
The vapor deposition process is performed so as to maintain the range of 0 ° C. It is preferable that the deposition temperature is maintained the same during the pre-stabilization step of the deposition chamber and the original deposition process.

As described above, the inside of the deposition chamber is pre-stabilized using nitrogen gas before the deposition process is fully performed. At this time, the process conditions of the pre-stabilization stage and the process conditions of the original deposition process are maintained without any difference. In such a case, particles generated due to a temperature gradient between the center portion and the edge portion on the semiconductor wafer mounted inside the evaporation chamber can be suppressed.

FIG. 2 is a graph showing the distribution of the number of particles per unit cluster of polysilicon deposited on a semiconductor wafer which has been subjected to the deposition step according to the description relating to FIG. At this time, the horizontal axis indicates the number of semiconductor wafers on which the vapor deposition process was performed at the same time. Here, the upper semiconductor wafer (T ₁ ) and the lower semiconductor wafer (B ₁ ) in the case where the vapor deposition process is performed by using the vertical type vapor deposition chamber are compared with each other.

FIG. 3 shows an etching step of depositing polysilicon on a semiconductor wafer by performing a deposition step according to the process conditions of FIG. 1, and then forming a polysilicon spacer on the side of the pattern that is positively etched on the semiconductor wafer. 6 is an SEM photograph showing the upper surface of the semiconductor wafer after the application.

According to FIG. 3, the patterns formed on the semiconductor wafer are clearly separated from each other. On the other hand, such an effect is obtained by repeating the process 10 times (run10 lo
t) When the above is repeated, the effect appears more remarkably. That is, the effect of the present invention is improved as the vapor deposition process is performed on a large number of semiconductor wafers at the same time.

<Comparative Example> In order to explain the present invention more specifically and in detail, a comparative example which is compared with an embodiment of the present invention will be described with reference to the accompanying drawings.

FIGS. 4 to 6 are a graph and an SEM photograph for explaining a comparative example in comparison with the embodiment in which polysilicon is deposited on a semiconductor wafer according to the present invention.

FIG. 4 is a graph showing the vapor deposition step (processing) temperature on the vertical axis versus the vapor deposition step (processing) time on the horizontal axis. According to FIG. 4, if a predetermined process temperature is reached after the semiconductor wafer is mounted in the deposition chamber, no gas flows, that is, a vacuum state (0 Torr) is maintained for a predetermined time period (t ₄ ). After that, 5
A silane gas having a content of 0 percent (%) was introduced into the deposition chamber for a predetermined time period (t ₅ ). At this time,
The process pressure inside the deposition chamber was maintained, for example, adjusted to 0.25 Torr. Under such conditions, the silane gas flowing into the inside of the deposition chamber caused a chemical reaction on the semiconductor wafer to proceed in a deposition step of forming a polysilicon layer.

FIG. 5 shows a vapor deposition step according to FIG.
5 is a graph showing the distribution of the number of particles per unit cluster of polysilicon deposited on a semiconductor wafer according to the number of semiconductor wafers subjected to a deposition step at the same time. On the other hand, when the deposition chamber is a vertical type, the upper semiconductor wafer (T ₂ ) and the lower semiconductor wafer (B ₂ )
Are shown in comparison with each other.

Referring to FIG. 5, a unit cluster of deposited polysilicon for each of the upper semiconductor wafer (T ₂ ) and the lower semiconductor wafer (B ₂ ) among the semiconductor wafers subjected to the deposition process in the vertical deposition chamber. It was found that there was a deviation in the number of particles per unit, and the number of particles per unit cluster on the upper semiconductor wafer (T ₂ ) appeared smaller than that on the lower semiconductor wafer (B ₂ ).

When the contents shown in FIG. 2 and the contents shown in FIG. 5 are compared with each other, a remarkable effect of the present invention can be understood. That is, in the case of the embodiment of the present invention, the number of particles per unit cluster of the deposited polysilicon has a distribution based on 100, whereas in the comparative example, the same value has a distribution based on 1,000. Have.

[0040]

According to the embodiment of the present invention, in comparison with the comparative example, particles generated in the deposited polysilicon layer are 90%.
It has the advantage of saving up to a percent (%).

FIG. 6 shows an etching process after depositing polysilicon on a semiconductor wafer according to the process conditions of FIG. 4 and then forming a polysilicon spacer on a side portion of a pattern engraved on the semiconductor wafer. 5 is an SEM photograph showing the upper surface of a semiconductor wafer.

According to FIG. 6, the polysilicon particles generated in the vapor deposition process remain between the patterns engraved on the semiconductor wafer, and a gap between adjacent patterns to be formed separately from each other is formed. A defective pattern to be interconnected occurred. It is clear from the comparison result between FIG. 6 and FIG. 3 that the effect of the present invention is remarkable.

[Brief description of the drawings]

FIG. 1 is a graph for explaining one embodiment of a chemical vapor deposition method of the present invention.

FIG. 2 is a graph for explaining the result of one embodiment of the chemical vapor deposition method of the present invention.

FIG. 3 is an SEM photograph showing a top surface of a semiconductor wafer according to one embodiment of the chemical vapor deposition method of the present invention.

FIG. 4 is a graph for explaining a comparative example compared with the example of the present invention.

FIG. 5 is a graph for explaining a result of a comparative example compared with the example of the present invention.

FIG. 6 is an SEM photograph showing a top surface of a semiconductor wafer according to a comparative example compared with the example of the present invention.

[Explanation of symbols]

t ₁ : predetermined time t ₂ : predetermined time area

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Zhang Yuan Jun 733-10, Yongdu 2-dong Dongdaemun-gu, Seoul, Republic of Korea

Claims (16)

[Claims] 1. The method according to claim 1, further comprising: pre-stabilizing the inside of the CVD chamber; and depositing a predetermined material on the semiconductor wafer in the pre-stabilized CVD chamber. Chemical vapor deposition method. 2. The method of claim 1, wherein the pre-stabilization step and the material deposition step are performed under the same process conditions. 3. The method according to claim 2, wherein the pre-stabilization is performed while introducing a predetermined gas into the CVD chamber. 4. The method of claim 2, wherein the step of depositing the material is performed while flowing a deposition source gas selected according to a material to be deposited on the semiconductor wafer. 5. The pre-stabilization step and the material deposition step each include determining at least one process condition based on a flow rate of a gas introduced into the deposition chamber and a process pressure inside the deposition chamber in each step. The chemical vapor deposition method according to claim 1, wherein each step is performed while maintaining the same. 6. The pre-stabilization step and the material deposition step may be performed while maintaining a flow rate of each gas introduced into the deposition chamber within a ± 10 SCCM deviation range with reference to 500 SCCM. The chemical vapor deposition method according to claim 5, wherein 7. The method of claim 5, wherein the step of depositing the material is performed while maintaining the content of gas introduced into the deposition chamber at 50%. 8. The pre-stabilization step and the material deposition step include performing each step while maintaining a process pressure in the deposition chamber within a deviation range of ± 0.015 Torr based on 0.25 Torr. The chemical vapor deposition method according to claim 5, characterized in that: 9. The method of claim 1, wherein the pre-stabilization is performed while introducing the gas into the deposition chamber using a nitrogen gas. 10. The method according to claim 1, wherein the predetermined material is any one selected from the group consisting of polysilicon, silicon oxide, and silicon nitride.
5. The chemical vapor deposition method according to 1. 11. The chemical vapor deposition method according to claim 10, wherein the material deposition step uses a silane gas as a source gas introduced into the deposition chamber to deposit polysilicon on the semiconductor wafer. Phase deposition method. 12. The chemical vapor phase of claim 11, wherein the pre-stabilization step and the material deposition step are performed in each step while maintaining a plurality of process conditions the same. Evaporation method. 13. The pre-stabilization step and the material deposition step may include at least one of a flow rate of a nitrogen gas and a silane gas flowing into the deposition chamber and a process pressure inside the deposition chamber in each step. The chemical vapor deposition method according to claim 12, wherein each step is performed while maintaining the same process conditions including: 14. The pre-stabilization step and the material deposition step may include controlling the flow rates of the nitrogen gas and the silane gas flowing into the deposition chamber to ± 1 on the basis of 500 SCCM.
14. The chemical vapor deposition method according to claim 13, wherein each step is performed while maintaining the deviation within a deviation range of 0 SCCM. 15. The method of claim 12, wherein the depositing the material is performed while maintaining a content of silane gas introduced into the deposition chamber at 50%. 16. The pre-stabilization step and the material deposition step may be performed while maintaining a process pressure in the deposition chamber within a deviation range of ± 0.015 Torr based on 0.25 Torr. Claim 12
5. The chemical vapor deposition method according to 1.