JPH11306075A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer wherein influence upon a processing speed is minimized and, at the same time, noise occurrence is reduced. SOLUTION: This device is equipped with a bus change rate detection part 21 which detects whether a bit change rate of an address outputted by a CPU 2 is large or not, outputs a slew rate adjustment demand and a wait instruction when it is large, and a bus interface part 22 which performs slew rate adjustment in accordance with the slew rate adjustment demand and the wait instruction, and which inserts the wait in an access cycle and outputs the address outputted by the CPU 2 to a memory part by way of an address bus. According to this method, when the bit change rate is large, that is, when an occurrence of noise is frequent, it is possible to reduce the occurrence of a noise by adjusting the slew rate and, at the same time, a transition time is made longer by this slew rate adjustment and the access time becomes long, but an effect which can complement increase in this access time can be obtained by inserting the wait.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer comprising a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of applied equipment, the proximity between semiconductor elements mounted on the same substrate, the speeding up of semiconductor elements, and the miniaturization between semiconductor elements have resulted in recent generation of noise. Malfunction of equipment due to interference between semiconductor elements and the like has become a problem. In particular, the microcomputer performs data processing and various controls via a bus.
This bus is composed of a plurality of signal lines and has a common signal path, so that a plurality of peripheral devices and memory units are connected in addition to the CPU. Therefore, a CPU or the like that must drive the plurality of peripheral devices and the memory unit must secure the driving capability of the driver. This driving capability
As the normal operation speed increases, it must increase,
High AC power consumption. For example, in a 16-bit bus, all 16 bus drivers operate at the maximum, and a large amount of current flows instantaneously via a power supply or a ground line. When a large amount of current flows through the power supply line and the ground line instantaneously, it becomes an electromagnetic wave and propagates in the air, causing malfunction of other adjacent semiconductor elements.

Conventionally, a slew rate adjusting circuit may be provided to reduce the instantaneous current. This is for suppressing a through current peculiar to a CMOS circuit, and is changed from an off state to an on state so that the time during which the P-channel transistor and the N-channel transistor are simultaneously turned on during the output transition of the driver is reduced. This delays the timing.

On the other hand, conventionally, there is also a configuration in which a wait is inserted into an access cycle according to an access target such as a memory unit or a peripheral device. FIG. 4 is a block diagram showing a conventional microcomputer.
Is a clock control unit that generates an operation clock, and 2 is a central processing unit (hereinafter referred to as C) that performs processing in synchronization with the operation clock.
A bus control unit 3 performs bus control in synchronization with the operation clock. A plurality of other peripheral devices and a memory unit (not shown) are connected to the bus control unit 3 via a bus. Further, the clock control unit 1, the CPU 2 and the bus control unit 3 are configured in one semiconductor integrated circuit, and the other plural peripheral devices and the memory unit are configured in another semiconductor integrated circuit and the like, and are connected by the bus. ing.

In the CPU 2, reference numeral 4 denotes an instruction fetch unit for reading an instruction from a memory unit, 5 denotes an instruction decode unit for decoding the read instruction, and 6 denotes an instruction execution unit for executing the instruction in accordance with the result of decoding the instruction. Further, in the bus control unit 3, reference numeral 7 denotes a bus arbitration unit which arbitrates when an access request from the instruction fetch unit 4 and an access request from the instruction execution unit 6 occur simultaneously, 8 denotes a switch for switching addresses, and 9 denotes an instruction. And a switch for switching the operand. Reference numeral 10 denotes a weight setting unit for setting whether or not to insert a wait in an access cycle according to an access target such as a memory unit or a peripheral device.
Is a bus interface unit that inserts a wait into an access cycle in response to the wait instruction and inputs / outputs via a bus. 12 is a driver for driving an address bus, a data bus and a control bus, and 13 is a timing control of the driver 12. And an input / output timing generation unit that outputs a driver control signal to a memory unit and peripheral devices connected to the bus.

Next, the operation will be described. For example, when reading instructions via a bus from a memory unit included in a semiconductor integrated circuit other than the semiconductor integrated circuits constituting the clock control unit 1, the CPU 2 and the bus control unit 3, the CPU 2
Output a memory access request and an address from the instruction fetch unit 4. The memory access request is output to the bus interface unit 11 via the bus arbitration unit 7. The address is output to the wait setting unit 10 and it is determined whether to insert a wait in the access cycle. In this case, it is assumed that no wait instruction is output to the bus interface unit 11. The address is output directly to the bus interface unit 11 via the switch 9.

An input / output timing generator 13 of the bus interface 11 controls a driver 12 for driving an address bus, a data bus and a control bus. At this time,
The address input from the instruction fetch unit 4 via the switch 8 is output to the address bus. Further, it outputs a driver control signal to the memory unit connected to the bus. Then, the instruction of the memory unit stored at the specified address is read out via the data bus, and is read into the instruction fetching unit 4 via the switch 9. In a microcomputer having a slew rate adjusting circuit,
The slew rate adjusting circuit is connected to the bus interface unit 11.
Driver 12 and a driver for driving the bus of the memory unit.

[0008]

Since the conventional microcomputer is configured as described above, the slew rate adjusting circuit increases the transition time of the driver 12 and is effective in terms of noise suppression. There was a problem that it was disadvantageous in terms of conversion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a microcomputer capable of minimizing the influence on processing speed and reducing noise generation.

[0010]

A microcomputer according to the present invention detects whether or not a bit change rate of an address output from a central processing unit is large, and outputs a slew rate adjustment request and waits if the bit change rate is large. A bus change rate detecting unit for outputting an instruction, a slew rate adjustment in accordance with the slew rate adjustment request and the wait instruction, and a wait inserted in an access cycle to transfer an address output from the central processing unit to a memory unit on an address bus; And a bus interface unit for outputting the data via the USB interface.

[0011] The microcomputer according to the present invention comprises:
The bus change rate detection unit sets a plurality of addresses before the bit change rate becomes large in a plurality of registers, and sets which of the plurality of addresses set in the plurality of registers is to be used. Freely
When the address output from the central processing unit matches the set address, it is detected that the bit change rate is large.

[0012] The microcomputer according to the present invention comprises:
It is determined whether the operation clock generated from the clock control unit is the basic clock or the divided clock.If the divided clock is the divided clock, the slew rate is adjusted and the address output from the central processing unit is stored in the memory unit. It has a bus interface unit for outputting via an address bus.

[0013] The microcomputer according to the present invention comprises:
The end point of the access cycle of the bus interface unit is monitored, and the next address is predicted from the address output from the central processing unit. An intermediate address between the addresses is set as a dummy cycle after the end of the access cycle. It is provided with an address insertion unit for outputting to the bus interface unit.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a microcomputer according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a clock control unit for generating an operation clock;
Reference numeral 2 denotes a central processing unit (hereinafter referred to as a CPU) that performs processing in synchronization with the operation clock, and reference numeral 20 denotes a bus control unit that performs bus control in synchronization with the operation clock. Bus control unit 2
0 is connected to a plurality of other peripheral devices and a memory unit (not shown) via a bus. Further, the clock control unit 1, the CPU 2 and the bus control unit 20 are configured in one semiconductor integrated circuit, and the other plural peripheral devices and the memory unit are configured in another semiconductor integrated circuit and the like, and are connected by the bus. ing.

In the CPU 2, reference numeral 4 denotes an instruction fetch unit for reading an instruction from a memory unit; 5, an instruction decoding unit for decoding the read instruction; and 6, an instruction execution unit for executing the instruction in accordance with the result of decoding the instruction. Also, the bus control unit 20
, 7 is a bus arbitration unit that arbitrates when an access request from the instruction fetch unit 4 and an access request from the instruction execution unit 6 occur simultaneously, 8 is a switch for switching addresses, and 9 is a switch for switching instructions and operands. is there. Reference numeral 10 denotes a weight setting unit for setting whether to insert a wait in an access cycle according to an access target such as a memory unit or a peripheral device, and 21 denotes whether or not a bit change rate of an address output from the CPU 2 is large. The bus change rate detection unit 22 detects the detection and outputs a slew rate adjustment request when it is larger, and outputs a wait instruction to the weight setting unit 10. A bus interface unit that adjusts a slew rate in response to a wait instruction, inserts a wait in an access cycle, and inputs / outputs via a bus, 12 is a driver for driving an address bus, a data bus, and a control bus, and 23 is a driver. It controls the timing of the driver 12 and also controls the memory and peripheral devices connected to the bus. An input-output timing generator that outputs a driver control signal and the slew rate adjustment enable signal.

Next, the operation will be described. For example, when reading instructions via a bus from a memory unit included in a semiconductor integrated circuit other than the semiconductor integrated circuits constituting the clock control unit 1, the CPU 2 and the bus control unit 3, the CPU 2
Output a memory access request and an address from the instruction fetch unit 4. The memory access request is output to the bus interface unit 22 via the bus arbitration unit 7. The address is output to the wait setting unit 10 and it is determined whether or not to insert a wait in the access cycle. In this case, the wait instruction is not output to the bus interface unit 22. The address is output directly to the bus interface unit 22 via the switch 9 and also to the bus change rate detection unit 21.

The bus change rate detection section 21 detects whether or not the bit change rate of the address output from the CPU 2 is large. If the bit change rate is large, the bus change rate detection section 21 outputs a slew rate adjustment request to the bus interface section 22 and a weight setting section. 10
To output the wait instruction. For example, in the previous address 0FFF ₁₆ outputted from the CPU 2, and carry the address is then output changes every bit like 1000 _16, bit changes such large number of bits is changed by a jump instruction or the like When the rate is high, the generation of noise is large, but the generation of noise is reduced by adjusting the slew rate. Further, the transition time becomes longer and the access time becomes longer due to the slew rate adjustment when the bit change rate is large. However, a wait is inserted to compensate for the increase in the access time. On the other hand, when the bit change rate is small, the occurrence of noise is small, so that high-speed access can be achieved with the highest drive capability without adjusting the slew rate and inserting a wait. Usually, since the address is monotonically increased by one or several addresses, the rate of change is small. On the other hand, there is a case where the bit change rate is large, such as the above-described carry in which all bits change, or a large number of bits change, but the ratio is small in view of the amount of execution of all programs.

The input / output timing generator 23 of the bus interface 22 controls the driver 12 that drives the address bus, data bus and control bus. At this time,
The wait is inserted into the access cycle in accordance with the wait instruction from the wait setting unit 10. Further, the time during which the P-channel transistor and the N-channel transistor are simultaneously turned on during the output transition of the driver 12 is reduced,
A slew rate adjusting circuit that delays the timing of the transition from the off state to the on state is performed to alleviate the instantaneous current and reduce the generation of noise. The address input from the instruction fetch unit 4 via the switch 8 is output to the address bus. Further, it outputs a driver control signal and a slew rate adjustment signal to a memory unit connected to the bus. Then, the instruction of the memory unit stored at the specified memory address is read out via the data bus, and is read out into the instruction fetch unit 4 via the switch 9.

As described above, in the first embodiment, the bus change rate detecting section 21 detects whether or not the bit change rate of the address output from the CPU 2 is large. Since a slew rate adjustment request is output and a weight instruction is output to the weight setting unit 10, noise is generated by adjusting the slew rate when the bit change rate is large, that is, when noise is large. Can be reduced. Also, by adjusting this slew rate,
Although the transition time becomes longer and the access time becomes longer, the increase in the access time can be compensated for by inserting a wait.

Embodiment 2 FIG. 2 is a block diagram showing a microcomputer according to a second embodiment of the present invention. In the figure, reference numeral 30 denotes a clock control unit for generating an operation clock of a basic clock or a divided clock;
Is a bus interface unit that determines whether the operation clock generated from the clock control unit 30 is a basic clock or a divided clock, and adjusts the slew rate when the divided clock is the divided clock. The other configuration is the same as that of FIG.

Next, the operation will be described. The second embodiment is applied to a microcomputer having a low power consumption mode. Particularly, in the case of a form device, the normal device is in a standby state, and the operation clock of the microcomputer is changed to a basic (highest frequency) clock divided by 8 or 16 to perform low-speed operation to reduce power consumption of the device. At the same time, when the device starts up from the standby state, the device operates with the basic clock, thereby reducing the total power consumption while achieving a predetermined performance at a necessary timing.

Therefore, the slew rate is adjusted in conjunction with the low speed mode. When using the basic clock,
At the time of high-speed operation, the best performance is obtained without performing the slew rate adjustment, but the slew rate is adjusted at the same time as shifting to the low-speed operation. In this low-speed operation, similarly to the case where the weight is inserted in the first embodiment, the permissible access time becomes long, so that there is no problem even if the slew rate adjustment is performed.

In FIG. 2, the clock control unit 30
An operation clock is supplied to the PU2 and the bus control unit 20. Normally, the clock control unit 30 internally includes a basic clock and a plurality of frequency-divided clocks obtained by dividing the basic clock.
An operation clock is selected under the control of PU2. In the second embodiment, a signal whose polarity is inverted by the clock control unit 30 when the basic clock is selected as the operation clock and when the divided clock is selected, for example,
The signals (0) and (1) are provided and used as the slew rate adjustment signal.

As described above, in the second embodiment, the bus interface unit 31 determines whether the operation clock generated from the clock control unit 30 is a basic clock or a divided clock, and determines whether the operation clock is a divided clock. Since the slew rate is adjusted in a certain case, it is possible to reduce the generation of noise at the time of the divided clock.

Embodiment 3 FIG. 3 is a block diagram showing a microcomputer according to a third embodiment of the present invention. In FIG.
Monitoring the end of the access cycle of the
An address insertion unit that predicts the next address from the address output from U2 and outputs an intermediate address between the addresses as a dummy cycle after the end of the access cycle. A switch that selects an address output from the insertion unit 40 and outputs the selected address to the bus interface unit 22. The other configuration is the same as that of FIG.

Next, the operation will be described. The address insertion unit 40 constantly monitors the address output from the CPU 2 and monitors the timing when the bus becomes empty. The bus interface unit 22 determines whether the bus is free.
The bus interface unit 22 does not perform the bus operation unless a bus request from the bus arbitration unit 7 occurs at the time when the bus operation can be started, for example, at the end of the bus access cycle. At this time, the bus interface unit 22 notifies the address insertion unit 40 that the bus is idle. If the address output from the CPU 2 is 0FFF ₁₆ and the bus access cycle is completed and the next output address is predicted to be 1000 ₁₆ , address such, for example, and outputs the dummy cycle to address the 1F0F _16. Thus, for the bus from 0FFF ₁₆ 1,000 ₁₆ simultaneously 13 bits has changed, 1F0F _16, 1F0F ₁₆ from 1000 ₁₆ with each 5 bits are for but divided into two simultaneously change from 0FFF _16, This is equivalent to 8 bits, and the current flowing instantaneously is smoothed, so that generation of noise can be suppressed.

As described above, according to the third embodiment, the address insertion unit 40 monitors the end point of the access cycle of the bus interface unit 22 and, at the same time, monitors the CPU.
Since the next address is predicted from the address output from the address 2 and an intermediate address between the addresses is output as a dummy cycle after the end of the access cycle, the bus for many bits changes at the same time. What has been done can be divided into two times, the bits that change simultaneously can be reduced, and the current flowing instantaneously can be smoothed to suppress the generation of noise.

Embodiment 4 In the fourth embodiment, the reference of the bus change rate of the bus change rate detecting unit 21 in the first embodiment can be set by software, and a plurality of addresses before the bit change rate becomes large can be set. In addition to setting in advance to a plurality of registers, it is possible to freely set which of the plurality of addresses set in the plurality of registers is to be used, and to change a bit when an address output from the CPU 2 matches the set address. It detects that the rate is large.

Next, the operation will be described. In the fourth embodiment, the standard of the bus change rate in the first embodiment can be set by software. For this, a register is provided in the bus change rate detecting section 21 and an address is set in the register. For example, if a 16-bit address bus, idea to 0FFF ₁₆ and program in advance register, 0F
When a bus access occurs at the address of the FF ₁₆ , the bus change rate detection unit 21 outputs a slew rate adjustment request to the bus interface unit 22. Bus interface unit 2
2, when there is a slew rate adjustment request, it determines that the slew rate adjustment will be performed at the time of the next bus access,
The slew rate is adjusted when a bus access actually occurs.

A plurality of address setting registers may be provided. By providing multiple registers, if priority is given to noise suppression, all registers are used, and if high speed is given priority, the number of registers to be used is limited. It is possible to gain flexibility for turning off. In addition, since the reference of the bus change rate can be set by software programming, the address change rate can be set in a frequently executed area, that is, in a frequently executed address, in the entire execution program. Noise generation at a large address can be suppressed.

As described above, in the fourth embodiment, the reference of the bus change rate of the bus change rate detecting section 21 can be set by software, and a plurality of addresses before the bit change rate becomes large can be set. Pre-set in the register of
It is possible to freely set which of the plurality of addresses set in the plurality of registers is to be used, and to detect that the bit change rate is large when the address output from the CPU 2 matches the set address. Therefore, it is possible to obtain flexibility with respect to a trade-off between noise suppression and speeding up, and to suppress occurrence of noise at an address of a frequently executed area in the entire execution program.

[0032]

As described above, according to the present invention, the generation of noise can be reduced by adjusting the slew rate when the bit change rate is large, that is, when the generation of noise is large. By adjusting the slew rate, the transition time becomes longer and the access time becomes longer, but the effect of compensating for the increase in the access time can be obtained by inserting a wait.

According to the present invention, it is possible to obtain flexibility in a trade-off between noise suppression and high speed, and to suppress occurrence of noise at an address of a frequently executed area in the entire execution program. The effect that can be obtained is obtained.

According to the present invention, by performing the slew rate adjustment in the case of the divided clock, it is possible to obtain the effect of reducing the occurrence of noise during the divided clock.

According to the present invention, the buses for a large number of bits are changed at the same time, but the bits that change at the same time can be reduced by dividing the buses into two times, and the current flowing instantaneously is smoothed. The effect of suppressing generation of noise is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a microcomputer according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a microcomputer according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional microcomputer.

[Explanation of symbols]

1, 30 clock control unit, 2 CPU (central processing unit), 21 bus change rate detection unit, 22, 31 bus interface unit, 40 address insertion unit.

Claims (4)

[Claims] When accessing a memory unit, a central processing unit for outputting an address of the memory unit in synchronization with an operation clock generated from a clock control unit, and a bit of an address output from the central processing unit A bus change rate detection unit that detects whether the change rate is large and outputs a slew rate adjustment request and outputs a wait instruction when the change rate is large; a slew rate adjustment request and a weight output from the bus change rate detection unit A microcomputer comprising: a bus interface unit that adjusts a slew rate according to an instruction, inserts a wait into an access cycle, and outputs an address output from the central processing unit to the memory unit via an address bus. 2. The bus change rate detecting section sets a plurality of addresses before a bit change rate is increased in a plurality of registers, and determines which of the plurality of addresses set in the plurality of registers. 2. The microcomputer according to claim 1, wherein the address can be freely used or set, and when the address output from the central processing unit matches the set address, the microcomputer detects that the bit change rate is large. And a central processing unit for outputting an address of the memory unit in synchronization with an operation clock generated by the clock control unit when accessing the memory unit; and an operation clock generated by the clock control unit. A bus for judging whether the clock is a basic clock or a divided clock, and in the case of the divided clock, adjusting a slew rate and outputting an address outputted from the central processing unit to the memory unit via an address bus A microcomputer including an interface unit. 4. A central processing unit which, when accessing a memory unit, outputs an address of the memory unit in synchronization with an operation clock generated from a clock control unit, and outputs the address of the memory unit to the memory unit from the central processing unit. A bus interface unit for outputting an address via the address bus, monitoring the end of an access cycle of the bus interface unit, predicting the next address from the address output from the central processing unit, and A microcomputer which outputs an intermediate address between the bus interface unit as a dummy cycle after completion of the access cycle to the bus interface unit.