JP4764387B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a current consumption technique in a semiconductor device, for example, a technique effective when applied to a data processing or communication semiconductor device having a large time bias or location bias in current consumption.

  Patent Document 1 describes a semiconductor device equipped with a current consumption circuit that suppresses fluctuations in power supply voltage due to fluctuations in load current when switching between a power-down mode and a normal mode. This is because current is supplied to the current consumption circuit before a sudden current flows through the load, and current consumption by the current consumption circuit is reduced before the load current is suddenly reduced. To do.

  Patent Document 2 discloses an operation detection circuit that detects an operation rate (activity rate) of a pulse generation circuit and a detection signal generated by the detection circuit to reduce power supply voltage fluctuation caused by a change in current amount. A semiconductor device having a transient current reduction circuit comprising a current consumption circuit is described.

JP 2003-258617 A JP-A-10-090370

  The inventor examined the influence of a decrease in the amount of current consumption due to the pipeline installation of the central processing unit. We paid attention to the fact that if the instruction execution operation is stalled before the central processing unit accesses the low-speed module and acquires data, the current consumption is greatly reduced. Since the amount of current consumed by the central processing unit is large, the power supply voltage may fluctuate before and after pipeline installation if the amount of consumed current decreases during the pause period. In order to suppress this decrease in current consumption, it is sufficient to consume current during that period, but it is difficult to estimate the current in advance. The above-mentioned patent document does not consider this point.

  Furthermore, as a result of studying the current consumption circuit, the present inventor has found that a current consumption circuit capable of controlling the amount of current and the timing of current flow against a side-channel attack that takes away secret information from the power consumption of the circuit and leaked electromagnetic waves, It was found useful for disturbing electric power and leaked electromagnetic waves.

  An object of the present invention is to provide a semiconductor device capable of easily suppressing fluctuations in a power supply voltage due to a difference in power consumption state by a circuit synchronized with a clock cycle.

  Another object of the present invention is to provide a semiconductor device that can easily disturb power consumption and leakage electromagnetic waves of a circuit against side channel attacks.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, a current consumption circuit that performs a current consumption operation when the first circuit that can operate in synchronization with the clock cycle and request access is waiting for a response to the access request is employed. The current consumption circuit performs a current consumption operation for each clock cycle in order to suppress a decrease in the amount of current consumption during a pause period of an operation instructed by the first circuit, and includes a plurality of current consumption units that perform the current consumption operation. Have. The operation is being stopped in the first circuit, the number of the current consumption unit for current consumption operation is variable available-.

  From the above, it is possible to suppress the current consumption amount from decreasing during the operation suspension period of the first circuit by the current consumption circuit. Since the amount of current consumed by the current consuming circuit is set according to the number of current consuming units selected for operation, it is possible to easily cope with cases where it is difficult to estimate the amount of current in advance.

  Further, by adopting a current consumption circuit that performs a current consumption operation so as to compensate for the difference in the consumption current amount of the circuits operated in a complementary manner, it becomes difficult to estimate the difference in the internal operation state from the consumption current amount.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to easily suppress fluctuations in the power supply voltage due to the difference in power consumption state between circuits synchronized with the clock cycle.

  It is possible to easily disturb circuit power consumption and leakage electromagnetic waves against side channel attacks.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] The semiconductor device operates in synchronization with the clock cycle and can access the first circuit (2), and the second circuit (5) performs access control in response to the access request from the first circuit. A third circuit (4) and a current consumption circuit (20) that performs a current consumption operation during a period in which the third circuit instructs the first circuit to suspend operation until there is an access response from the second circuit. The current consumption circuit performs a current consumption operation for each clock cycle in order to suppress a decrease in the amount of current consumption during the pause period of the operation instructed to the first circuit. The current consumption circuit includes a plurality of current consumption unit (21), the operation is being stopped in the first circuit, the number of the current consumption unit for current consumption operation is variable available-.

  From the above, it is possible to suppress the current consumption amount from decreasing during the operation suspension period of the first circuit by the current consumption circuit. Since the amount of current consumed by the current consuming circuit is set according to the number of current consuming units selected for operation, it is possible to easily cope with cases where it is difficult to estimate the amount of current in advance.

  [2] The semiconductor device according to [1] further includes a flash memory (6) having control data (CDAT) designating the number of the current consuming units, and the control data output from the flash memory to decode the current. And a decoder (22) for generating a selection signal for selecting the current consumption unit that performs the consumption operation. Control data to be read from the flash memory may be determined according to the number of current consuming units to be selected for operation. For example, the initial value may be supplied from the flash memory to the decoder in the initialization operation after canceling the reset instruction of the semiconductor device.

  [3] In the semiconductor device of [2], the decoder sets the number of the current consuming units that perform the current consuming operation to zero even if the values of all the bits of the control data are 0 or 1. In the initial state of the flash memory, it is possible to prevent an excessive current from flowing unexpectedly when the control data is indefinite whether it is all 0 or 1.

  [4] In the semiconductor device described above, the first circuit is a central processing unit that executes an instruction, the second circuit is a circuit having an operation speed slower than that of the first circuit, and the third circuit is a bus state. It is a controller. The third circuit instructs the first circuit to pause the operation according to an instruction to stall the instruction execution operation. The semiconductor device is, for example, a microcomputer.

  [5] A semiconductor device according to another aspect of the present invention includes a first circuit (71) and a second circuit in which the first circuit operates in a complementary manner and consumes a larger amount of current during operation than the first circuit. (72) and the difference between the amount of current consumption during the period in which the second circuit waits for operation and the first circuit operates and the amount of current consumption in the period for which the first circuit waits for operation and the second circuit operates Therefore, a current consumption circuit (81, 82) that consumes current during the former period is provided.

  As a result, it becomes difficult to estimate the difference in the internal operation state from the amount of current consumption, and the power consumption and leakage electromagnetic waves of the circuit can be easily disturbed against side channel attacks.

  [6] In the semiconductor device as described in [5], the current consuming circuits are arranged in a distributed manner or evenly throughout the semiconductor device. In addition, the current consuming circuits are arranged closer to the first circuit than the second circuit. This makes it difficult to grasp the difference in current consumption from the point of circuit arrangement.

  [7] In the semiconductor device of [6], the first circuit and the second circuit operate in synchronization with a clock cycle of a clock signal, and the current consumption circuit performs a current consumption operation every clock cycle. It is possible to make it difficult to grasp the difference in the amount of current consumption from the point of operation form of clock synchronization.

2. Details of Embodiment << Suppression of Reduction of Current Consumption at Stall of Central Processing Unit >>
FIG. 1 illustrates a microcomputer 1 according to an example of the present invention. The microcomputer 1 shown in the figure is not particularly limited, but is formed on a semiconductor substrate such as single crystal silicon by a known complementary MOS integrated circuit manufacturing technique.
The microcomputer 1 is supplied with an operating power supply voltage VCC from an external voltage regulator (VPREGU) 10 as an external power supply circuit mounted on its mounting board (not shown).

  The microcomputer 1 has a central processing unit (CPU) 2 that operates in synchronization with the clock signal CLK and executes instructions. When the central processing unit 2 decodes and executes the fetched instruction, the central processing unit 2 requests access to fetch an operand necessary for an operation or the like or fetch an instruction to be executed next. If the access request issued by the central processing unit 2 is for the high speed access module (HSMDL) 3, the high speed access module 3 returns data or the like to the central processing unit 2 in response thereto. The high speed access module 3 is, for example, an internal RAM (random access memory). The central processing unit 2 and the high-speed access module are not particularly limited, but operate in units of cycles of the clock signal CLK. For example, the central processing unit 2 has an ability to execute instructions in a pipeline and apparently execute one instruction in one cycle of the clock signal CLK. However, if the data required for the calculation is not available at the operation stage, the pipeline is stalled until the data is available. Also, piler installation occurs when there are no executable instructions stored in the prefetch queue. When pipeline installation occurs, each pipeline stage is set to NOP (non-operation), and during that period, the CPU 2 pauses the instruction execution operation. Pipeline installation occurs when a process result of a pipeline stage requires a process result of an earlier pipeline stage and a necessary process result is not available.

  The access request issued by the central processing unit 2 is also supplied to the bus state controller (BSC) 4. The bus state controller 4 is connected to a flash memory (FLASH) 6 and other low-speed access modules (LSMDL) 5. In the bus state controller 4, an access request from the central processing unit 2 is directed to the flash memory 6 or other low-speed access module 5 (the flash memory 6 and other low-speed access modules 5 are also simply referred to as low-speed access modules 5 and 6). At this time, the access control of the low speed access modules 5 and 6 is performed in accordance with the operation speed of the low speed access modules 5 and 6. If the access request is a read access, read data as a response result is given from the low-speed access modules 5 and 6 to the bus state controller 4, and the bus state controller 4 sends the data to the central processing unit 2 that is the access request source. return.

  The bus state controller 4 outputs a stall signal STL to the central processing unit 2 until a response to the access request from the central processing unit 2 is returned to the central processing unit 2. When the stall signal STL is asserted, the central processing unit 2 thereafter makes each stage of the pipeline non-operation, thereby stalling the instruction execution operation until it is negated, that is, halting the instruction execution operation.

  The microcomputer 1 has a current consumption circuit 20 that performs a current consumption operation in response to a stall period of the instruction execution operation by inputting a stall signal STL. The current consumption circuit 20 includes a plurality of current consumption units (CLDU) 21_1 to 21_i. The number of the current consuming units that perform the current consuming operation is made variable according to an instruction from the current consumption control circuit (CLDCNT) 22. Control data CDAT for this purpose is held in the flash memory 6. For example, when the reset instruction by the reset signal RES is cancelled, the control data CDAT is initially loaded from the flash memory 6 to the current consumption control circuit 22, and the current consumption control circuit 22 decodes it to perform current consumption operation. Enable signals ENB_1 to ENB_i as selection signals for selecting the unit 21 are generated.

  There are no restrictions on the location of the current consuming unit, and the current consuming unit can be placed freely throughout the semiconductor device.

  FIG. 2 shows a specific example of the current consumption unit 21_i. The current consumption unit 21_i has, for example, a plurality of unit circuits 30_1 to 30_j. Each unit circuit 30_1 to 30_j is supplied with a stall signal STL, a corresponding enable signal ENB_i, and a clock signal CLK.

  The unit circuit 30_1 has a plurality of load cells (LDC) 40 connected in series, and the data input terminal of a D-type latch circuit (LAT) 41 is connected to the output of the load cell 4 at the final stage. A data output terminal of the latch circuit 41 is feedback-coupled to one input terminal of each of a NAND gate (NAND) 42 and a NOR gate (NOR) 43, each output is selected by the selector 44, and the selected output is the first stage load cell 40. Is coupled to the input terminal. The enable signal ENB_i corresponding to the stall signal STl is ANDed by the AND gate 45, the AND signal is supplied to the other input terminal of the NAND gate 42, and the inverted signal of the AND signal is the NOR gate 43. It is supplied to the other input terminal. The selector 44 selects the output of the NOR gate 43 when the selection signal ivs is 1, and selects the output of the NAND gate 42 when the selection signal ivs is 0. Since the initial output of the AND gate 45 is 0, the initial output of the NAND gate 42 is 1, and the initial output of the NOR gate 43 is 0. In a state where the output of the NAND gate 42 is selected by the selector 44, when the output of the selector 44 is fed back to the NAND gate 42 by the latch operation of the latch circuit 41, the output of the NAND gate 42 is inverted each time. In a state where the output of the NOR gate 43 is selected by the selector 44, when the output of the selector 44 is fed back to the no-add gate 43 by the latch operation of the latch circuit 41, the output of the NOR gate 43 is inverted each time. Accordingly, the output of the selector 44 is clock-changed at a cycle twice that of the clock signal CLK as illustrated in FIG. The clock change when the selection signal ivs = 1 and the clock change when ivs = 0 are out of phase by 180 degrees.

  As illustrated in FIG. 4, the load cell 4 sets the input A to output Y through inverters 50 and 51 in two stages in series. The inverted signal from the inverter 50 of the input A is delayed by the delay circuit (DLY) 54, and the output of the delay circuit 54 and the non-inverted signal from the inverters 50 and 52 of the input A are received by the AND gate 56. The type driving MOS transistor 57 is switch-controlled. As illustrated in FIG. 5, the output en of the AND gate 56 has a clock waveform with a duty smaller than the clock duty of the input A, and the drive MOS transistor 57 is turned on during the period when the output en is set to 1. A current Id is supplied.

  The pulse waveform supplied to the input A of the load cell is the waveform at the time of ivs = 1 or the waveform at the time of ivs = 0 in FIG. 3, and the operation in which one unit circuit 30 flows current is in two cycles of the clock signal CLK. Once. Since the clock signal CLK is an operation cycle of the central processing unit 2, the half unit circuit 30 is set to ivs = 1 and the other half unit circuit 30 is set to ivs = 0 so as to perform an operation of passing a current every cycle. To be. Thereby, one current consumption unit 21_i can flow the same current every cycle of the clock signal CLK. Although not specifically shown, other current consuming units are similarly configured.

  FIG. 6 illustrates the decode logic (DEC) of the current consumption control circuit (CLDCNT) 22. Here, the control data is 3 bits, six enable signals ENB_1 to ENB_6 are generated, and for convenience, two current consumption units are assigned to each enable signal. In particular, there is provided decoding logic that sets the number of current consumption units that perform a current consumption operation to zero even when the value of the control data CDAT is all 0 or 1. With the above control, the number of modules to be operated can be arbitrarily selected, so that necessary current consumption can be generated according to the situation.

According to the microcomputer described above, the following operational effects are obtained.
(1) The current consumption circuit 20 can suppress a reduction in the amount of current consumption during the operation suspension period of the central processing unit 2. Since the amount of current consumed by the current consumption circuit 20 is set according to the number of current consumption units 21 selected for operation, it is possible to easily cope with a case where it is difficult to estimate the amount of current in advance.
(2) As exemplified by the current waveform in FIG. 3, a current can be passed every operation clock cycle of the central processing unit 2, similarly to the clock synchronization operation of the central processing unit 2.
(3) Since the latch circuit 41 is arranged as a sequential circuit in the current consuming unit 21 as illustrated in FIG. 2, the current consuming unit 21 may be subject to event-driven timing verification in automatic placement and routing. It is possible to reduce human intervention as much as possible.
(4) The current consumption control circuit 22 sets the number of the current consumption units that perform the current consumption operation to zero regardless of the values of all the bits of the control data being 0 or 1. In the initial state of the flash memory 6, it is possible to prevent an excessive current from flowing unintentionally when it is uncertain whether the control data CDAT is all bits 0 or 1.

<Suppression of current consumption reduction to improve tamper resistance>
Next, an example of improving the tamper resistance by applying a current consumption circuit to a circuit that requires tamper resistance, such as an RSA encryption circuit, will be described.

For example, an example of an encryption circuit using a power-residue arithmetic circuit by a binary method will be given. The power residue arithmetic circuit algorithm is, for example,
Input: Z, N, E = (ek-1, ..., e1, e0) 2
Output: Z = XE mod N
1: Z: = 1;
2: for i = k-1 downto 0
3: Z: = Z * Z mod N;
4: if (ei == 1) then
5: Z: = Z * X mod N;
6: endif
7: end for
It is described as follows.

  FIG. 7 illustrates an overall view of a circuit using the above algorithm. Processing branches depending on the value of ei in the description line of “4:” in the above algorithm. The circuit scale of this is expressed by the size of the block in the figure. The “first circuit 71” (process of ei == 0) and the “second circuit 72” (ei == 1) shown in FIG. Process). The first circuit 71 and the second circuit 72 are operated complementarily.

  Since there is a difference in circuit scale between the first circuit 71 and the second circuit 72, the power consumption varies depending on the value of ei as illustrated in FIG. The second circuit 72 consumes more current. Further, if the arrangement when these circuits are laid out on the chip is shown in FIG. 9, the radiation electromagnetic wave can be seen to have a bias and a difference in strength as shown in FIG. Due to the difference between these power consumption and radiated electromagnetic waves, they are susceptible to side channel attacks.

  Therefore, as shown in FIG. 11, a plurality of current consuming circuits 81 and 82 having the current consuming unit 21 are arranged on the entire chip of the semiconductor device so as to fill the current difference. Accordingly, the difference in current consumption becomes invisible as illustrated in FIG. 12, and the radiated electromagnetic wave can be disturbed as shown in FIG.

  Further, if the current consuming unit 21 constituting the current consuming circuits 81 and 82 is made into a cell using a standard MOS, it cannot be distinguished from the standard cell in terms of layout, so it is difficult to see the arrangement and the arrangement is also difficult. Since it can be done freely, it is hard to be overlooked as a source of disturbance.

  As described above, by using a current consumption circuit that can control the amount of current and the timing of current flow against a side channel attack that steals secret information from the power consumption of the circuit and leakage electromagnetic waves, the power consumption and leakage electromagnetic waves are disturbed. It becomes possible to make it.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  The configuration described as an example of suppressing the decrease in the amount of current consumption when the central processing unit is stalled can be applied not only to the microcomputer but also to various accelerators such as image processing, audio processing, and encryption / decryption processing. The present invention can also be applied to the case of suppressing the current consumed when the high-speed communication module communicates and the current fluctuation at the time of stoppage.

FIG. 1 is a block diagram of a microcomputer according to an example of the present invention. FIG. 2 is a logic circuit diagram illustrating a specific example of the current consumption unit. FIG. 3 is a timing chart illustrating the operation timing of the current consumption unit. FIG. 4 is a logic circuit diagram illustrating a specific example of the load cell. FIG. 5 is a timing chart illustrating the operation timing of the load cell. FIG. 6 is an explanatory diagram illustrating the decoding logic of the current consumption control circuit. FIG. 7 is a block diagram generally showing a circuit using a power residue arithmetic circuit algorithm. It is explanatory drawing which shows the power consumption which is different by the value of ei in a 1st circuit and a 2nd circuit. FIG. 8 is a plan view illustrating an arrangement when the circuit of FIG. 7 is laid out on a chip. FIG. 10 is a plan view illustrating a distribution of radiated electromagnetic waves in the layout of FIG. 9. It is a top view which illustrates the state which has arrange | positioned the current consumption circuit in the chip | tip of a semiconductor device. It is explanatory drawing which illustrates a mode that the difference of current consumption becomes invisible by complementary operation | movement of a 1st circuit and a 2nd circuit by arrangement | positioning of a current consumption circuit. It is a top view which illustrates a mode that a radiation electromagnetic wave is disturbed by a current consumption circuit.

Explanation of symbols

1 Microcomputer (MCU)
10 External voltage regulator (VPREGU)
CLK Clock signal 2 Central processing unit (CPU)
3 High-speed access module (HSMDL)
4 Bus state controller (BSC)
6 Flash memory (FLASH)
5 Low-speed access module (LSMDL)
STL stall signal 20 Current consumption circuit 21_1 to 21_i Current consumption unit (CLDU)
22 Current consumption control circuit (CLDCNT)
CDAT control data ENB_1 to ENB_i enable signal 30_1 to 30_j Unit circuit 40 Load cell (LDC)
ivs selector selection signal 71 first circuit 72 second circuit

Claims (8)

A first circuit that can operate in synchronization with a clock cycle and request access; a third circuit that controls access to the second circuit in response to an access request from the first circuit; and an access response from the second circuit A current consuming circuit that performs a current consuming operation during a period in which the third circuit instructs the first circuit to pause the operation until
The current consumption circuit performs a current consumption operation for each clock cycle in order to suppress a decrease in the amount of current consumption during a pause period of an operation instructed to the first circuit,
The current consumption circuit includes a plurality of current consumption unit, the operation is being stopped in the first circuit, the number of the current consumption unit for current consumption operation is variable available-semiconductor device.   A flash memory having control data designating the number of the current consuming units, and a selection signal for selecting the current consuming unit for performing the current consuming operation by decoding the control data output from the flash memory The semiconductor device according to claim 1, further comprising a decoder.   3. The semiconductor device according to claim 2, wherein the decoder sets the number of the current consumption units that perform the current consumption operation to zero even when the values of all bits of the control data are 0 or 1. 4. The first circuit is a central processing unit that executes instructions, the second circuit is a circuit having an operation speed slower than that of the first circuit, and the third circuit is a bus state controller,
4. The semiconductor device according to claim 1, wherein the third circuit instructs the first circuit to pause the operation by an instruction to stall the instruction execution operation. 5.   The first circuit and the first circuit are operated in a complementary manner and consume a larger amount of current consumption during operation than the first circuit, and the first circuit waits for the first circuit to operate and the first circuit operates And a current consuming circuit that consumes current during the former period in order to compensate for the difference between the amount of consumed current and the amount of current consumed during the period when the first circuit waits for the second circuit to operate.   The semiconductor device according to claim 5, wherein the current consumption circuit is distributed over the entire semiconductor device.   The semiconductor device according to claim 6, wherein more current consuming circuits are arranged closer to the first circuit than the second circuit. The first circuit and the second circuit operate in synchronization with a clock cycle of a clock signal;
The semiconductor device according to claim 7, wherein the current consumption circuit performs a current consumption operation for each clock cycle.

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