JPH11306020A - Execution control system for block store instruction in information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor which has a series of block store instructions successively execute so that a waiting time of a CPU is made shortest and, at the same time, to make control of order of the instruction execution easier. SOLUTION: This device is equipped with a counter means 11 which is made increment when a request signal from a CPU 2 is the request signal based on a block store instruction and is made decrement when it is detected that execution of the block store instruction is completed and a request selector means 12 which controls input of the request signal in accordance with a count value of the counter means 11. Then, when the count value of the counter means 11 is not zero, only the request signal based on a block store instruction is preferentially selected and is made continuously execute.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an execution control method of a block store instruction in an information processing device. For example, an information processing device such as a large computer includes a plurality of central processing units each having a buffer storage device, a plurality of main storage devices storing data processed by each of the central processing units, and a central processing unit. And a storage control device that controls both the buffer storage device and the main storage device under the exchange of data.

In such an information processing apparatus, a process corresponding to each instruction is executed based on various instructions issued from each central processing unit. One of the various instructions is a block store. There are orders. The present invention describes an execution control method of the block store instruction.

[0003]

2. Description of the Related Art In recent years, an information processing apparatus has been required to increase its processing capability more and more. Therefore, the conventional serial processing has been shifted to a pipeline processing. In this pipeline type information processing apparatus, one instruction is executed in parallel by a plurality of pipelines, and the throughput of processing increases dramatically. In this case, it is not enough to simply execute the instructions in parallel, and the information processing apparatus must operate so as to guarantee the execution order of the instructions described in the program by the user. For this purpose, a control unit for determining the execution order of instructions is generally incorporated in an information processing apparatus.

Among the various instructions targeted by the control means, especially in the processing of store instructions, the execution order must be carefully determined. This is because, in the processing of such store-related instructions, the main storage device (MS
U) and the buffer storage device (C) in each central processing unit (CPU).
This is because data update processing in various storage devices such as an ACHE) and a key storage device (KSU) that holds a main storage protection key is involved.

[0005] Store-type instructions involving such an updating process can be accessed from a main storage device (M
SU) and a buffer memory (CACH) built in each central processing unit (CPU).
Since the update process of the same data existing in all of E) is involved, the update process takes a considerable time.

[0006] Among the store-related instructions, especially in the case of a block store instruction, the above-described update processing requires a considerable amount of time. This is because a block store instruction usually consists of a group of consecutive store instructions. FIG. 5 is a basic block diagram showing an example of a general information processing apparatus to which the present invention is applied. In FIG. 1, reference numeral 1 denotes an information processing device, for example, a large computer. The information processing apparatus 1 has a central processing unit (CPU) 2 that controls the entire apparatus.
There are a plurality of U (# 0, # 1... #N). Further, the information processing apparatus 1 has a main storage device (MSU) 3 for storing data processed by each CPU 2, and the MSUs 3 are plural (# 0, # 1,... #M). Each CPU 2 has a built-in buffer storage device (CAC: CACHE) 4 and each CACH
E4 holds the same data as some data in MSU3.

[0007] At least these CPU2, MSU3 and CACHE4 are controlled by a storage control unit (MCU).
5, the present invention mainly describes this MCU5. The MCU 5 is a key storage device (KSU) 6 as described above.
And an input / output device (I / O) 7. The block store instruction which is the subject of the present invention will be described with reference to FIG. The block store instruction is an instruction executed when the main storage (MSU) 3 is initialized, and a large amount of data is processed at one time. When a block store instruction is issued from any of the central processing units (CPU) 2, the following and are executed.

An invalidation process is performed on the buffer storage device (CACHE) 4. That is, the block data held in CACHE4 is invalidated. Data “0” is written to all addresses of the specified fixed-length memory block in the main storage device (MSU) 3. The data that is invalidated above is the same data as the data of the fixed-length memory block.

The key of the key storage device (KSU) 6 is updated. The key information is information useful for security management of the main storage device (MSU) 3, and is information indicating whether a certain memory block has been referred to, whether the memory block has been changed, and the like. The information of this key is updated whenever there is a write to MSU3. When the block store instruction is issued from one of the plurality of CPUs 2, the block store instruction is similarly issued from the remaining CPUs 2 in conjunction with the instruction. Then, invalidation is first performed on the CACHE 4 in the CPU 2 that has issued the block store instruction, and subsequently, the remaining CPUs 2 are sequentially invalidated with respect to the CACHE 4 incorporated therein.

FIG. 6 is a time chart showing an execution procedure of a block store instruction according to a conventional serialization control method. In the figure, “CPU _n (0−
3) "indicates four CPUs with n = 0 to 3 (2 in FIG. 5).
Shows that a series of block store instructions are issued from the CPU. The "MCU" in the second column indicates that the MCU 5 receives each block store instruction from the CPU and performs internal processing (because an instruction other than the block store instruction is received from each CPU). , A process such as selecting only a block store instruction from among them). After this internal processing, the above-described invalidation command is issued. “CPU0 (cache)” is 1
This shows that the MCU 5 invalidates the CACHE 4 of # 0 of the CPU 2 according to one block store instruction. This means that other "CPU1 (cach
e) "," CPU2 (cache) ", and the like. The" CPU3 (cache) "
3 shows a state in which invalidation is performed on CACHE4 of No.3. The same applies to the next block store instruction issued subsequent to this block store instruction.

The MCU 5 performs the first invalidation corresponding to the first block store instruction for all the CACHEs 4. At this time, the CPUs 2 also execute some processing unique to each of the CACHEs 4. The time until the conversion is completed is not the same for each CPU 2. In the example of this figure, C
CACHE4 (CPU1) in PU1 # 1 (CPU1)
The invalidation for (cache)) ends the latest. The MCU 5 waits for the end of the latest invalidation, and executes the second invalidation corresponding to the second block store instruction. In the example of this figure, CACHE4 (CPU2 (cache)) in # 2 (CPU2) of CPU2 ends latest, and after this end, MCU5 starts the third invalidation. As soon as the invalidation is completed, writing of “0” to the MSU 5 and updating of the KSU 6 are executed as described above, but are not shown in the figure.

[0012]

As is apparent from FIG. 6, in the conventional control of the execution order for block store instructions, the next block store instruction is executed after the invalidation processing for all CPUs 2 is completed. That is, MCU5
In order to guarantee the execution order of the processing, the next following instruction waits until the processing based on the previous instruction is completed. This is serialization control.

As a result, each CPU is made to wait for a long time (see "CPU WAIT" in FIG. 6), and there is a problem that the operating rate of the entire information processing apparatus 1 is reduced. This problem is particularly remarkable when a series of store instructions such as a block store instruction are executed successively. For this reason, the effect of introducing the processing of the pipeline system described earlier is lost.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a block store instruction execution control method which does not reduce the operation rate of an information processing apparatus.

[0015]

FIG. 1 is a diagram showing a basic configuration of a block store instruction execution control system according to the present invention. The information processing apparatus 1 includes a central processing unit (CPU) 2
And a storage control unit (MCU) 5 which receives various request signals RQ output from and controls pipeline processing according to each request signal RQ. The means for controlling the pipeline processing is shown as pipeline processing control means 13 in the figure.

The feature of the present invention resides in that the present invention comprises a counter means 11 and a request selector means 12 which operates under the supervision of the counter means 11. These are provided in a storage control unit (MCU) 5. The counter means 11 outputs the request signal R
It is incremented when Q is a request signal based on a block store instruction, and decremented when it is detected that the execution of the block store instruction has been completed.

The request selector 12 controls the input of the request signal RQ according to the count value of the counter 11. When the count value of the counter means 11 is not zero, the request selector means 11 preferentially selects only the request signal based on the block store instruction and continuously executes the processing based on the block store instruction.

In the figure, CMP (complete) is an execution completion signal indicating that the completion of execution of the block store instruction is detected. The other components, MSU3, CACHE (CAC) 4, and K
SU6 is as described above. FIG. 2 is a time chart showing a control procedure according to the block store instruction execution control method according to the present invention. How to read this diagram
Is the same as However, in FIG. 2, the count value of the counter means (COUNTER) 11 is 0, 1, 2, or 3.
It is shown as ...

In the figure, a,
A continuous block store instruction is issued as shown in b, c, d, and this is sent as a continuous request signal RQ to the MCU.
5 is output. MCU5 which receives these sequentially,
A predetermined selection is made by the request selecting means 12 and an order is output to each CPU 2. This order a '
Is an invalidation for CACHE4 in the case of a block store instruction.

If the request signal is a request signal based on a block store instruction a, the counter means 1
In the case of 1, the counter value is incremented (+1) (FIG. 2
"1" in the column of "COUNTER"). The invalidation for CACHE4 in each CPU is executed based on the invalidation order a '. The earliest completion of this invalidation was C
CACHE4 in CPU # 2 of PU2 (CPU2 (cac
he)), and a slight temporal space S occurs before the next order b '. On the other hand, the invalidation was completed latest at the CACHE4 (C
PU1 (cache)).

In the present invention, when the next order b '(invalidation) following the previous order a' is output from the MCU 5, the above-mentioned invalidation of the CPU 2 for CACHE 4 in # 1 has not been completed. Also, the processing according to the order b 'is performed continuously. Thereby, the processing time of the block store instruction is reduced. However, for that purpose, monitoring by the counter means 11 is necessary. When the order b 'is output, the count value of the counter means 11 is incremented from 1 to 2. If the counter value is increased to 3 or 4, execution of the block store instruction is no longer possible. Because CACHE
This is because the number of orders will be greater than the number of completed invalidations of No. 4.

Therefore, the counter value of the counter means 11 is:
When the invalidation processing for one order is completed for all CPUs, the value is immediately decremented by one, and the counter value is reduced to as small as possible
Try to keep the number close to. This is because the smaller the counter value is, the more room there is for receiving request signals one after another. Referring again to FIG.
Count value (COUNTER) is incremented from 0 → 1 → 2 → while the order a ′, b ′... Based on the request signals a, b.
Each time U invalidates one CACHE4, it is decremented as 2 → 1. In the figure, when the CPU 1 (cache) ends the invalidation at the end of the first invalidation, the counter value decreases as 2 → 1, and the CPU 2 (cache) ends at the end of the second invalidation. When the invalidation is completed, the counter value decreases as 2 → 1.

As described above, the request selector means 12
Allows a series of block store instructions to be executed continuously (without gaps) under monitoring by the counter means 11. As a result, the waiting time of the CPU is shown in FIG.
As shown in FIG. 6 as “CPU WAIT”,
It is significantly shorter than "CPU WAIT" shown in (conventional). Thus, the operation rate of the entire information processing apparatus 1 is improved.

There are the following two modes of monitoring the request selector means 12 by the counter means 11. (I) When the count value of the counter means 11 is zero,
The request selector means, according to a predetermined priority,
Various request signals output from the central processing unit 2 are selected (as before).

(Ii) When the count value of the counter means 11 is
When the predetermined upper limit is reached, the request selector 12 stops selecting the request signal based on the block store instruction. That is, the block store instruction is not executed. This is because the number of inputs of the block store instruction is more than the number of execution completions of the block store instruction.

As described above, according to the present invention, it is only necessary to introduce a simple device called the counter means 11, and there is an advantage that the burden is reduced both in cost and hardware. This advantage is even more pronounced in contrast to the following disadvantages. In general, there is a technique called parallel execution using a pipeline to improve the operation rate, but it is very troublesome to know that all the processes for continuously executing a series of block store instructions have been completed. . For example, a signal indicating the ID of the command is added to the completion notification signal from each CPU, and a method of knowing the command that has been processed among the commands being processed by this ID, a method of inquiring each CPU about the processing status, etc. However, there is a disadvantage that the number of signal lines between CPUs increases, the protocol becomes complicated, and the access between CPUs increases.

[0027]

FIG. 3 is a diagram showing a configuration example of an information processing apparatus according to the present invention. The same components as those already described are denoted by the same reference numerals or symbols. In the figure, the MCU 5 includes a counter unit 11, a request selector unit 12, and a pipeline processing control unit 13. In addition, the CPU 2 has two
Although shown in two places, both are exactly the same. This is simply divided into a request issuing function (upper side) and an order execution function (right side).

In the figure, CNT = 0, 0 <CNT <N and CNT ≧ N represent monitoring conditions of the counter means 11, and CNT is the above-mentioned count value. The block store instruction control method of the present invention is particularly applicable to 0 <CNT
It functions effectively under the condition of <N. Whether or not a block store instruction has been input, more precisely, whether or not the block store instruction has been selected from one of various request signals by the request selector means 12 and output from the means 12, is determined by the counter means 11. This is important information.

Therefore, in the configuration example of FIG.
The determination unit 15 is provided in 1 together with the counter. The determination unit 15 determines whether the request signal RQ based on the block store instruction has been output from the request selector 12. The determination unit 15 includes a decoder that decodes a code specified by the request signal.

The counter means 11 increments the count value by the output of the decoder, while the execution completion signal CM indicating that the execution of the block store instruction has been completed.
Decrement by P. This execution completion signal CMP
FIG. 4 shows an example of the means for generating. FIG.
FIG. 3 is a diagram illustrating a more specific configuration example of an information processing apparatus.
In this figure, the MCU 5 is divided into two parts on the left side of the figure and on the lower side of the center, but both are the same. It is only shown by function. The latter MCU 5 (lower center in the figure) shows the means (16) for generating the above-mentioned execution completion signal CMP. The detection unit 16 detects that the execution of the block store instruction has been completed (“invalidation end” in the drawing).

More specifically, the detection unit 16 is realized by an existing physical address / logical address conversion table in the storage control unit (MCU) 5, and the address in the physical address / logical address conversion table is When all the blocks are invalidated by the execution of the block store instruction, it detects that the execution of the block store instruction has been completed and outputs it as an execution completion signal CMP.

In FIG. 4, the same group of CPUs 2 as in FIG.
) And the order receiving side including CACHE4. The request signal output from each of the plurality of CPUs 2 corresponds to a port P corresponding to each CPU 2.
And is selected by the request selector 12. Other configurations of the MCU 5 (left side in FIG. 4) are the same as those in FIG.

[0033]

As described above, according to the present invention, the processing time of a series of successive block store instructions is reduced. The waiting time of CPU2 (CPU WAIT)
And the operating rate of the entire information processing apparatus can be improved.
For this purpose, the newly added hardware is a counter (1
Only 1), it is also economical.

Further, the instruction execution order can be easily controlled only by using the count value of the counter (11) as a guide.
Also, there is an effect that issuance of an excessive instruction can be easily suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a block store instruction execution control system according to the present invention.

FIG. 2 is a time chart showing a control procedure according to a block store instruction execution control method according to the present invention.

FIG. 3 is a diagram illustrating a configuration example of an information processing apparatus according to the present invention.

FIG. 4 is a diagram illustrating a more specific configuration example of an information processing apparatus.

FIG. 5 is a basic block diagram illustrating an example of a general information processing apparatus to which the present invention is applied.

FIG. 6 is a time chart showing an execution procedure of a block store instruction according to a conventional serialization control method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus 2 ... Central processing unit (CPU) 3 ... Main storage unit (MSU) 4 ... Buffer storage unit (CACHE) 5 ... Storage control unit (MCU) 6 ... Key storage unit (KSU) 7 ... Input / output unit (I / O) 11 ... Counter means 12 ... Request selector means 13 ... Pipeline processing control means 15 ... Determining unit 16 ... Detecting unit

Claims (3)

[Claims] 1. A storage controller (MC) that receives various request signals output from a central processing unit (CPU) and controls pipeline processing corresponding to each request signal.
U), the storage control device is incremented when the request signal is a request signal based on a block store instruction, and decremented when detecting that execution of the block store instruction is completed. And a request selector for controlling the input of the request signal in accordance with the count value of the counter means. The request selector means, when the count value of the counter means is not zero, the block An execution control method for a block store instruction in an information processing device, wherein priority is given to selecting only a request signal based on a store instruction and processing based on the block store instruction is continuously executed. 2. The request selector according to claim 1, wherein when the count value of said counter is zero, said request selector selects various request signals output from said central processing unit according to a predetermined priority. Execution control method for block store instructions. 3. The block store according to claim 1, wherein when the count value of said counter means reaches a predetermined upper limit, said request selector means stops selecting a request signal based on said block store instruction. Instruction execution control method.