JPH113050A - Plasma address display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the increase in a resolution of a plasma address display device without affecting an aperture rate and an electrical resistance of a signal electrode. SOLUTION: A plasma address display device consists of display cell 1 modulating incident light into exit light according to picture signals for displaying a picture, and a plasma cell 2 surface-joining with the display cell and scanning it. The plasma cell 2 has discharge channels 5 arranged in lines and discharges successively to scan them line-sequentially. The display cell 1 has signal electrodes 10 arranged in columns and forms picture elements 11 at the points of intersecting the discharge electrodes 5 and also impresses the picture signals synchronizing with the linesequential scanning to modulate incident light at each picture element 11. Picture elements for two lines are specified for discharge channels for one line. Namely, the intersections of each signal electrode 10 and the discharge channels 5 are partially shielded by a mask M according to a predetermined pattern, and transparent parts left at the intersections are distributed to the picture elements 11 for any one line, and picture signals are impressed on picture elements 11 for two lines at the same time by means of discharge of the discharge channels 5 for one line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a plasma addressed display device having a flat panel structure in which a display cell and a plasma cell are overlapped. More specifically, the present invention relates to a technique for increasing the resolution of a pixel formed in a plasma addressed display device.

[0002]

2. Description of the Related Art A plasma address display device is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-265931, and its structure is shown in FIG. As shown, the plasma addressed display device has a flat panel structure including a display cell 1, a plasma cell 2, and a common intermediate sheet 3 interposed therebetween. The intermediate sheet 3 is made of an extremely thin plate glass or the like and is called a micro sheet. The plasma cell 2 is composed of a lower glass substrate 4 joined to an intermediate sheet 3, and an ionizable gas is sealed in a gap between the two. A stripe-shaped discharge electrode is formed on the inner surface of the lower glass substrate 4. These discharge electrodes function alternately as anode A and cathode K. Since the discharge electrodes can be printed and baked on the flat glass substrate 4 by a screen printing method or the like, they are excellent in productivity and workability. A partition wall 7 is formed immediately above the discharge electrode along the anode A, and a gap filled with an ionizable gas is divided to form a discharge channel 5. The partition wall 7 can also be printed and fired by the screen printing method, and the top portion is in contact with one surface side of the intermediate sheet 3. A plasma discharge is generated between an anode A on both sides and an intermediate cathode K in a discharge channel 5 surrounded by a pair of partition walls 7. In addition, the intermediate sheet 3
And the lower glass substrate 4 are joined to each other by a glass frit or the like.

On the other hand, the display cell 1 is configured using a transparent upper glass substrate 8. The glass substrate 8 is bonded to the other surface of the intermediate sheet 3 with a sealing material or the like via a predetermined gap, and a liquid crystal 9 is sealed in the gap as an electro-optical material. A signal electrode 10 is formed on the inner surface of the upper glass substrate 8. Matrix pixels are formed at the intersections of the signal electrodes 10 and the discharge channels 5. The color filter 1 is provided on the inner surface of the glass substrate 8.
3 is also provided, and for example, RGB three primary colors are assigned to each pixel. The flat panel structure having such a configuration is of a transmission type. For example, the plasma cell 2 is located on the incident side, and the display cell 1 is located on the emitting side. Further, a backlight 12 is attached to the plasma cell 2 side.

In the plasma addressed display device having such a configuration, a row-shaped discharge channel 5 in which plasma discharge is performed is switched in a line-sequential manner and scanned, and an image is applied to a column-shaped signal electrode 10 on the display cell 1 side in synchronization with the scanning. Display driving is performed by applying a signal. When a plasma discharge is generated in the discharge channel 5, the inside becomes almost uniformly at the anode potential, and pixel selection is performed for each row. That is, the discharge channel functions as a sampling switch. When an image signal is applied to each pixel while the plasma sampling switch is turned on, sampling is performed and lighting or extinguishing of the pixel can be controlled. Even after the plasma sampling switch is turned off, the image signal is held in the pixel as it is. That is, the display cell 1 performs image display by modulating incident light from the backlight 12 into outgoing light in accordance with an image signal.

FIG. 8 is a schematic diagram showing only two pixels cut out. In this figure, only two signal electrodes 101 and 102, one cathode K1, and one anode A1 are shown for easy understanding. Individual pixel 1
1 has a laminated structure composed of the signal electrodes 101 and 102, the liquid crystal 9, the intermediate sheet 3, and the discharge channel. The discharge channel is substantially connected to the anode potential during the plasma discharge. In this state, each signal electrode 101, 1
When an image signal is applied to the liquid crystal 02, charges are injected into the liquid crystal 9 and the intermediate sheet 3. On the other hand, when the plasma discharge ends, the discharge channel returns to the insulating state, and becomes a floating potential, and the injected charge is held in each pixel 11. A so-called sampling hold operation is performed. Accordingly, the discharge channels function as individual sampling switching elements provided in the individual pixels 11, and are thus schematically represented using the switching symbols S1. On the other hand, the liquid crystal 9 and the intermediate sheet 3 held between the signal electrodes 101 and 102 and the discharge channel function as sampling capacitors. Sampling switch S1 by line sequential scanning
Is turned on, the image signal is held by the sampling capacitor, and each pixel is turned on or off according to the signal voltage level. Even after the sampling switch S1 is turned off, the signal voltage is held in the sampling capacitor and the active matrix operation of the display device is performed. Note that the effective voltage actually applied to the liquid crystal 9 is determined by the capacitance division with the intermediate sheet 3.

[0006]

In the plasma addressed display device having the above-mentioned structure, it is necessary to increase the density of pixels arranged in a matrix when increasing the resolution.
In order to miniaturize the pixel in the horizontal direction, the line width of the signal electrode may be reduced. Also, in order to make the pixel finer in the vertical direction,
What is necessary is just to shorten the arrangement pitch of the discharge channels. However, the individual discharge channels are separated by partition walls. It is difficult to make the thickness of the partition extremely thin from the viewpoint of processing technology, and the minimum thickness is determined in order to secure mechanical strength and the like. For this reason, when the arrangement pitch of the discharge channels is reduced, the portion occupied by the thickness of the partition wall becomes relatively large, and the area of the opening through which light is actually transmitted is sacrificed. In other words, as the number of discharge channels, that is, the number of scanning channels increases, the aperture ratio of the panel decreases.

One measure for addressing this problem is disclosed in
-265933, which is shown in FIG.
As shown, the signal electrodes 101, 101 ', 10
, Are row-shaped discharge channels 51, 5
2, 53, 54,..., And pixels are defined at the intersections. Each signal electrode has a pattern that is divided into two at the intersection. That is, each signal electrode is a signal electrode 1 corresponding to the upper half of each discharge channel 51-54.
, 01, 102, 103, 104,... And the signal electrodes 101 ′, 1 corresponding to the lower half of each of the discharge channels 51 to 54.
02 ', 103', 104 ',... Thus, the discharge channels 51-
The signal electrodes arranged orthogonally to 54 are divided into a plurality of units in each scanning unit to form a multiplex matrix. More specifically, the signal electrodes are divided into upper and lower parts in one discharge channel to form a double matrix, and there are two pixel rows (two scanning lines) for one discharge channel. The operation equivalent to is performed. Therefore, if the number of scanning lines is constant, the arrangement pitch of the discharge channels is halved, and processing becomes easy. However, in order to simultaneously write a plurality of rows of pixels into one discharge channel, a portion where the signal line width becomes extremely narrow occurs as shown in FIG. 9 due to the necessity of separating the signal electrodes. . The signal voltage applied to the signal electrode is limited by a time constant determined by the product of the electrode resistance and the capacitance of the pixel. If the resistance of the signal electrode becomes extremely high, it becomes impossible to perform sufficient writing to all pixels included in one screen within one frame time.

Generally, in order to perform high-resolution display using an active matrix type color display device, it is necessary to increase the number of pixels in a screen. Along with this, the size of one pixel becomes smaller, and the time allocated for writing becomes shorter. In the case of a plasma addressed display device, the size of a pixel is determined by the arrangement pitch of discharge channels and the width of a signal electrode. In the plasma addressed display device, it is necessary to form partitions to separate each discharge channel. Therefore, as the arrangement pitch is reduced, the existence of the partitions becomes an obstacle, and the aperture ratio of the panel is significantly reduced. As a means for avoiding this, a method of writing image signals for a plurality of scanning lines in one discharge channel has been proposed as described above. In this method, discharge channels are created at an arrangement pitch corresponding to the number of scanning lines to be written simultaneously, and image signals stored in a line memory are simultaneously written by plasma discharge of one discharge channel. However, this method also has a disadvantage, and it is necessary to divide the signal electrode into a plurality of parts in a pixel. as a result,
The resistance of the signal electrode increases. Then, the voltage waveform applied to the signal electrode becomes dull due to the effect of the time constant determined by the product of the electrode resistance and the capacitance of the display pixel, so that a predetermined signal voltage cannot be applied to the signal electrode.

[0009]

SUMMARY OF THE INVENTION In view of the above-mentioned problems in the prior art, the present invention provides a plasma addressed display device capable of realizing high resolution display while suppressing a decrease in aperture ratio and an increase in resistance of signal electrodes. The purpose is to do. The following measures were taken to achieve this purpose. That is, the plasma addressed display device according to the present invention has, as basic components, a display cell that modulates incident light into outgoing light in accordance with an image signal to display an image, and a plasma cell that is surface-bonded to the display cell and scans the display cell. And a flat panel structure comprising: The plasma cells have discharge channels arranged in rows and discharge sequentially to scan the display cells line-sequentially. On the other hand, the display cell has signal electrodes arranged substantially in a row and forms pixels at intersections with the discharge channels, and applies an image signal in synchronization with the line-sequential scanning to apply incident light to each pixel. Perform modulation. As a feature, a plurality of rows of pixels are defined in one row of discharge channels, and the intersection of each signal electrode and the discharge channel is partially masked in accordance with a predetermined pattern, and the portion left at the intersection is determined. Then, the image signals are distributed to the pixels for one row, and the image signals are simultaneously applied to the pixels for a plurality of rows by the discharge of the discharge channel for one row.

Preferably, the predetermined pattern is a lattice pattern in which a masked light-shielding portion and a transmissive portion which is left as a pixel from the mask are arranged in a checkered pattern. Preferably, in the signal electrode, the line width of the masked light-shielding portion is narrow and the line width of the unmasked transmission portion is widened to the extent that the problem of wiring resistance does not occur. Also preferably, the discharge channel includes a pair of partition walls forming a row-like space, an anode electrode disposed below each partition wall, and a cathode electrode disposed between the anode electrodes on both sides in the space. That is, one row of pixels is defined between one partition and the cathode electrode, and another row of pixels is defined between the other partition and the cathode electrode. More preferably, an image processing means for performing two-dimensional filtering of an image signal in advance so as to adapt to a predetermined pattern is provided.

According to the present invention, in a plasma addressed display device, pixels are arranged in, for example, a checkerboard pattern by partially masking signal electrodes arranged in a generally striped manner in each discharge channel. Two rows of pixels (two scanning lines) are provided in the discharge channel. As a result, the density of pixels can be increased without sacrificing the aperture ratio or the electrical resistance of the signal electrode, and high-resolution display is realized.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic diagram showing one embodiment of a plasma addressed display device according to the present invention,
(A) is a partial plan view, and (B) is a partial sectional view.
As shown in FIG. 1B, the present plasma addressed display device modulates incident light into outgoing light in accordance with an image signal to display an image, and a plasma cell 2 which is surface-bonded to the display cell 1 and scans the display cell. And a flat panel structure comprising: The plasma cell 2 has discharge channels 5 arranged in rows, and sequentially generates a plasma discharge to scan the display cell 1 line-sequentially. The discharge channel 5 includes a pair of partition walls 7 forming a row-like space, and an anode electrode A disposed below each partition wall.
And a cathode electrode K arranged between the anode electrodes A on both sides in the space. On the other hand, the display cell 1 has signal electrodes 10 arranged in a row and forms pixels at intersections with the discharge channels 5, and applies image signals in synchronization with line-sequential scanning to modulate incident light for each pixel. Perform Note that the display cell 1 and the plasma cell 2 are separated from each other by the intermediate sheet 3. The plasma cell 2 is configured using a substrate 4 bonded to the intermediate sheet 3 from below, while the display cell 1 is configured using a substrate 8 bonded to the intermediate sheet 3 from above. A liquid crystal 9 is held between the substrate 8 and the intermediate sheet 3 as an electro-optical material. A color filter 13 is formed on the inner surface of the substrate 8, and three primary colors of RGB are assigned to each pixel. A mask M is formed on the color filter 13 with a predetermined pattern.

As shown in FIG. 1A, in this embodiment, a plurality of rows of pixels 11 are defined in one row of discharge channels 5. For this purpose, the intersection of each signal electrode 10 and the discharge channel 5 is partially shielded from light by a mask M in accordance with a predetermined pattern, and the portion left at each intersection is replaced by one row of pixels 1.
Distribute to 1. With such a configuration, an image signal can be simultaneously applied to the pixels 11 for a plurality of rows by the plasma discharge of the discharge channels 5 for one row. In the present embodiment, one row of pixels 11 is defined between one partition 7 and the cathode electrode K, and another row of pixels 11 is defined between the other partition 7 and the cathode electrode K. . The predetermined pattern is a lattice pattern in which a masked light-shielding portion and a transparent portion left from the mask and becoming a pixel 11 are arranged in a checkered pattern. Preferably, in the signal electrode, the line width of the masked light-shielding portion is narrow and the line width of the unmasked transmission portion is widened to the extent that the problem of wiring resistance does not occur.

FIG. 3A shows pixels R1 and G belonging to the upper row.
1, B1 and pixels R2, G2, B2 belonging to the lower row. A set of R1, G1, and B1 is one display unit. In this specification, this display unit is hereinafter referred to as “pixel trio”.
I will call it. As apparent from the figure, the pixel trio (R1, G1, B1) has a dimension of P / 2 in the vertical direction and a dimension of W in the horizontal direction. Here, P is the arrangement pitch of the discharge channels 5. Other pixel trios (R2, G
2, B2) also has a vertical dimension of P / 2 and a horizontal dimension of W. As described above, according to the present invention, the vertical size of the pixel trio is equal to the arrangement pitch P of the discharge channels 5.
, And miniaturization has been achieved.

According to the present invention, a stripe-shaped color filter 13 generally used in a color display device corresponds to each signal electrode 10 within one discharge channel 5 as shown in FIG. The pattern of the mask M is created so as to divide the stripe of the color filter into two.
Thereby, two pixel rows can be provided in one discharge channel 5 in the vertical direction. Writing is performed simultaneously on two pixel rows. With such a configuration, the number of the partition walls 7 necessary for forming the discharge channel 5 used as the plasma switching element can be reduced to half, and the aperture ratio of the panel is improved. As a result, it is possible to improve the display brightness and reduce the power consumption of the backlight. Further, since the number of discharge channels 5 is reduced by half, the number of times of switching of the discharge channels within one frame period is also reduced, so that a longer writing time per scanning line can be obtained, and the discharge channel side and the signal electrode side can be increased. And the load on the switching speed of the discharge channel can be reduced.

FIGS. 2A and 2B show a reference example of the plasma addressed display device, wherein FIG. 2A is a partial plan view and FIG. 2B is a partial sectional view. Basically, the present embodiment is the same as the embodiment shown in FIG. 1, and corresponding portions are denoted by corresponding reference numerals to facilitate understanding. The difference is that no mask is formed on the color filter 13.
In this case, the vertical dimension of the pixel trio (R1, G2, B1) is P equal to the arrangement pitch of the discharge channels 5, and
The horizontal dimension is W. Similarly, the other pixel trios (R
2, G1, B2), the vertical dimension is P and the horizontal dimension is W. As is clear from a comparison between FIG. 1 and FIG. 2, the vertical dimension of the pixel trio in the embodiment is half that of the reference example. However, the line width of the signal electrode 10 of the embodiment is half that of the reference example. This narrowing is relatively easy and there is no problem in processing.

FIG. 3 is a comparison of the embodiment shown in FIG. 1 and the reference example shown in FIG. (A)
Shows an embodiment, and (B) shows a reference example. If you try to equalize the vertical resolution in both,
In the embodiment, when the arrangement pitch of the discharge channels 5 is P, in the reference example, the arrangement pitch of the discharge channels 5 must be P / 2. As a result, as shown in (B), the ratio of the area of the partition wall 7 and the area of the cathode electrode K to the individual discharge channels 5 becomes relatively large, and the aperture ratio is sacrificed. On the other hand, as shown in (A), a sufficiently large aperture ratio can be secured in the embodiment. In other words, in the case where the resolution in the vertical direction is the same and the pitch in the vertical direction is small, the embodiment can obtain a large aperture ratio even in consideration of light shielding by the mask as compared with the reference example. The brightness of the screen can be improved accordingly. Preferably, in the signal electrode, the line width of the masked light-shielding portion is narrow and the line width of the unmasked transmission portion is widened to the extent that the problem of wiring resistance does not occur.

FIG. 4 shows another embodiment of the plasma addressed display device according to the present invention, which is shown in FIG. Note that FIG. 1A is a repeat of the previous embodiment shown in FIG. 1 for comparison. As shown in (B), in this embodiment, the line width of each signal electrode 10 is doubled as compared with the previous embodiment shown in (A). As a result, the pixel trio (R,
G, B) has a horizontal dimension of 2 W. However, as is apparent from the figure, even in the width W formed by bisecting 2W,
RGB pixels are included as trios in one discharge channel. Since the horizontal dimension of the pixel trio can be regarded as W in terms of driving, the occurrence of false colors is not noticeable. Therefore, with such a configuration, both the improvement of the horizontal resolution and the improvement of the electrical resistance of the signal electrode can be achieved.

FIG. 5 shows various modified examples of the mask pattern formed on the color filter. The present invention is not limited to the mask pattern shown in FIG.
Various mask patterns shown in FIGS. 5A to 5G can be selected. Further, it is also possible to use a mirror image symmetric pattern, an inverted symmetric pattern, a periodically equivalent pattern, a pattern in which RGB are exchanged, and the like of the mask pattern shown in FIG. In the patterns shown in FIGS. 5F and 5G, the vertical resolution is increased particularly for G pixels that are conspicuous from the viewpoint of visibility, and the vertical resolution is set for other R pixels and B pixels. Did not double. Naturally, the mask patterns shown in (F) and (G) are also included in the scope of the present invention.

FIG. 6 is a block diagram showing the overall configuration of the plasma addressed display device including the peripheral circuit section. The plasma address display device basically includes a panel 0 having a flat structure, a scanning circuit 22, and a signal circuit 23 as a basic configuration. The panel 0 has a laminated structure in which a display cell and a plasma cell are stacked on each other, and is basically as shown in FIG. That is, an intermediate sheet made of thin glass or the like is interposed between the display cell and the plasma cell. The display cell has column-shaped signal electrodes 10, while the plasma cell has row-shaped discharge channels 5. Discharge channel 5
Is composed of an intermediate cathode electrode K and anode electrodes A on both sides. Pixel 11 is defined at the intersection of signal electrode 10 and discharge channel 5. As described above, the pixels 11 are defined by the checkered mask pattern, and two rows of the pixels 11 are assigned to one row of the discharge channels 5. The pixels 11 are arranged in a grid to form a display screen. The scanning circuit 22 sequentially selects the discharge channels 5 to generate plasma discharge, and selects two pixel rows at a time. On the other hand, the signal circuit 23 supplies an image signal to the signal electrode 10 in synchronization with the discharge driving. A synchronizing circuit 27 is connected to the scanning circuit 22 and the signal circuit 23, and generates a synchronizing signal necessary for synchronizing the two. An image processing circuit 28 is connected to the signal circuit 23, and converts an externally supplied primary image signal into a secondary image signal suitable for driving the panel 0. Specifically, the image processing circuit 28 performs two-dimensional filtering of the primary image signal in advance so as to apply to a predetermined mask pattern, and supplies the result to the signal circuit 23 as a secondary image signal.

If the horizontal width of the pixel trio is assumed to be W in the structure as shown in FIG. 4B and the pixel trio is driven, the total number of the addressable pixels 11 becomes half of the structure of FIG. 4A. For this reason, the resolution in the physical sense also decreases. However, in the case of a general television signal or the like, there is often a correlation between adjacent images, so that a significant deterioration in image quality is not recognized as long as an appropriate mask pattern is used. However, in the case of an image that cannot be expected to correlate, such as a graphic display output from a computer, a decrease in resolution in a physical sense may greatly affect the display content. For example, in a checkerboard mask pattern, coloring occurs in oblique high-frequency components included in an image signal. In the present invention, in order to avoid such coloring, the image processing circuit 28 is provided, and the coloring problem can be avoided by recognizing a display pattern in advance and performing an appropriate two-dimensional filter processing corresponding to the pattern. . Here, a checkered mask pattern is taken as an example, but the arrangement of the mask pattern itself is not a major problem, but rather, a method of digital sampling (sampling) of an image signal and characteristics of a low-pass cutoff filter for the image signal are considered. This is very important.

[0022]

As described above, according to the present invention,
In a plasma address display device, for example, by applying a lattice-like mask pattern to a stripe-like signal electrode, it becomes possible to allocate at least two pixel rows to one discharge channel, and to increase the aperture ratio and the like. At least the resolution in the vertical direction can be increased without adversely affecting the signal electrode resistance. Thus, a high-resolution flat-type plasma addressed display device can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a partial plan view and a partial cross-sectional view illustrating an embodiment of a plasma addressed display device according to the present invention.

FIG. 2 is a partial plan view and a partial cross-sectional view showing a reference example of the plasma addressed display device.

FIG. 3 is a schematic diagram showing an embodiment and a reference example of a plasma addressed display device according to the present invention for comparison.

FIG. 4 is a partial plan view showing another embodiment of the plasma addressed display device according to the present invention.

FIG. 5 is a schematic view showing various examples of a mask pattern used in the plasma addressed display device according to the present invention.

FIG. 6 is a block diagram showing an overall configuration including peripheral circuits of the plasma addressed display device according to the present invention.

FIG. 7 is a sectional view showing an example of a conventional plasma addressed display device.

8 is a schematic diagram for explaining the operation of the conventional example shown in FIG. 7;

FIG. 9 is a plan view showing another example of the conventional plasma addressed display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Display cell, 2 ... Plasma cell, 3 ... Intermediate sheet, 4 ... Glass substrate, 5 ... Discharge channel, 7 ... Partition, 8 ... Glass substrate, 9 ..Liquid crystal, 10 ... signal electrode, 11 ... pixel, 12 ...
Backlight, 13: color filter, A: anode electrode, K: cathode electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 3/36 G09G 3/36

Claims (5)

[Claims] 1. A flat panel structure comprising: a display cell that modulates incident light into outgoing light in accordance with an image signal to display an image; and a plasma cell that is surface-bonded to the display cell and scans the display cell. The plasma cell has discharge channels arranged in rows and sequentially discharges and scans the display cells line-sequentially, while the display cells have signal electrodes arranged in substantially columns and at intersections with the discharge channels. A plasma address display device for forming pixels and applying an image signal in synchronization with the line-sequential scanning to modulate incident light for each pixel, wherein a plurality of rows of pixels are defined in one row of discharge channels. In accordance with a predetermined pattern, the intersection of each signal electrode and the discharge channel is partially masked, and the portion remaining at the intersection is divided into any one row of pixels, and the discharge of one row discharge channel corresponds to a plurality of rows. of A plasma addressed display device, wherein image signals are applied to pixels simultaneously. 2. The plasma address according to claim 1, wherein the predetermined pattern is a lattice pattern in which a masked light-shielding portion and a transparent portion left as a pixel from the mask are arranged in a checkered pattern. Display device. 3. The plasma addressed display device according to claim 2, wherein the signal electrode has a line width of a masked light-shielded portion smaller than a line width of an unmasked transmission portion. 4. The discharge channel includes a pair of partition walls forming a row-like space, an anode electrode disposed below each partition wall, and a cathode electrode disposed between the anode electrodes on both sides in the space. Wherein one row of pixels is defined between one partition and the cathode electrode, and another row of pixels is defined between the other partition and the cathode electrode. 2. The plasma addressed display device according to 1. 5. The plasma addressed display device according to claim 1, further comprising image processing means for performing two-dimensional filtering of an image signal in advance so as to adapt to said predetermined pattern.