JP2001195036A - Plasma address display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the lowering of a driving voltage by improving the driving system of plasma cells in which an AC type and a DC type are blended. SOLUTION: This plasma address display device has a flat panel 10 in which display cells which are provided with columnar signal electrodes Ys and plasma cells which are provided with row-like discharge channels Xs are laminated and pixels 11 are provided at intersections of respective signal electrodes Ys and respective discharge channels Xs, a scanning circuit 22 which selects pixels for every row by successively discharging the row discharge channels Xs, a signal circuit 21 which writes a picture signal in pixels 11 of a selected row by successively supplying the picture signal to the columnar signal electrodes Ys in comformity with the discharge of the discharge channel X. Each discharge channel X has a coated electrode C whose conductor surface is coated with a dielectric substance and an exposed electrode B whose conductor surface is not coated with a dielectric substance. After the scanning circuit 22 generates a preliminary discharge in the discharge channel X by holding the exposed electrode B to the ground potential and, on the other hand, by impressing a pulse on the coated electrode C, the circuit generates a principal discharge in the channel by holding the coated electrode C to the ground potential and, on the other hand, by impressing the pulse on the exposed electrode B and thus, the circuit makes it possible to perform the lowering of the driving voltage. Moreover, the impression order of the pulse may be exchanged in both electrodes B, C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma addressed display device in which a display cell and a plasma cell are overlapped. More specifically, the present invention relates to a scanning circuit configuration of a plasma cell having a coating electrode and an exposed electrode in one discharge channel.

[0002]

2. Description of the Related Art A plasma addressed display device is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-265931, and FIG. 11 shows the structure thereof. As shown, the plasma addressed display device has a flat panel structure including a display cell 1, a plasma cell 2, and a common intermediate sheet 3 interposed therebetween. The intermediate sheet 3 is made of an extremely thin plate glass or the like and is called a micro sheet. The plasma cell 2 is composed of a lower glass substrate 4 bonded to the intermediate sheet 3, and a gas that can be discharged is sealed in a gap between the two. A stripe-shaped discharge electrode is formed on the inner surface of the lower glass substrate 4. These discharge electrodes function as an anode electrode A and a cathode electrode K, respectively. Since the discharge electrodes can be printed on the flat glass substrate 4 by a screen printing method or the like, productivity and workability are excellent. The partition wall 7 is formed so as to partition the anode electrode A and the cathode electrode K one by one, and forms a discharge channel X by dividing a gap filled with a dischargeable gas. This partition wall 7 can also be formed by a screen printing method, and the top portion is in contact with one surface side of the intermediate sheet 3. Plasma discharge is generated between the anode electrode A and the cathode electrode K having opposite polarities in the discharge channel X surrounded by the pair of partition walls 7. The intermediate sheet 3 and the lower glass substrate 4 are bonded to each other by a glass frit or the like.

On the other hand, the display cell 1 is configured using a transparent upper glass substrate 8. The glass substrate 8 is bonded to the other surface of the intermediate sheet 3 with a sealing material or the like via a predetermined gap, and a liquid crystal 9 is sealed in the gap as an electro-optical material. A signal electrode Y is formed on the inner surface of the upper glass substrate 8. Matrix pixels are formed at the intersections of the signal electrodes Y and the discharge channels X.
A color filter 13 is also provided on the inner surface of the glass substrate 8, and for example, three primary colors of RGB are assigned to each pixel.
The flat panel having such a configuration is of a transmission type, for example, in which the plasma cell 2 is located on the incident side and the display cell 1 is located on the emitting side. The backlight 12 is connected to the plasma cell 2.
Attached to the side.

In the plasma address display device having such a configuration, a row-shaped discharge channel X in which plasma discharge is performed is switched in a line-sequential manner and scanned, and an image is applied to a column-shaped signal electrode Y on the display cell 1 side in synchronization with the scanning. Display driving is performed by applying a signal. When a plasma discharge is generated in the discharge channel X, the inside becomes almost uniformly at the anode potential, and pixel selection is performed for each row. That is, one discharge channel X corresponds to one scanning line and functions as a sampling switch. When an image signal is applied to each signal line in a state where the plasma sampling switch is turned on, sampling is performed and lighting or extinguishing of a pixel can be controlled. Even after the plasma sampling switch is turned off, the image signal is held in the pixel as it is. The display cell 1 is a backlight 1 according to an image signal.
The image display is performed by modulating the incident light from No. 2 into the outgoing light.

FIG. 12 is a schematic diagram showing only two pixels cut out. In this figure, two signal electrodes Y1 and Y2 and one cathode electrode K are shown for easy understanding.
One discharge channel X1 having one and one anode electrode A1 is shown. Each pixel 11 has a laminated structure including the signal electrode Y1 or Y2, the liquid crystal 9, the intermediate sheet 3, and the discharge channel X1. Discharge channel X1 is substantially connected to the anode potential during the plasma discharge. When an image signal is applied to each of the signal electrodes Y1 and Y2 in this state, charges are injected into the liquid crystal 9 and the intermediate sheet 3. On the other hand, when the plasma discharge ends, the discharge channel X
1 becomes a floating potential because it returns to the insulating state, and the injected charges are held in each pixel 11. A so-called sampling hold operation is performed. Accordingly, the discharge channel X1 functions as an individual sampling switching element provided in each of the pixels 11, and thus is schematically represented by using the switching symbol S1. On the other hand, the signal electrode Y
1, liquid crystal 9 held between Y2 and discharge channel X1
The intermediate sheet 3 functions as a sampling capacitor. When the sampling switch S1 is turned on by line-sequential scanning, an image signal is written to the sampling capacitor, and each pixel is turned on or off according to the signal voltage level. Sampling switch S1
The signal voltage is held in the sampling capacitor even after the device is turned off, and the active matrix operation of the display device is performed. Note that the effective voltage actually applied to the liquid crystal 9 is determined by the capacitance division with the intermediate sheet 3.

FIG. 13 shows a scanning process timing for sequentially discharging a row-shaped discharge channel X and a column-shaped signal electrode Y.
5 is a timing chart schematically showing signal processing timing for supplying an image signal to each pixel and writing the pixel signal to each pixel. 1
In general, during the selection period of a line (one scanning line), the discharge of the corresponding discharge channel X and the writing of the image signal to the corresponding pixel are completed. For example, in a VGA display device, the number of lines is 480, and thus 480 discharge channels are formed. In this case, each line is sequentially selected at a predetermined cycle (horizontal cycle, 1H = 32 μs). Therefore, the maximum discharge period assigned to the discharge channel X of each line is 1H = 32 μs. In the illustrated example, since the discharge of the discharge channel X and the writing of the image signal to the pixel are completed during 1H, the discharge period is set to 1H or less, for example, 13 μs. That is, a selection pulse having a pulse width of 13 μs is applied in the first half of 1H to discharge the discharge channel X, and an image signal is written in the second half of 1H. This is because the image signal is written in the process (decay) of returning to the original state after the occurrence of the discharge. For example, the corresponding image signal 1 is written at the time when the discharge to the line 1 ends. In the next horizontal cycle, line 2 is selected and the corresponding image signal 2 is written. In the next horizontal cycle, the line 3 is selected and the corresponding image signal 3 is written, and then the line 4 is selected and the corresponding image signal 4 is written.

[0007]

FIG. 14 is a cross-sectional view schematically showing one discharge channel formed in the plasma cell shown in FIG. The discharge channel X is of a so-called DC type, and is composed of the conductor 30 exposed at both the anode electrode A and the cathode electrode K. In the DC type, a pulse of negative polarity is applied to the cathode electrode K with respect to the anode electrode A to generate a DC plasma discharge in the discharge channel X. For this reason, a discharge voltage exceeding 400 V in absolute value is required, and there is a drawback that the drive voltage is high. or,
There is a disadvantage that the life of the exposed electrode surface is shortened due to abrasion of the sputtered surface by the plasma discharge.

The discharge channel is known to be of the AC type as well as the DC type, and has a sectional structure as shown in FIG. That is, a pair of coating electrodes C are formed in one discharge channel X. Each electrode C has a structure in which a lower conductor 40 made of a transparent conductive film and an upper conductor 30 made of a metal thin film are stacked, and is embedded in the dielectric 20. In some cases, M
gO may be deposited. In the AC type, an AC plasma discharge is generated by applying a discharge voltage between a pair of covered electrodes C covered with the dielectric layer 20. Unlike the DC plasma discharge, the AC plasma discharge utilizes charge / discharge of electric charges to / from the dielectric 20, so that the discharge current is suppressed autonomously. Since each electrode C is covered with the dielectric 20, there is an advantage that deterioration with time due to sputtering of plasma discharge is small. On the other hand, in order to keep the inside of the discharge channel X at the ground potential, in addition to the covering electrode C covered with the dielectric 20,
The necessity of the reference electrode R composed of the conductor 30 causes a disadvantage that the discharge channel structure is complicated. In the illustrated example, the reference electrode R is formed integrally with the partition wall 7 in order to increase the aperture ratio of the discharge channel X, so that the structure is further complicated.

A structure having the advantages of the AC type and the DC type described above has also been developed, and is referred to as a DAC type in this specification. DAC type plasma cells are disclosed, for example, in Japanese Patent Application Laid-Open Nos.
FIG. 16 shows a basic cross-sectional structure thereof. The DAC type discharge channel X includes a covered electrode C in which the conductor 30 is covered with the dielectric 20 and an exposed electrode B in which the conductor 30 is not covered with the dielectric. A predetermined discharge voltage is applied between the coated electrode C and the exposed electrode B,
Generate a plasma discharge. As described above, the DAC type has both the advantages of the DC type and the AC type. Specifically, with respect to electrode wear due to plasma discharge sputtering, since the dielectric material 20 is present on one of the coated electrodes C, the discharge current is limited by this, and the total discharge current becomes close to that of the AC type. Deterioration is suppressed. In general,
When electrode sputtering occurs, a part of the electrode material adheres to the glass substrate, so that the transmittance is reduced. 1000 for DAC type
After the operation for 0 hours, the transmittance degradation is 2.2% or less. On the other hand, in the DC type, the transmittance reduction reaches about 20% after 10,000 hours of operation. Also, if the electrode material adheres to the back surface of the intermediate sheet by plasma sputtering, the electrical separation between the signal electrodes on the display cell side becomes insufficient, and the display quality deteriorates. Again, the DAC type is greatly improved over the DC type. Further, the DAC type has almost no temperature dependency as compared with the DC type. On the other hand, as compared with the AC type, the DAC type has at least the exposed electrode B formed in the discharge channel X, and therefore does not need to form the reference electrode R, and has a simple structure. Furthermore, in the AC type, a laminate of a transparent conductive film and a metal thin film is used as an electrode in order to improve the aperture ratio.
It is not necessary to use a transparent conductive film in the mold.

[0010] However, even in the case of the DAC type, the discharge voltage is still high, which is an obstacle in forming the scanning circuit into an IC. Therefore, an object of the present invention is to improve the driving method of a DAC type plasma cell and realize a low voltage.

[0011]

The following means have been taken in order to achieve the above-mentioned object of the present invention. That is, the present invention provides a flat panel in which display cells having column-shaped signal electrodes and plasma cells having row-shaped discharge channels are stacked, and pixels are provided at intersections of each signal electrode and each discharge channel. A scanning circuit for sequentially discharging the row-shaped discharge channels to select pixels for each row, and supplying an image signal to the column-shaped signal electrodes sequentially according to the discharge of the discharge channel, and applying the image signal to the pixels of the selected row. In the plasma addressed display device having a write signal circuit, each discharge channel has a covered electrode whose conductor surface is covered with a dielectric, and an exposed electrode whose conductor surface is not covered with a dielectric. After applying a pulse to the coated electrode while maintaining the exposed electrode at the ground potential to cause a preliminary discharge, applying a pulse to the exposed electrode while maintaining the coated electrode at the ground potential to cause a main discharge Or After applying a pulse to the exposed electrode while maintaining the coated electrode at the ground potential to cause a preliminary discharge, applying a pulse to the coated electrode while maintaining the exposed electrode at the ground potential to cause a main discharge. Thus, writing of an image signal is enabled. Specifically, the scanning circuit charges the electric charge from the exposed electrode to the dielectric of the coated electrode in the preliminary discharge, and discharges the electric charge from the coated electrode to the exposed electrode in the main discharge, whereby each discharge is performed. The voltage of a pulse required for discharging a channel is reduced. Preferably, the scanning circuit repeats the preliminary discharge and the main discharge at least twice for each discharge channel to increase the efficiency of writing the image signal. In one embodiment, the scanning circuit applies a negative pulse to the coated electrode to cause a preliminary discharge and also applies a negative pulse to the exposed electrode to cause a main discharge, or to the exposed electrode. On the other hand, a negative pulse is applied to generate a preliminary discharge, and a negative pulse is applied to the coated electrode to generate a main discharge.
In addition, each discharge channel is partitioned by a pair of parallel partitions formed on the substrate, and electrodes shared by both discharge channels are arranged along the lower portion of each partition on the substrate. The part of the electrode belonging to one discharge channel is covered with a dielectric and functions as a covering electrode, and the part of the electrode belonging to the other discharge channel is not covered with a dielectric and functions as an exposed electrode. In one embodiment, the covering electrode includes a conductor pattern formed on the substrate and a transparent dielectric layer formed entirely on the substrate so as to cover the conductor pattern. In this case, each discharge channel is partitioned by a pair of parallel partitions formed on the substrate, and each exposed electrode is formed integrally with the partition. The conductor pattern is made of a metal thin film formed by sputtering or vacuum evaporation. Further, the conductor pattern is formed by laminating a transparent conductive film extending between adjacent partitions and a metal thin film disposed below one of the partitions.

According to the present invention, the plasma cell incorporated in the plasma addressed display device is a so-called DAC type,
Each discharge channel includes a covered electrode whose conductor surface is covered with a dielectric (insulator) and an exposed electrode whose conductor surface is not covered with an insulator. The plasma discharge current is applied to the pair of covered electrode and exposed electrode. It flows directly and alternately between them. This D
When driving the AC-type discharge channel, the covered electrode and the exposed electrode are alternately selected within one scanning period (horizontal cycle), and electric charges (hereinafter, referred to as wall charges) accumulated in the dielectric are superimposed. It is possible to reduce the discharge voltage by almost half compared with the conventional case. In some cases, by driving the pair of covered electrodes and the exposed electrodes over a plurality of scanning periods, the writing characteristics of the image signal can be improved. As described above, since the plasma addressed display device according to the present invention basically employs the DAC type, a long life can be obtained with a relatively simple structure. By employing a driving method using wall charges, it is possible to reduce the plasma discharge voltage by half while maintaining good display quality. Thereby, the configuration of the scanning circuit can be simplified.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic diagram showing an embodiment of a plasma addressed display device according to the present invention. As shown in the figure, the present plasma addressed display device mainly includes a panel 0, and additionally, a peripheral signal circuit 21, a scanning circuit 2 and the like.
2 and a control circuit 23. The basic configuration of panel 0 is the same as the panel of the conventional plasma addressed display device shown in FIG. That is, the panel 0 is composed of a display cell that modulates incident light into outgoing light in accordance with an image signal and displays an image, and a plasma cell that is surface-bonded to the display cell and performs scanning. The plasma cell has discharge channels X1 to Xn arranged in rows, and discharges sequentially to scan display cells line-sequentially. Each discharge channel X has a pair of electrodes C and B
And driven by the scanning circuit 22 for discharge.
The scanning circuit 22 is connected to each of the discharge channels X1, X2, X3,.
n discharge electrodes C1, B1, C2, B2, C3, B3,.
.. The display cell is scanned by sequentially applying a selection pulse to Cn and Bn. The display cell is a signal electrode Y1 arranged in a row.
To Ym, and the pixel 11 at the intersection with the discharge channel X
To form The signal circuit 21 is connected to the discharge channel X1 described above.
The image signal is applied to each of the signal electrodes Y1 to Ym in synchronization with the line-sequential scanning of Xn to Xn to modulate the incident light for each pixel 11. The control circuit 23 controls the synchronization between the signal circuit 21 and the scanning circuit 22.

As a feature, the plasma cell has a DAC type structure, and each discharge channel X has a covered electrode C whose conductor surface is covered with a dielectric and an exposed electrode B whose conductor surface is not covered with a dielectric. And In order to drive this DAC type plasma cell, the scanning circuit 22 applies a selection pulse to the coating electrode C while maintaining the exposed electrode B at the ground potential for each discharge channel X to cause a preliminary discharge.
While the covering electrode C is kept at the ground potential, a selection pulse is applied to the exposed electrode B to cause a main discharge, thereby writing an image signal to the pixel 11. Specifically, the scanning circuit 22 charges electric charges from the exposed electrode B to the dielectric material of the coated electrode C in the preliminary discharge, and discharges the wall charges from the coated electrode C to the exposed electrode B in the main discharge. The voltage of the selection pulse required for the plasma discharge in the discharge channel X is reduced (almost halved). In some cases, the scanning circuit 22 repeats the preliminary discharge and the main discharge at least twice for each discharge channel X, thereby improving the efficiency and stabilization of writing the image signal to the pixel 11. Preferably, the scanning circuit 22 applies a selection pulse of negative polarity with respect to the ground potential to the coating electrode C to cause a preliminary discharge, and also applies a selection pulse of negative polarity to the exposed electrode B to cause a main discharge.

FIG. 2 is a timing chart for explaining the operation of the plasma addressed display device shown in FIG.
In the figure, Y represents an image signal applied to the signal electrode Y,
B represents a selection pulse applied to each of the exposed electrodes B1 to Bn, C1 represents a selection pulse applied to the coating electrode C1 included in the first discharge channel X1, and C2 represents a coating pulse included in the next discharge channel X2. This represents a selection pulse applied to the electrode C2. As shown, all the selection pulses are negative with respect to the ground potential GND, for example, 275.
It has a voltage level of V and is almost halved compared to the conventional 400 to 500 V. Also, each of the discharge channels X1 to X
n is sequentially driven every horizontal period (1H = 32 μs), and the image signal Y is supplied accordingly. The time length of the image signal Y is 28 μs, and the time width of each selection pulse is 10 μs.
μs. However, the above numerical values are merely examples, and do not limit the scope of the present invention.

First, a pulse of negative polarity is applied to C1, and a predischarge (indicated by an asterisk) is generated at the fall.
At a timing 3 μs after that, the application of the image signal to the signal electrode Y starts. When the preliminary discharge occurs, a discharge current flows, so that the surface potential of the coating electrode C1 covered with the dielectric gradually increases due to the charging of the wall charges. At the timing, the selection pulse of C1 returns to GND. In accordance with this, the surface potential rises instantaneously. After a lapse of 5 μs, a selection pulse is applied to the exposed electrode B at a timing. As a result, a large positive and negative potential difference is generated between the surface potential of the coating electrode C1 and the surface potential of the exposed electrode B1,
The main discharge occurs as shown by the asterisk. As a result of this main discharge, C
1 is discharged, and the surface potential gradually changes toward GND. Thereafter, the selection pulse applied to the exposure electrode B is released at a timing. By this main discharge, writing of the image signal Y is executed. Thereafter, the image signal returns to GND at the timing before moving to the next horizontal cycle. Thereafter, when the process proceeds to the next horizontal cycle, similar driving is performed in the second discharge channel X2. That is, first, a selection pulse of negative polarity is applied to C2, and then a selection pulse is applied to all exposed electrodes B including B2.

As described above, in the driving method according to the present invention, a selection pulse is applied to each of the covered electrode and the exposed electrode within one scanning period. The plasma discharge occurs at the timing indicated by the asterisk, but the first preliminary discharge is relatively weak and its main purpose is to accumulate wall charges on the dielectric surface on the coated electrode C. In the next main discharge, the electric field due to the wall charges and the electric field due to the selection pulse are superimposed, so that a strong discharge occurs, and an image signal is written to the pixel mainly at this timing. In addition, the preliminary discharge becomes a pilot flame, so that the main discharge is more easily generated by a so-called priming effect. As described above, the discharge voltage was able to be almost halved by utilizing the wall charge and the priming effect. or,
In the case of the DAC type, writing of image signals to pixels can be performed uniformly, writing in halftone is stable, and display quality is not impaired. As a specific configuration of the scanning circuit, a driver is connected for each line on the coated electrode C side,
The exposed electrode B side can be collectively driven by a single discrete driver. The sequential application of the selection pulse to the pair of the covering electrode C and the exposed electrode B is preferably performed within 1H, but may be performed over a plurality of scanning periods in order to improve the writing characteristics.

FIG. 3 is a schematic sectional view showing a specific example of the structure of panel 0 shown in FIG. 1. Parts corresponding to those of the conventional structure shown in FIG. 11 are denoted by corresponding reference numerals. And make it easy to understand. Plasma cell 1 and display cell 2
Are joined to each other via the intermediate sheet 3. The display cell 2 is composed of a liquid crystal 9 held between a glass substrate 8 and the intermediate sheet 3. The color filter 13 and the signal electrode Y are formed on the inner surface of the glass substrate 8. On the other hand, the plasma cell 1 is composed of a glass substrate 4 joined to the intermediate sheet 3 via a partition wall 7. A pair of covered electrodes C and exposed electrodes B are formed in the discharge channels X partitioned by the pair of partition walls 7. The surface of the conductor 30 made of a metal thin film or the like is covered with the dielectric 20 in the covered electrode C. In contrast,
The exposed electrode B has the conductor 30 exposed as it is. Such a DAC type plasma cell configuration has the AC type shown in FIG.
Compared to the conventional plasma cell configuration, since the transparent conductive film is not interposed between the electrodes C and B and the glass substrate 4, the adhesion of the electrodes is excellent. In addition, since there is no dielectric in the light transmitting portions of the pair of electrodes C and B, there is no decrease in transmittance or contrast due to the dielectric. In the case of the AC type, it is necessary to perform vacuum baking in order to remove bubbles from the dielectric material in order to avoid a decrease in contrast, but in the case of the DAC type, it is not necessary.
In the DAC type, since the dielectric 20 covering the conductor 30 is local, it is not necessary to make it transparent, and the firing temperature can be set low, and damage to the conductor 30 and the like can be reduced. Further, as compared with the DC type shown in FIG. 14, since the dielectric 20 autonomously limits the discharge current, abnormal discharge is less likely to occur even if the gas pressure in the discharge channel X is increased. Therefore, by increasing the gas pressure to shorten the decay of metastable atoms and speeding up the scanning of the plasma cell, it becomes easy to deal with HDTV and the like.

FIG. 4 is a schematic partial sectional view showing another embodiment of the plasma addressed display device according to the present invention.
Parts corresponding to those in the previous embodiment shown in FIG. 3 are denoted by corresponding reference numerals to facilitate understanding. In this embodiment,
Both the coating electrode C and the exposed electrode B are shared in the adjacent discharge channel X. Specifically, discharge channel X
A conductor 30 is formed below each of the partition walls 7 for partitioning.
Conductor 3 belonging to one discharge channel separated by partition 7
The portion of 0 is covered with the dielectric 20 and functions as the covering electrode C, and the portion of the conductor 30 belonging to the other discharge channel is not covered with the dielectric 20 and functions as the exposed electrode B.

FIG. 5 is a schematic partial sectional view showing another embodiment of the plasma addressed display device according to the present invention.
Parts corresponding to those in the previous embodiment shown in FIG. 3 are denoted by corresponding reference numerals to facilitate understanding. In this embodiment,
The exposed electrode B is formed below each partition 7, while the covering electrode C is formed along the center of the discharge electrode X surrounded by the pair of partitions 7. Thus, in each discharge channel X, a plasma discharge is uniformly generated between the central coating electrode C and the exposed electrodes B on both sides thereof. The center covering electrode C is obtained by locally covering the conductor 30 with the dielectric 20. Generally, the dielectric 20 is black in order to prevent a decrease in contrast due to light scattering. Conductor 30 and dielectric 2
When both are formed using the screen printing method, the aperture ratio is about 50% in the design of, for example, a 42-inch VGA.

FIG. 6 is a schematic partial cross-sectional view showing still another embodiment of the plasma addressed display device according to the present invention, and portions corresponding to those of the previous embodiment shown in FIG. Numbers are attached to facilitate understanding. In the present embodiment, the conductor 30 formed on the glass substrate 4 is
The exposed electrode B is disposed on the surface of the dielectric 20 while the coated electrode C is formed by covering the entire surface with 0. In particular, if the exposed electrode B is formed integrally with the partition 7, the aperture ratio can be improved. The dielectric 20 formed entirely on the glass substrate 4 is transparent. As is clear from comparison with the previous embodiment shown in FIG. 3, the region shielded from light by the black dielectric can be used as an opening. Also, dielectric 2
The solid printing of 0 has a margin in positioning with respect to the conductor 30, and has an advantage that the manufacturing can be simplified. On the other hand, the exposed electrode B is disposed below the partition wall 7, and the aperture ratio can be improved. In this embodiment, the aperture ratio can be increased to about 70%. In addition, if the conductor 30 of the covered electrode C is not a thick film but a metal thin film formed by sputtering or vacuum deposition, its patterning can be precisely controlled by photolithography and etching.

FIG. 7 is a schematic partial cross-sectional view showing still another embodiment of the plasma addressed display device according to the present invention, and portions corresponding to those of the previous embodiment shown in FIG. To facilitate understanding. In this embodiment, the lower conductor 40 made of a transparent conductive film is used as a covering electrode.
And the upper conductor 30 made of a metal thin film is laminated, and this is embedded in the dielectric 20.
The lower conductor 40 made of a transparent conductive film extends between the pair of partition walls 7, while the conductor 30 made of the upper metal thin film is hidden under one partition wall 7. If a transparent conductor is used in this way, it is possible to further increase the aperture ratio,
For example, an aperture ratio of 80% can be achieved. The conductor 30 made of an upper metal thin film is provided as an auxiliary to eliminate the high resistance of the lower conductor 40 made of a transparent conductive film. As a result, a 42-inch VG
An A-type can achieve a maximum aperture ratio of 85%.

FIG. 8 is a modification of the previous embodiment shown in FIG. 7, and corresponding parts are denoted by corresponding reference numerals to facilitate understanding. In this example, the exposed electrode B is formed integrally at an intermediate portion of the partition 7, not at the bottom of the partition 7.

FIG. 9 is a schematic partial sectional view showing still another embodiment of the plasma addressed display device according to the present invention. The covering electrode C is formed by laminating the metal conductor 30 and the transparent conductor 40 and is covered with the dielectric 20. On the other hand, the exposed electrode B has the same laminated structure of the metal conductor 30 and the transparent conductor 40, and is formed on the surface of the dielectric 20.

FIG. 10 is a schematic diagram showing an additional embodiment regarding the driving method of the plasma addressed display device according to the present invention. As shown, the plasma cell has a discharge channel X
1, X2, X3, X4, and X5 are arranged in this order, and are separated from each other by a partition wall 7. The discharge channel X1 includes a covered electrode C1 covered with the dielectric 20, and an exposed electrode B1 formed on the dielectric 20, and a plasma discharge is generated between both electrodes. Similarly, the discharge channel X2 includes a pair of covered electrodes C2 and exposed electrodes B2. Hereinafter, the covering electrode C3 and the exposed electrode B3 are provided in the discharge channel X3.
Are formed. In the first horizontal period H1, the selection pulse is sequentially applied to the pair of electrodes C1 and B1 belonging to the discharge channel X1, and at the same time, the selection pulse is sequentially applied to the pair of electrodes C2 and B2 belonging to the adjacent discharge channel X2. You. Thus, in the first horizontal cycle H1, two discharges are generated in the discharge channel X1 including the preliminary discharge and the main discharge, and at the same time, two plasma discharges are generated in the adjacent discharge channel X2 by the preliminary discharge and the main discharge. . When shifting to the next horizontal cycle H2, a pair of electrodes C belonging to the discharge channel X2
2 and B2 are sequentially applied with the selection pulse, and at the same time, the selection pulse is sequentially applied to the pair of electrodes C3 and B3 belonging to the adjacent discharge channel X3. As a result, in the horizontal period H2, the preliminary discharge and the main discharge occur twice in the discharge channel X2, and at the same time, the plasma discharge occurs twice in the preliminary discharge and the discharge channel in the next discharge channel X3. Hereinafter, similarly, this sequential scanning is repeated. Here, for example, the discharge channel X2
Focusing on, the preliminary discharge and the main discharge are repeated twice over the horizontal periods H1 and H2, and the image signal Y can be sufficiently written.

FIG. 17 is a schematic partial sectional view showing another embodiment of the plasma addressed display device according to the present invention, and portions corresponding to those of the previous embodiment shown in FIG. To facilitate understanding. This embodiment has basically the same structure as the previous embodiment shown in FIG. 4, and the covered electrode C and the exposed electrode B are shared in adjacent discharge channels. That is, the conductor 30 is formed below each partition 7 that partitions the discharge channel. Conductor 30 belonging to one discharge channel separated by partition wall 7
Is covered with the dielectric 20 and functions as a covered electrode C, and the portion of the conductor 30 belonging to the other discharge channel is not covered with the dielectric 20 and functions as an exposed electrode B.

FIG. 17 shows only the n-th line (line n). The scanning direction of each line is from left to right as indicated by the arrow in the drawing. When attention is paid to the line n, the preceding electrode in the scanning direction is represented by xn, and the succeeding electrode is represented by xn + 1. Line n
Focusing on, first, a negative pulse is applied to the electrode xn, then a negative pulse is applied to the electrode xn + 1, and selection for the line n is performed. That is, in the present embodiment, first, a pre-discharge is performed by applying a negative pulse to the exposed electrode B with the covered electrode C as the ground potential, and then the exposed electrode B
Is applied as a ground potential, a negative pulse is applied to the coated electrode C to perform main discharge. On the other hand, in the previous embodiment shown in FIG. 4, the order of applying the negative polarity pulse is reversed.

FIG. 18 is a timing chart for explaining the operation of the embodiment shown in FIG. First, the electrode x
A negative pulse is applied to n, and a preliminary discharge occurs at the timing shown by. The pulse width of the negative polarity pulse is, for example, 13 μsec, and the voltage is, for example, −360V.
Note that one horizontal period (1H) is 20 μsec. Focusing on the line n, the electrode xn functions as the covering electrode B. At the next 1H, a negative pulse is applied to the electrode xn + 1. The electrode xn + 1 functions as the covering electrode C for the line n. Thus, the main discharge occurs at the timing. With this main discharge, the image signal applied to each signal electrode Ym is sampled and written to each pixel on line n. The width of the image signal per line is, for example, 18 μsec, and the voltage has a maximum amplitude of, for example, about ± 70 V. As shown, the polarity of the image signal is inverted for each line, and the image signal is driven by AC.

FIG. 19 is a schematic diagram for comparing the operation of the embodiment shown in FIG. 17 with the operation of the embodiment shown in FIG.
(A) shows the state after the preliminary discharge of the embodiment shown in FIG. 17, and (B) shows the state after the preliminary discharge of the embodiment shown in FIG. As is clear from a comparison between the two, the embodiment shown in FIG. 17 has a structure obtained by inverting the previous embodiment shown in FIG. Alternatively, it can be considered that the structure is the same and the scanning direction is reversed.
As shown in (A), in the present embodiment, first, the coating electrode C is kept at the ground potential, and a negative pulse is applied to the exposed electrode B to generate a preliminary discharge. Thereby, negative charges are accumulated in the dielectric 20 on the electrode xn + 1 side as shown in the figure. Thereafter, while the exposed electrode B (xn) is kept at the ground potential, a negative pulse is applied to the coated electrode C (xn + 1) to perform the main discharge. In this discharge, the discharge pulse voltage can be reduced by superimposing a voltage resulting from the negative charges stored in the dielectric 20. In addition, in this discharge, the covered electrode C functions as a cathode, while the exposed electrode B functions as an anode. When the main discharge occurs, the inside of the discharge channel X becomes almost the anode potential.
In this embodiment, since the electrode xn functioning as the anode is the exposed electrode B, the anode potential becomes the ground potential itself and is extremely stable. Therefore, a stable signal voltage can be written to the liquid crystal 9 with reference to the anode potential, and so-called DC offset does not occur.

On the other hand, as shown in FIG. 4B, in the previous embodiment shown in FIG.
, A pre-discharge is generated by applying a negative pulse. By this preliminary discharge, positive charges are accumulated in the dielectric 20 on the electrode xn side. Next, while the coated electrode C (xn) is grounded,
A negative pulse is applied to the exposed electrode B (xn + 1) to generate a main discharge. At this time, it is possible to reduce the main discharge pulse voltage by superimposing the voltage due to the positive charges. In this discharge, the coated electrode C side becomes the anode and the exposed electrode B side becomes the cathode. Since the anode is covered with the dielectric 20, the anode potential is not always at the ground potential, and the DC offset with respect to the liquid crystal 9 is −100 to −100.
There is about 150V. If the DC offset is left for several tens of hours after the first aging, it is relaxed and disappears on the surface. There is no practical problem if the apparatus is left for a long period of time or the offset value does not change. However, it is conceivable that long-term storage or offset unevenness may occur in the case of a product. Therefore, it is considered that the driving method shown in FIG. 17 in which the DC offset is essentially eliminated is desirable.

[0031]

As described above, according to the present invention,
The plasma cell incorporated in the plasma address display device is of a DAC type, can have a longer life than that of the DC type, and has a life almost similar to that of the AC type. D
It is easier to shorten the decay by increasing the gas pressure in the discharge channel as compared with the C type, and it is possible to cope with HDTV. Further, as compared with the AC type, a reference electrode and a transparent conductor are not required, and the structure is relatively simple. In addition, AC
As compared with the mold, the manufacturing process can be simplified such that the firing temperature of the dielectric is lower and vacuum firing is unnecessary. Further, in the present invention, a plasma discharge is generated by utilizing wall charges accumulated on the coated electrode, so that the discharge voltage can be reduced by almost half while maintaining a good display quality as compared with the DC type and the AC type. is there. Further, the aperture ratio can be improved up to 85% by devising the structure and arrangement of the covering electrode and the exposed electrode. In particular, by forming the coated electrode into a metal thin film, precise processing becomes possible, which can contribute to stabilization of the aperture ratio. In addition, as the structure of the coated electrode, the conductor pattern formed on the glass substrate is entirely covered with a transparent dielectric, thereby simplifying the manufacturing method and improving the yield. In particular, by applying a pulse to the exposed electrode while holding the coated electrode at the ground potential to cause a preliminary discharge, and then applying a pulse to the coated electrode while holding the exposed electrode at the ground potential to cause a main discharge, DC applied to liquid crystal
Offset can be suppressed, and reliability such as display quality and service life is improved.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing an overall configuration of a plasma addressed display device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the plasma addressed display device shown in FIG. 1;

FIG. 3 is a partial sectional view showing an embodiment of a plasma addressed display device according to the present invention.

FIG. 4 is a partial sectional view showing an embodiment of a plasma addressed display device according to the present invention.

FIG. 5 is a partial sectional view showing an embodiment of the plasma addressed display device according to the present invention.

FIG. 6 is a partial sectional view showing an embodiment of a plasma addressed display device according to the present invention.

FIG. 7 is a partial sectional view showing an embodiment of a plasma addressed display device according to the present invention.

FIG. 8 is a partial sectional view showing an embodiment of the plasma addressed display device according to the present invention.

FIG. 9 is a partial sectional view showing an embodiment of a plasma addressed display device according to the present invention.

FIG. 10 is a schematic view showing a modified example of the plasma addressed display device according to the present invention.

FIG. 11 is a schematic sectional view showing a conventional plasma addressed display device.

FIG. 12 is a schematic view for explaining the operation of the plasma addressed display device shown in FIG. 11;

FIG. 13 is a timing chart for explaining the operation of the plasma addressed display device shown in FIG. 11;

FIG. 14 is a partial sectional view showing an example of a conventional plasma addressed display device.

FIG. 15 is a partial sectional view showing another example of the conventional plasma addressed display device.

FIG. 16 is a partial sectional view showing another example of the conventional plasma addressed display device.

FIG. 17 is a partial sectional view showing an embodiment of a plasma addressed display device according to the present invention.

18 is a timing chart for explaining the operation of the plasma addressed display device shown in FIG.

FIG. 19 is a schematic diagram comparing the operation of the plasma addressed display device shown in FIGS. 4 and 17;

[Explanation of symbols]

0 ... panel, 1 ... display cell, 2 ... plasma cell, 3 ... intermediate sheet, 9 ... liquid crystal, 11 ...
Pixel, 21: Signal circuit, 20: Dielectric, 22
..Scanning circuit, 30 conductor, 40 conductor, X
..Discharge channels, C: coated electrodes, B: exposed electrodes

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/36 3/36 H01J 11/00 K H01J 11/00 17/49 K 17 / 49 G09G 3/28 Z (72) Inventor Masanobu Tanaka 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 2H089 HA36 QA12 TA07 2H093 NA16 NC09 ND22 ND35 ND53 5C006 AC22 BB18 BC03 FA46 5C040 FA09 GD03 5C080 AA10 BB05 DD01 DD29 FF11 FF12 JJ02 JJ04 JJ06

Claims (13)

[Claims] 1. A flat panel in which a display cell having a column-shaped signal electrode and a plasma cell having a row-shaped discharge channel are stacked, and a pixel is provided at an intersection of each signal electrode and each discharge channel; A scanning circuit that sequentially discharges the discharge channel of each of the rows to select a pixel for each row, and supplies an image signal to the signal electrodes in a column sequentially according to the discharge of the discharge channel, and writes the image signal to the pixels of the selected row. In a plasma addressed display device having a signal circuit, each discharge channel has a covered electrode whose conductor surface is covered with a dielectric, and an exposed electrode whose conductor surface is not covered with a dielectric. After applying a pulse to the coated electrode to cause a preliminary discharge while maintaining the exposed electrode at the ground potential,
A pulse was applied to the exposed electrode while maintaining the coated electrode at ground potential to cause a main discharge, or a preliminary discharge was generated by applying a pulse to the exposed electrode while maintaining the coated electrode at a ground potential. Thereafter, a pulse is applied to the coating electrode to generate a main discharge while the exposed electrode is maintained at the ground potential, thereby enabling writing of an image signal. 2. The method according to claim 1, wherein the scanning circuit charges the electric charge from the exposed electrode to the dielectric of the coated electrode in the preliminary discharge, and discharges the electric charge from the coated electrode to the exposed electrode in the main discharge. 2. The plasma addressed display device according to claim 1, wherein a voltage of a pulse required for discharging the channel is reduced. 3. The plasma addressed display device according to claim 1, wherein the scanning circuit repeats preliminary discharge and main discharge at least twice for each discharge channel to increase the efficiency of writing an image signal. 4. The scanning circuit applies a negative pulse to the coated electrode to cause a preliminary discharge, and also applies a negative pulse to the exposed electrode to cause a main discharge. 2. The plasma addressed display device according to claim 1, wherein a pre-discharge is generated by applying a negative pulse to the electrode, and a main discharge is generated by applying a negative pulse to the coated electrode. 5. Each of the discharge channels is partitioned by a pair of parallel partitions formed on the substrate, and electrodes shared by the discharge channels on both sides are arranged along the lower portion of each partition on the substrate. The portion of the electrode belonging to one discharge channel is covered with a dielectric and functions as a covering electrode, and the portion of the electrode belonging to the other discharge channel is not covered with a dielectric and functions as an exposed electrode. 2. The plasma addressed display device according to claim 1, wherein: 6. The coating electrode includes a conductor pattern formed on the substrate and a transparent dielectric layer formed entirely on the substrate so as to cover the conductor pattern. The plasma addressed display device according to claim 1. 7. The discharge channel according to claim 6, wherein each discharge channel is partitioned by a pair of parallel partitions formed on the substrate, and each exposed electrode is formed integrally with the partition. Plasma address display device. 8. The plasma addressed display device according to claim 6, wherein said conductor pattern is made of a metal thin film formed by sputtering or vacuum evaporation. 9. The conductive pattern according to claim 7, wherein the conductive pattern is formed by laminating a transparent conductive film extending between adjacent partition walls and a metal thin film disposed below one of the partition walls. Plasma address display device. 10. A display cell having a column-shaped signal electrode and a plasma cell having a row-shaped discharge channel are stacked.
A flat panel in which pixels are provided at the intersections of each signal electrode and each discharge channel, a scanning circuit for sequentially discharging the row-shaped discharge channels and selecting pixels for each row, and a column-shaped array in accordance with the discharge of the discharge channels A signal circuit that supplies an image signal to the signal electrode and writes the image signal to a pixel in a selected row; each discharge channel includes a covered electrode having a conductor surface covered with a dielectric, and a conductor surface made of a dielectric. In a driving method of a plasma addressed display device having an uncovered exposed electrode, the scanning circuit, while maintaining the exposed electrode at a ground potential, applying a pulse to the coated electrode to cause a preliminary discharge,
A pulse was applied to the exposed electrode while maintaining the coated electrode at ground potential to cause a main discharge, or a preliminary discharge was generated by applying a pulse to the exposed electrode while maintaining the coated electrode at a ground potential. Thereafter, a pulse is applied to the coating electrode to generate a main discharge while maintaining the exposed electrode at a ground potential, thereby enabling an image signal to be written, thereby driving the plasma addressed display device. 11. The scanning circuit according to claim 1, wherein the pre-discharge charges electric charges from the exposed electrode to the dielectric of the coated electrode, and discharges the electric charges from the coated electrode to the exposed electrode in the main discharge. 11. The driving method for a plasma addressed display device according to claim 10, wherein a voltage of a pulse required for discharging the channel is reduced. 12. The scanning circuit according to claim 10, wherein a pre-discharge and a main discharge are repeated at least twice for each discharge channel, thereby efficiently writing an image signal.
The driving method of the plasma addressed display device according to the above. 13. The scanning circuit according to claim 1, wherein a negative pulse is applied to the coated electrode to cause a preliminary discharge, and a negative pulse is applied to the exposed electrode to cause a main discharge.
11. The plasma addressed display device according to claim 10, wherein a negative pulse is applied to the exposed electrode to cause a preliminary discharge, and a negative pulse is applied to the coated electrode to cause a main discharge. Drive method.