JPH11297842A - Automatic layout wiring device, method of semiconductor integrated circuit, and storage medium loaded therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor integrated circuit to be lessened in dead space and improved in degree of integration, to reduce a manual operation carried out by an operator's hands so as to finish a design in a shorter time for a semiconductor integrated circuit, and to reduce operation failures. SOLUTION: An automatic layout wiring method of a semiconductor integrated circuit comprises a first step A1 where each of grouped wiring regions is indicated, a second step A2 where a second circuit which is designated and grouped in the first step A1 is automatically disposed in a prescribed arrangement region, a third step A3 where a power supply wiring is provided to the second circuit disposed in the second step A2, a fourth step A4 where a prescribed range which includes the above arrangement region is designated as an arrangement forbidden region where a following circuit is forbidden to be arranged, a fifth step A5 where a power supply wiring is provided to the first circuit driven by a primary power supply system, a sixth step A6 where the first circuit is automatically arranged, and a seventh step A7 where all wirings except the power supply wirings are automatically installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing apparatus for a semiconductor integrated circuit, a method therefor, and a recording medium recording the method, and more particularly, to a semiconductor integrated circuit including a circuit block driven by a backup power supply. Circuits, semiconductor integrated circuits including digital circuits and analog circuits, or
The present invention relates to a technique suitable for arrangement and wiring of semiconductor integrated circuits and the like including circuits driven by different voltages.

[0002]

2. Description of the Related Art Conventionally, a single semiconductor integrated circuit often requires a plurality of independent power supplies. In such a case, it is necessary to separate these power supply systems in the layout process. I was taking.

Referring to FIG. 8, there is a method in which all instances are grouped in a floor plan, and arrangement areas for different power supply systems are separated only by grouping. Although it is possible to separate the arrangement regions by this conventional technique, there are the following problems. The first problem is a decrease in the degree of integration. The reason is that the size of each group is generally different, and different power supply systems cannot overlap each other, so that the degree of freedom of the floor plan is reduced and the dead space region 16 in FIG. 8 is generated. was there.

[0004] The second problem is that TA related to layout is required.
Mistakes such as T and power short-circuit increase. The reason is that the separation of the power supply wiring relies on manual work. In particular, the power supply separation including the pre-buffer has a problem that the operation becomes complicated and the design time becomes long.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to reduce the dead space to improve the degree of integration, and further reduce the number of manual operations by a short time. It is an object of the present invention to provide a new semiconductor integrated circuit automatic placement and routing apparatus and a method thereof, which complete the design and reduce operation errors.

Another object of the present invention is to provide a recording medium on which the above method is recorded.

[0007]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, in the first aspect of the semiconductor integrated circuit arrangement / wiring method according to the present invention, the first circuit driven by the main power supply system and the first circuit driven by a power supply system different from the main power supply system are provided. A method of arranging and wiring a semiconductor integrated circuit including a second circuit, wherein a second circuit driven on a power supply system different from a main power supply system is grouped for each power supply system on a floor plan. A second step of automatically arranging the grouped second circuits specified in the first step in a predetermined arrangement area, and a second step of arranging the second circuits specified in the first step. A third step of performing power supply wiring of the circuit, a fourth step of generating a predetermined range including the layout area as a layout prohibited area for prohibiting the layout of subsequent circuits, and driving by the main power system. The first A fifth step of automatically arranging the first circuit, a sixth step of automatically arranging the first circuit, and a seventh step of automatically arranging all the wiring except for the power wiring. In a second aspect, the second to fourth steps are repeatedly performed for each power supply system in a region outside the set arrangement prohibition region. In addition, the third mode is characterized in that the arrangement area overlaps with an arrangement area of a different power supply system at first.

[0008] A first aspect of the arrangement and wiring apparatus for a semiconductor integrated circuit according to the present invention is that a first circuit driven by a main power supply system and a power supply system different from the main power supply system are provided. An automatic placement and routing apparatus for a semiconductor integrated circuit including a driven second circuit, wherein each of the second circuits driven by a power supply system different from a main power supply system in a floor plan is provided with a respective power supply. First means for grouping for each system, second means for automatically arranging the grouped second circuits specified in the first step in a predetermined arrangement area, and arranging in the second step A third means for performing power supply wiring of the second circuit, a fourth means for generating a predetermined area including the arrangement area as an arrangement prohibition area for prohibiting the subsequent circuit arrangement, and the main means. The first driven by the power system And fifth means for performing a power line of the road,
A sixth means for automatically arranging the first circuit, a seventh means for automatically arranging all wirings except the power supply wiring,
The second aspect is characterized in that
The arrangement and wiring performed by the second to fourth means are repeated for each power supply system in a region outside the set arrangement prohibition region.

A first aspect of the recording medium according to the present invention is as follows.
A computer program of a layout method of a semiconductor integrated circuit including a first circuit driven by a main power supply system and a second circuit driven for each power supply system different from the main power supply system is recorded. A first step of grouping the second circuits driven for each power supply system different from the main power supply system for each power supply system in a floor plan, and the first step A second step of automatically arranging the grouped second circuits specified in the above in a predetermined arrangement area; and a third step of performing power supply wiring of the second circuits arranged in the second step. A fourth area is generated in which a predetermined range including the arrangement area is set as an arrangement prohibited area for prohibiting the subsequent circuit arrangement.
And a first step driven by the main power supply system.
A fifth step of automatically arranging the first circuit, a sixth step of automatically arranging the first circuit, and a seventh step of automatically arranging all the wiring except for the power wiring. Each step is recorded in order to cause a computer to execute a series of processing. In a second aspect, the second to fourth steps are performed outside the set arrangement prohibited area. It is repeatedly executed for each power supply system in the area.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a layout process of a semiconductor integrated circuit having a plurality of independent power supply systems.
An object of the present invention is to provide a method of automatically performing power supply separation based on instance information for each power supply system. 1 and 2, information on instances driven by different power supply systems VDD2 and VDD3 different from the main power supply system VDD1 is given in advance, and the circuit of the power supply system VDD2 is used in the floor plan process based on the information. Placement area 2
And an arrangement area 4 of the circuit of the power supply system VDD3. Next, the arrangement and power supply wiring steps are automatically performed for each of the different power supply systems, and a process in which these steps are performed is set as an arrangement prohibited area. Finally, power supply wiring and circuit arrangement wiring of the main power supply system VDD1 are performed using an area other than the prohibited area.

According to the method of the present invention, the degree of integration can be improved,
It is possible to reduce T and reduce operation errors.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an automatic placement and routing apparatus for a semiconductor integrated circuit according to the present invention; FIG. 1 is a diagram showing circuit blocks arranged in groups for each power supply system of a semiconductor integrated circuit according to the present invention.
Are flowcharts showing specific examples of the automatic placement and routing method. In these figures, a first circuit K1 driven by a main power supply system VDD1 and a power supply system VDD2 different from the main power supply system VDD1 are shown. , Driven every VDD3
And a method of arranging and wiring the semiconductor integrated circuit including the circuits K2 and K3 of the first embodiment, wherein the second circuits K2 and K3 driven for each of the power supply systems VDD2 and VDD3 different from the main power supply system VDD1 are provided on the floor plan. Each power supply system VDD
2, a first step A1 for designating each of the grouped placement areas 2 and 4 and a second circuit K2 specified in the first step A1 as well as a grouping for each VDD3. A second step A2 of automatically arranging in the wiring area, and the second step A2
A third step A3 in which the power supply wiring of the second circuit K2 arranged in the step S3 is performed, and an arrangement prohibition area 8 in which the arrangement of the subsequent circuits K3 and K1 is inhibited within a predetermined range including the arrangement area 2. A fourth step A4 for generating a power supply, a fifth step A6 for performing power supply wiring of a first circuit K1 driven by the main power supply system VDD1, and a fourth step A6 for automatically arranging the first circuit K1. 6 and a seventh step A8 of automatically routing wiring of all circuits except for the power supply wiring, and a method of placing and wiring a semiconductor integrated circuit is shown. Are power supply systems VDD2, VDD outside the set placement prohibited area 8.
3 shows a method of arranging and wiring a semiconductor integrated circuit that is repeatedly executed every three steps.

Next, the present invention will be specifically described with reference to FIGS. Referring to FIG. 1, this specific example has VDD1 as a main power supply system, VDD2 and VDD3 as separate power supply systems, and an arrangement area 1 of a circuit K1 for VDD1.
A power supply block 3 for VDD2, a power supply block 3 for VDD3, a power supply block 5 for VDD3, a main buffer 11-1, and a main buffer 11-1. And a prebuffer 11-2 attached to the buffer. The main buffer 11-1 and the pre-buffer 11-2 may be physically integrated. Reference numerals 12 and 13 denote a part of an area grouped with respect to VDD1 and subdivide the arrangement area 1.

Referring to FIGS. 2A and 2B, which are enlarged views of FIG. 1, this embodiment also includes a power supply wiring 6 for VDD
A power supply wiring 7 for DD2, an arrangement prohibited area 8 for a power supply system other than VDD2, a power supply wiring 9 for VDD3,
And an arrangement prohibited area 10 for a power supply system other than the DD3. Next, with reference to FIG. 3 and FIG. 4, information of instances driven by VDD2 and VDD3 applied to this specific example will be described. FIG. 3 is a hierarchical diagram of a circuit to which this specific example is applied. H1, H2, H3, and H4 are instance names of hierarchical macros, and U1, U2, and U3 are instance names of primitive cells. H1, H2 and U1 are V
When driven by DD2 and H4, U2 and U3 are driven by VDD3, the information shown in FIG. 4 is created. The main power supply system VDD1 is not included in this information. Here, when an instance name of a hierarchical macro is specified, it is assumed that a constituent element of a lower hierarchical level is specified. Also, it is assumed that an instance whose hierarchy is relatively lower has a higher priority. That is, in the configuration of this specific example, U3 is a component of H2, but by specifying the instance name of U3, the power supply system of U3 is recognized as VDD3.

Next, with reference to FIG. 5, each step of the placement and routing will be described in detail. Floor plan process step A
In FIG. 1, by inputting the information A0 shown in FIG. 4, the group information of the instances driven by VDD2 and VDD3 is automatically created, and in the placement areas 2 and 4 of FIG. Perform grouping. For VDD1, grouping is performed as necessary. In this case, when areas 2 and 4 are specified, VD
The grouping of D1 may overlap with another power supply system like 12 and 13.

Next, step A2 of the automatic arrangement (1) process
, Only the instances belonging to VDD2 are automatically arranged in the arrangement area 2 based on the result of step A1. Subsequently, in step A3 of the power supply wiring (1) process, V
The power supply wiring 7 of VDD2 is automatically provided so as to surround the arrangement region 2 from the power supply block 3 for DD2. Further, in step A4, which is a step of generating the placement prohibited area 8,
An arrangement prohibited area 8 having a predetermined size is generated outside the arrangement area 2 and the power supply wiring 7. Here, the predetermined size is
In a later step A6, the power supply wiring 6 of VDD1 has a size surrounding the power supply wiring 7.

In step A5, since the processing for VDD3 has not been completed, steps A2 to A4 are repeatedly executed in the same manner as in the case of VDD2, and the power supply wiring 9 for VDD3 and the layout prohibited area 10 are generated. Thereafter, step A5 is executed again, but the other power supply systems VDD2, V
Since the processing of steps A2 to A4 has been completed for DD3, step A, which is the step of power supply wiring (2), has been completed.
In step 6, the power supply wiring 6 for VDD1 is automatically performed. At this time, the power supply wiring 6 is wired so as to surround the power supply wirings 7 and 9 performed in step A3. This is to supply a stable power supply to the instance of the power supply system VDD1 arranged near the arrangement areas 2 and 4.

Subsequently, in step A7 of the automatic arrangement (2), an instance of the power supply system VDD1 is automatically arranged. Here, since the placement prohibited areas 8 and 10 already exist, even if the groupings 12 and 13 are performed on the instances of VDD1 in Step A2, the instances of VDD1 do not enter the areas of VDD2 and VDD3.

Thereafter, in the automatic wiring step A8, all signal wirings are automatically wired, and the operation proceeds to the next step. Next, another specific example of the present invention will be described in detail with reference to FIGS. 6 and FIG. 7 which is an enlarged view of FIG.
Referring to (A) and (B), this specific example is characterized in that the arrangement area of the VDD2 is subdivided into 2-1 and 2-2, and one or a plurality of main buffers 14-1 and their pre-buffers 14 −2 is driven by VDD3, which is different from the above specific example.

The placement areas 2-1 and 2-2 are determined in step A1.
At this stage, the group information is subdivided and grouped so as to be in the vicinity. In step A2, step A1
Performs automatic placement in which the area is subdivided based on the grouping information. The generation of the power supply wiring 7 in step A3, the generation of the placement prohibited area 8 in step A4, and the power supply wiring 6 in step A6 are performed on an area including the placement areas 2-1 and 2-2.

This subdivision makes it possible to arrange the instances of different power supply systems in consideration of the timing. Next, a case where the buffer is driven by VDD3 will be described with reference to FIG. Main buffer 14
-1 has been arranged according to a predetermined terminal arrangement in step A1. The power of the main buffer 14-1 is supplied from the power supply block 5, and is separated from the main buffer 11-1 of VDD1 by the separation block 15. The pre-buffer 14-2 specifies the instance of the power supply system VDD3 in the information A0, and performs automatic arrangement collectively with other instances of VDD3 in step A2. The generation of the power supply wiring 9 in step A3 and the generation of the placement prohibition area 10 in step A4 are based on the
This is performed for the area including the arrangement area of 4-2. Further, since the placement prohibited area 10 covers the boundary of the placement area 1 of the internal instance, the power supply wiring 6 in step A6
Is performed in such a way as to bypass the inside along the arrangement prohibited area 10.

As a result, stable power supply can be achieved while suppressing the routing of redundant power supply wiring. The above-described automatic placement and routing is a first method of grouping, for example, in a firmware provided on a computer, a circuit driven for each power supply system different from a main power supply system for each power supply system in a floor plan. Means, second means for automatically arranging the grouped circuits designated in the first step in a predetermined arrangement area, and third means for power supply wiring of the circuits arranged in the second step Means,
Fourth means for generating a predetermined area including the arrangement area as an arrangement prohibition area for prohibiting arrangement of subsequent circuits, and fifth means for performing power supply wiring of a circuit driven by the main power supply system And a sixth means for automatically arranging circuits to which power supply wiring is applied by the fifth means, and a seventh means for automatically wiring wiring of all circuits except the power supply wiring. I can do it.

Also, in the floor plan, a first step of grouping circuits driven for each power supply system different from the main power supply system for each power supply system, and a grouping designated in the first step A second step of automatically arranging the arranged circuit in a predetermined arrangement area, a third step of wiring a power supply of the circuit arranged in the second step, and Generated as an arrangement prohibited area for prohibiting the arrangement of the circuit of FIG.
A fifth step of performing power supply wiring of a circuit driven by the main power supply system, a sixth step of automatically arranging a circuit with the power supply wiring provided by the fifth means, The present invention may be realized as a recording medium for causing a computer to execute a series of processes including a seventh step of automatically wiring the wiring of all circuits except the wiring.

Of course, the second to fourth steps are configured to be repeatedly executed for each power supply system.

[0025]

Since the present invention is configured as described above, it is possible to overlap the groupings of different power supply systems, so that the degree of freedom of the floor plan is increased and the dead space can be reduced. Therefore, the degree of integration is improved. In addition, since the separation of the power supply wiring as well as the arrangement is performed automatically, it is possible to reduce the number of manual correction operations. Therefore, the TAT is shortened, and work errors such as a short-circuit of the power supply are reduced.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining an arrangement state of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a partially enlarged view of FIG.

FIG. 3 is a diagram showing an example of a hierarchical diagram for implementing the present invention.

FIG. 4 is a diagram showing an example in which instructions for grouping by power supply system are described.

FIG. 5 is a flowchart of the present invention.

FIG. 6 is a plan view for explaining another specific example of the semiconductor integrated circuit according to the present invention.

FIG. 7 is a partially enlarged view of FIG. 6;

FIG. 8 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Internal instance area arrangement area 2 VDD2 arrangement area 3, 5 Power supply block 4 VDD3 arrangement area 6 VDD1 power supply wiring 7 VDD2 power supply wiring 9 VDD3 power supply wiring 8, 10 wiring prohibited area 11-1, 14-1 Main buffer 11-2, 14-2 Prebuffer 15 Separation block VDD1 Main power supply system VDD2, VDD3 Other power supply system K1 to K3 circuits

Claims (7)

[Claims] 1. A method of arranging and wiring a semiconductor integrated circuit including a first circuit driven by a main power supply system and a second circuit driven for each power supply system different from the main power supply system. In the floor plan, a first step of grouping the second circuits driven for each power supply system different from a main power supply system for each power supply system, and specifying in the first step A second step of automatically arranging the grouped second circuits in a predetermined arrangement area, a third step of performing power supply wiring of the second circuit arranged in the second step, and the arrangement. A fourth step of generating a predetermined range including the area as an arrangement prohibited area for prohibiting the arrangement of subsequent circuits, and a fifth step of performing power supply wiring of a first circuit driven by the main power supply system Steps; A sixth step of automatically arranging the first circuit; and a seventh step of automatically arranging all the wiring except for the power supply wiring. 2. The method according to claim 1, wherein the second to fourth steps are repeatedly performed for each power supply system in a region outside the set placement prohibition region. . 3. The method according to claim 1, wherein the placement area first overlaps a placement area of a different power supply system. 4. An automatic placement and routing method for a semiconductor integrated circuit including a first circuit driven by a main power supply system and a second circuit driven for each power supply system different from the main power supply system. An apparatus, wherein in a floor plan, first means for grouping, for each power supply system, the second circuit driven for each power supply system different from the main power supply system; A second means for automatically arranging the designated grouped second circuits in a predetermined arrangement area; a third means for power supply wiring of the second circuits arranged in the second step; Fourth means for generating a predetermined area including the arrangement area as an arrangement prohibition area for prohibiting arrangement of subsequent circuits, and a fifth means for performing power supply wiring of a first circuit driven by the main power supply system Means, and automatic operation of the first circuit A placement and routing apparatus for a semiconductor integrated circuit, comprising: a sixth means for performing placement; and a seventh means for automatically routing all wiring except for the power supply wiring. 5. The semiconductor integrated circuit according to claim 4, wherein the placement and routing performed by the second to fourth means are repeatedly performed for each power supply system in a region outside the set placement prohibited region. Circuit placement and wiring equipment. 6. A method of arranging and wiring a semiconductor integrated circuit including a first circuit driven by a main power supply system and a second circuit driven for each power supply system different from the main power supply system. A first step of grouping the second circuits driven for each power supply system different from the main power supply system for each power supply system in a floor plan; and A second step of automatically arranging the grouped second circuits specified in the first step in a predetermined arrangement area; and performing power supply wiring of the second circuits arranged in the second step. A third step, a fourth step of generating a predetermined range including the layout area as a layout prohibited area for prohibiting the subsequent circuit layout, and a first step driven by the main power supply system. A fifth step of performing power supply wiring on a road, a sixth step of automatically arranging the first circuit, and a seventh step of automatically wiring all wiring except the power supply wiring. A program for causing a computer to execute the processing of (1). 7. The recording medium according to claim 6, wherein the second to fourth steps are repeatedly performed for each power supply system in an area outside the set placement prohibited area.