JPH11289247A - Potential conversion circuit - Google Patents

Potential conversion circuit

Info

Publication number
JPH11289247A
JPH11289247A JP10088523A JP8852398A JPH11289247A JP H11289247 A JPH11289247 A JP H11289247A JP 10088523 A JP10088523 A JP 10088523A JP 8852398 A JP8852398 A JP 8852398A JP H11289247 A JPH11289247 A JP H11289247A
Authority
JP
Japan
Prior art keywords
potential
circuit
signal processing
power supply
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10088523A
Other languages
Japanese (ja)
Inventor
Takaaki Nozaki
孝明 野崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP10088523A priority Critical patent/JPH11289247A/en
Publication of JPH11289247A publication Critical patent/JPH11289247A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a potential conversion circuit for controlling a signal processing circuit to be driven by an oscillator power supply by a logical signal outputted from a signal processing circuit to be driven by a fixed potential power supply. SOLUTION: The potential conversion circuit is provided with a 1st potential comparator 1 to be driven by an oscillation power supply a 2nd potential comparator 2 and an order discriminating circuit 3 for receiving outputs from the 1st and 2nd potential comparators 1, 2 and processing timewise order information when the logical states of outputs from the two potential comparators 1, 2 are transited and constituted so that a 1st logical information signal inputted to the 2nd signal processing circuit is applied to the comparator 1, a 2nd logical information signal is applied to the comparator 2, a result obtained by processing the output change information of the comparators 1, 2 by the circuit 3 is outputted as a logical output 10, and the logical output 10 is controlled by the logical information of the 2nd signal processing circuit.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は接地に対し電位が揺
動する揺動電源で動作する揺動電源動作の信号処理回路
と、該揺動電源に対接地電位がより緩やかな変化あるい
は定常的電位で動作する信号処理回路の間で論理信号を
交換するための電位変換回路、あるいはレベルシフタ回
路の構成および使用法で、特に時分割マトリックス表示
を行う液晶表示装置の走査線ドライバーを制御する論理
信号の伝播方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for oscillating power supply operation which operates with an oscillating power supply whose electric potential oscillates with respect to the ground, and that the oscillating power supply has a more gradual or steady change in ground potential. A logic signal for controlling a scanning line driver of a liquid crystal display device which performs a time-division matrix display, particularly in a configuration and usage of a potential conversion circuit or a level shifter circuit for exchanging a logic signal between signal processing circuits operating with a potential. The propagation method.

【0002】[0002]

【従来の技術】従来、表示素子やアクチュエータ素子の
駆動においては50Vから150Vといった高駆動電圧
が要求され、駆動回路の集積回路化に難があったりチッ
プ面積の増加によるコスト増加を招いていたりしてい
た。しかし揺動電源駆動方式を採用することで半導体集
積回路の動作電圧を半分程度に低下させる技術が開発さ
れ集積回路化が容易になり、コストも低下した。ここで
揺動電源を使った駆動回路を制御するための制御信号
は、低電圧の論理回路で作成した制御信号を用いるのが
使いやすさの点から望まれる。ここで、低電圧の制御信
号で揺動電源を用いた信号処理回路を制御するために
は、揺動電源に対応した電位変換回路を使う必要があ
る。始めに揺動電源の説明を行い、次に電位変換回路の
従来例をしめす。
2. Description of the Related Art Hitherto, a high driving voltage of 50 V to 150 V has been required for driving a display element or an actuator element, which makes it difficult to integrate a driving circuit into an integrated circuit or increases the cost due to an increase in chip area. I was However, by employing the swing power supply driving method, a technology for reducing the operating voltage of the semiconductor integrated circuit to about half has been developed, and the integration into an integrated circuit has been facilitated, and the cost has been reduced. Here, it is desirable to use a control signal generated by a low-voltage logic circuit as a control signal for controlling the drive circuit using the oscillating power supply from the viewpoint of ease of use. Here, in order to control a signal processing circuit using an oscillating power supply with a low-voltage control signal, it is necessary to use a potential conversion circuit corresponding to the oscillating power supply. First, a swing power supply will be described, and then a conventional example of a potential conversion circuit will be described.

【0003】図6は時分割数nのマトリックス表示を行
う液晶表示装置の走査線ドライバーのタイミング図を示
す。走査線ドライバーは行走査クロックLP(Line
Pulse)と先頭走査線を示す制御信号FLM(F
irst Line Marker)とを与えると、n行
分の走査線出力S1〜Snに順次走査信号が出力され
る。出力される走査信号のパルス極性は、液晶素子への
直流電流成分印可による分極を防ぐために行ごとに反転
させる交流化駆動が一般的である。ここで正パルスの電
位をV1、負パルスの電位をV4、比選択時の走査線電
位をVMとする。奇数走査線が選択される時は必ず正パ
ルスが出力され、偶数走査線が選択される場合には負パ
ルスV4が出力される。640分割程度の液晶表示装置
の場合、V1〜V4間は50V程度、VMは中間の25
V程度に設定するのが普通であるから、走査線ドライバ
ーが取り扱う最大電圧は50Vとかなり高い耐圧が必要
となる。しかし奇数走査線が選択されている期間をよく
見ると全走査線出力の最高電位はV1であり最低電位は
VMでる。一方偶数走査線が選択されている期間につい
ても最高電位はVM、最低電位はV4である。したがっ
て、駆動回路自体が真に必要とする耐圧はV1〜VM間
電位、あるいはVM〜V4間電位で動作可能であること
がわかる。そこで、接地電位に対して矩形あるいは台形
状に揺動する電源VDDとVSSを用いる。揺動電源V
DDは走査線出力に正パルスが必要な期間では揺動電源
を高電位側に揺動させてV1に一致さる。一方負パルス
が必要な期間では揺動電源を低電位側に揺動させてV4
に一致させる。この時、VDD〜VSS間電位は常に一
定電位を保ち、かつ行ドライバを制御する論理信号の高
電位レベルをV2、定電位レベルをV3として、高電位
側に揺動した場合のVSSをV3に、低電位側に揺動し
た場合のVDDをV2に一致させる。このような揺動電
源VDDとVSSを用意しておき、走査線ドライバーは
この揺動電源VDD、VSSを電源として動作させる。
すなわち、正パルスが必要な奇数走査線選択期間では走
査線出力にVDDを出力し、負パルスが必要な偶数走査
線選択期間では走査線出力にVSSを、その他の非選択
期間にはVMを出力するように走査線ドライバーを構成
することにより、走査線ドライバー自体はV1〜V3あ
るいはV2〜V4の電位を扱い、走査線出力にはV1〜
V4の電位を供給することが可能となる。このように揺
動電源を用いることで駆動回路に必要な耐圧をおよそ半
分程度に低減することが可能である。
FIG. 6 is a timing chart of a scanning line driver of a liquid crystal display device for performing a matrix display of a time division number n. The scanning line driver uses a row scanning clock LP (Line
Pulse) and a control signal FLM (F
(first line marker), the scanning signals are sequentially output to the scanning line outputs S1 to Sn for n rows. In general, an alternating drive in which the pulse polarity of the output scanning signal is inverted for each row in order to prevent polarization due to application of a direct current component to the liquid crystal element. Here, the potential of the positive pulse is V1, the potential of the negative pulse is V4, and the scanning line potential at the time of selecting the ratio is VM. A positive pulse is always output when an odd scan line is selected, and a negative pulse V4 is output when an even scan line is selected. In the case of a liquid crystal display device of about 640 divisions, about 50 V is applied between V1 and V4, and VM is 25
Since the voltage is normally set to about V, the maximum voltage handled by the scanning line driver is required to be as high as 50 V, which is a considerably high withstand voltage. However, looking closely at the period in which the odd-numbered scanning lines are selected, the highest potential of all the scanning line outputs is V1 and the lowest potential is VM. On the other hand, the maximum potential is VM and the minimum potential is V4 also during the period in which the even-numbered scanning line is selected. Therefore, it can be seen that the withstand voltage that the drive circuit itself really needs can operate at a potential between V1 and VM or a potential between VM and V4. Therefore, power supplies VDD and VSS that swing in a rectangular or trapezoidal shape with respect to the ground potential are used. Oscillating power supply V
In the period in which a positive pulse is required for the scanning line output, DD swings the swing power supply to the high potential side and becomes equal to V1. On the other hand, during the period in which a negative pulse is required, the swing power supply is swung to the lower potential side and V4
To match. At this time, the potential between VDD and VSS is always kept constant, and the high potential level of the logic signal for controlling the row driver is V2, the constant potential level is V3, and the VSS when swinging to the high potential side is V3. , VDD when swinging to the lower potential side is made equal to V2. Such oscillation power supplies VDD and VSS are prepared, and the scanning line driver operates using the oscillation power supplies VDD and VSS as power supplies.
That is, VDD is output to the scanning line output during the odd scanning line selection period requiring a positive pulse, VSS is output to the scanning line output during the even scanning line selection period requiring a negative pulse, and VM is output during the other non-selection periods. The scanning line driver itself handles the potentials of V1 to V3 or V2 to V4, and the scanning line driver outputs V1 to V1.
V4 potential can be supplied. By using such a swing power supply, the withstand voltage required for the drive circuit can be reduced to about half.

【0004】図7は揺動電源対応の電位変換回路に要求
される電位関係を示している。ラインパルスLPとファ
ーストラインマーカーは外部より走査線ドライバーを制
御するための制御信号で論理レベルは高電位側V2、低
電位側V3の電位を持つ。これらに対し、揺動電源VD
D、VSSで動作する走査線ドライバー内部においては
LPはLP’に、FLMはFLM’に変換する必要があ
る。揺動電源が高電位側に揺動した期間では、制御信号
の高電位側レベルV2をV1へ、逆に揺動電源が低電位
側に揺動した期間では、制御信号の低電位側レベルV3
をV4へと、揺動状態によって変換するレベルが変わっ
てくる必要がある。
FIG. 7 shows a potential relationship required for a potential conversion circuit corresponding to a swing power supply. The line pulse LP and the first line marker are control signals for externally controlling the scanning line driver, and have logical levels of a high potential side V2 and a low potential side V3. In contrast, the swing power supply VD
LP and LPM need to be converted to LP 'and FLM', respectively, inside the scanning line driver operating at D and VSS. During the period when the swing power supply swings to the high potential side, the high potential side level V2 of the control signal is changed to V1. Conversely, during the period when the swing power supply swings to the low potential side, the low potential side level V3 of the control signal is changed.
Needs to be changed to V4 depending on the swing state.

【0005】[0005]

【発明が解決しようとする課題】揺動電源動作の論理回
路に制御信号を入力するために、揺動電源動作の接地レ
ベルから見た論理回路の最高電位と同最低電位からなる
大振幅信号を、揺動電源回路の外部の固定電源回路で作
成し、揺動源現回路の入力端子に接続する方法が技術的
に可能である。しかし、通常のICの構造では該外部レ
ベル変換回路の出力信号電位が揺動電源動作の集積回路
の電源電位の間になければ揺動電源動作ICの保護回路
が起動し、消費電流増の問題を生じる。保護回路電流増
問題に対処して保護回路での電流増加を防いだ場合にお
いても、揺動電源の最高電亥から最低電亥までの論理振
幅を出力する高電圧電源と高電圧動作論理振幅増幅回路
が必要になり、これは回路の消費電力増加と回路コスト
増加をもたらす。また、揺動電位がパルス状あるいは台
形状に変化する場合は、論理値電位が変化しない高電位
位相あるいは低電位位相で定電位電源動作の論理電位の
レベル変換回路を形成する手法が利用できるが、揺動電
位が変動している途中の位相において固定電位系の論理
レベルから変動電位系の論理レベルへの情報伝達あるい
は逆方向への雑音発生のない伝達の簡潔な回路の構成は
容易でない。
In order to input a control signal to the logic circuit of the swing power supply operation, a large amplitude signal having the same maximum potential and the lowest potential of the logic circuit as viewed from the ground level of the swing power supply operation is used. It is technically possible to create a fixed power supply circuit outside the swing power supply circuit and connect it to the input terminal of the swing power supply current circuit. However, in the structure of a normal IC, if the output signal potential of the external level conversion circuit is not between the power supply potentials of the integrated circuit of the swing power supply operation, the protection circuit of the swing power supply operation IC is activated, and the current consumption increases. Is generated. High voltage power supply and high voltage operation logic amplitude amplification that output the logic amplitude from the highest power supply to the lowest power supply of the oscillating power supply even if the current increase in the protection circuit is prevented by addressing the protection circuit current increase problem Circuits are required, which results in increased power consumption and increased circuit costs. When the oscillating potential changes in a pulsed or trapezoidal shape, a method of forming a logic potential level conversion circuit of a constant potential power supply operation at a high potential phase or a low potential phase where the logic value potential does not change can be used. However, it is not easy to configure a simple circuit for transmitting information from the logic level of the fixed potential system to the logic level of the fluctuating potential system or transmitting without noise in the reverse direction during the phase in which the oscillating potential is fluctuating.

【0006】[0006]

【課題を解決するための手段】上記の目的を達成する
為、本発明の電位変換回路は一定電位差を保ちつつ対接
地電位が揺動する揺動電源回路と対接地電位が一定の定
電位電源回路とを共に備えた複電源動作の第一の信号処
理回路と、対接地電位が一定の定電位電源で動作の第二
の信号処理回路とを備え、該第二の信号処理回路は定電
位電源と接地電位からなる第一の論理情報を該第一の信
号処理回路に論理情報を伝達し、該第一の複電源構造の
信号処理回路には揺動電源で動作する第一の電位比較回
路と、第二の電位比較回路と、該第一の電位比較回路の
出力と該第二の電位比較回路の出力を入力し2つの電位
比較回路の出力がある論理状態から反転した論理状態に
遷移するときの時間的順序を検知する順序弁別回路とを
備え、該第二の信号処理回路に入力された論理情報信号
を該第一電位比較回路に与え、該論理情報信号とは逆極
性の論理情報信号を該第二の電位比較回路に与え、揺動
電源が揺動した時の電位比較回路出力変化の順序を該順
序弁別回路が検知した結果を論理出力とし、揺動電源が
揺動した時点で第二の信号処理回路の論理信号により該
論理出力を制御する構造を備えたことを特徴とする。
In order to achieve the above object, a potential conversion circuit according to the present invention comprises an oscillating power supply circuit in which a ground potential is oscillated while maintaining a constant potential difference, and a constant potential power supply in which a ground potential is constant. And a second signal processing circuit operating with a constant potential power supply having a constant ground potential. The second signal processing circuit has a constant potential The first logic information including a power supply and a ground potential is transmitted to the first signal processing circuit, and the first signal processing circuit having a dual power supply structure is provided with a first potential comparison circuit operated by an oscillating power supply. A circuit, a second potential comparator, an output of the first potential comparator and an output of the second potential comparator, and the outputs of the two potential comparators change from a logic state to a logic state inverted from a certain logic state A sequence discriminating circuit for detecting a temporal sequence at the time of transition, and the second signal When a logic information signal input to the logic circuit is applied to the first potential comparison circuit, a logic information signal having a polarity opposite to that of the logic information signal is applied to the second potential comparison circuit, and when the swing power supply swings, A logic output based on the result of detection by the order discrimination circuit of the order of the potential change of the potential comparison circuit, and controlling the logic output by a logic signal of the second signal processing circuit when the swing power supply swings. It is characterized by having.

【0007】また、本発明の電位変換回路は一定電位差
を保ちつつ対接地電位が揺動する揺動電源回路と対接地
電位が一定の定電位電源回路とを共に備えた複電源動作
の第一の信号処理回路と、対接地電位が一定の定電位電
源で動作の第二の信号処理回路とを備え、該第二の信号
処理回路は定電位電源と接地電位からなる第一の論理情
報を該第一の信号処理回路に論理情報を伝達し、該第一
の複電源構造の信号処理回路には揺動電源動作の第一の
電位比較回路と、第二の電位比較回路と、該第一の電位
比較回路の出力と該第二の電位比較回路の出力を入力
し、2つの電位比較回路の出力がある論理状態から反転
した論理状態に遷移するときの時間的順序を検知する順
序弁別回路とを備え、該第二の信号処理回路に入力され
た論理情報信号を該第一電位比較回路に与え、該論理情
報信号とは逆極性の論理情報信号を該第二の電位比較回
路に与え、該第一および該第二の電位比較回路には閾値
を有するインバータ回路を用い、揺動電源が揺動した時
の電位比較回路出力変化の順序を該順序弁別回路が検知
した結果を論理出力とし、揺動電源が揺動した時点で第
二の信号処理回路の論理信号により該論理出力を制御す
る構造を備えたことを特徴とする。
Further, the potential conversion circuit of the present invention is the first of a double power supply operation having both an oscillating power supply circuit in which a ground potential oscillates while maintaining a constant potential difference and a constant potential power supply circuit having a constant ground potential. A signal processing circuit, and a second signal processing circuit that operates with a constant potential power supply having a constant ground potential, the second signal processing circuit stores first logic information including a constant potential power supply and a ground potential. Logic information is transmitted to the first signal processing circuit, and the signal processing circuit having the first multiple power supply structure includes a first potential comparison circuit for oscillating power supply operation, a second potential comparison circuit, Sequence discrimination for receiving the output of one potential comparison circuit and the output of the second potential comparison circuit, and detecting the temporal sequence when the outputs of the two potential comparison circuits transition from one logic state to an inverted logic state And a logic information signal input to the second signal processing circuit. The first potential comparison circuit is provided with a logic information signal having a polarity opposite to that of the logic information signal to the second potential comparison circuit, and an inverter circuit having a threshold is used for the first and second potential comparison circuits. The result of the sequence discrimination circuit detecting the order of the output change of the potential comparison circuit when the oscillating power supply oscillates is used as a logical output, and when the oscillating power supply oscillates, the logic signal of the second signal processing circuit is used. A structure for controlling the logical output is provided.

【0008】また、本発明の電位変換回路は該第一の信
号処理回路を同一半導体集積回路チップ上に形成し、外
部に設けた該第二の信号処理回路からの情報を入力して
揺動電源電位からなる論理情報に電位変換し、該第一の
信号処理回路を制御することを特徴とする。
Further, in the potential conversion circuit according to the present invention, the first signal processing circuit is formed on the same semiconductor integrated circuit chip, and information is input from the externally provided second signal processing circuit to oscillate. It is characterized in that the potential is converted into logic information composed of a power supply potential and the first signal processing circuit is controlled.

【0009】接地電位を基準に考え、揺動電源が高電位
側に揺動した時の電位比較回路の比較電位を入力する論
理信号の高電位レベルより高く設定し、逆に揺動電源が
低電位側に揺動した時の電位比較回路の比較電位を入力
する論理信号の低電位レベルより低く設定してけば、揺
動電源が高電位側あるいは低電位側に揺動する時には入
力する論理信号の電位は必ず比較電位を横切ることにな
る。揺動電源が高電位側から低電位側に揺動するとき
は、入力信号の論理値が高電位レベルにある方の電位比
較回路が先に比較電位を横切り、低電位レベルにある方
がが後に比較電位を横切ることになる。逆に揺動電源が
低電位側から高電位側に揺動するときは、入力信号の論
理値が低電位レベルにある方の電位比較回路が先に比較
電位を横切り、高電位レベルにある方がが後に比較電位
を横切ることになる。したがって、比較電位を横切る順
序を検知することで揺動電源の揺動時の入力信号の論理
値を知ることが可能である。また、インバータ回路は一
般に動作電源の電圧範囲内に閾値を有し、入力信号が閾
値より高いか低いかで論理信号を出力するため、電位比
較回路の代わりにインバータ回路を使用することが可能
である。
Considering the ground potential, the comparison potential of the potential comparator when the swing power supply swings to the higher potential side is set higher than the high potential level of the input logic signal, and conversely, the swing power supply becomes lower. If the comparison potential of the potential comparison circuit when swinging to the potential side is set lower than the low potential level of the input logic signal, the logic signal to be input when the swing power supply swings to the high potential side or low potential side Always cross the comparison potential. When the oscillating power supply oscillates from the high potential side to the low potential side, the potential comparison circuit in which the logic value of the input signal is at the high potential level crosses the comparison potential first, and the one at the low potential level Later it will cross the comparison potential. Conversely, when the swing power supply swings from the low potential side to the high potential side, the potential comparison circuit in which the logical value of the input signal is at the low potential level crosses the comparison potential first, and Will later cross the comparison potential. Therefore, it is possible to know the logical value of the input signal when the swing power supply swings by detecting the order of crossing the comparison potential. In addition, since an inverter circuit generally has a threshold value within the voltage range of the operating power supply and outputs a logic signal depending on whether an input signal is higher or lower than the threshold value, an inverter circuit can be used instead of the potential comparison circuit. is there.

【0010】[0010]

【発明の実施の形態】図1に本発明の電位変換回路の実
施例をしめす。本電位変換回路は2つの電位比較回路
1、2と順序弁別回路3とから構成されている。入力す
る論理信号は高電位レベルと低電位レベルの2状態を論
理値とする入力信号4とその反転論理の入力信号7を用
いる。電位比較回路1は非反転の入力信号4と比較電位
5とを比較し比較信号6を出力する。電位比較回路2は
反転入力信号7と比較電位8とを比較し比較信号9を出
力する。順序弁別回路3は比較信号6、9を入力し、そ
の論理状態が電源揺動時に変化する順序情報を処理して
論理出力信号10を出力する。電位変換回路1、2と順
序弁別回路3と比較電位発生器11、12は共に揺動電
源で動作する。揺動電源は対接地電位が揺動するが、揺
動電源で動作する回路から見れば電源電位は一定であ
る。逆に、揺動電源で動作している回路の一定電位は対
接地電位で見ると揺動電源といっしょに揺動することに
なる。ここで、比較電位5と8は対接地電位で見て、揺
動電源が高電位側に揺動した時の入力論理信号の高電位
レベルより高く、かつ、揺動電源が低電位側に揺動した
時の入力論理信号の低電位レベルより低く設定されてい
る。ここで、電位比較回路としては差動増幅器から構成
される電圧コンパレータを用いることが出来る。また、
閾値を有するインバータ回路、たとえば相補型の電界効
果トランジスタ対を用いたインバータ回路を用いれば、
その閾値を比較電位とする電位比較回路としても使用可
能である。この場合、トランジスタ対のオン抵抗を調整
することにより比較電位を動作電源の電圧範囲内におい
て調整することが可能である。
FIG. 1 shows an embodiment of a potential conversion circuit according to the present invention. This potential conversion circuit comprises two potential comparison circuits 1 and 2 and a sequence discrimination circuit 3. As an input logic signal, an input signal 4 having a logic value of two states of a high potential level and a low potential level and an input signal 7 of an inverted logic thereof are used. The potential comparison circuit 1 compares the non-inverted input signal 4 with the comparison potential 5 and outputs a comparison signal 6. The potential comparison circuit 2 compares the inverted input signal 7 with the comparison potential 8 and outputs a comparison signal 9. The sequence discriminating circuit 3 receives the comparison signals 6 and 9, processes the sequence information whose logic state changes when the power supply fluctuates, and outputs a logic output signal 10. The potential conversion circuits 1 and 2, the sequence discrimination circuit 3, and the comparison potential generators 11 and 12 all operate on a swing power supply. The oscillating power supply oscillates with respect to the ground potential, but the power supply potential is constant from the viewpoint of a circuit operating with the oscillating power supply. Conversely, the constant potential of the circuit operating with the oscillating power supply will oscillate together with the oscillating power supply when viewed from the ground potential. Here, the comparison potentials 5 and 8 are higher than the high potential level of the input logic signal when the oscillating power supply oscillates to the high potential side and the oscillating power supply oscillates to the low potential side when viewed from the ground potential. It is set lower than the low potential level of the input logic signal when it operates. Here, a voltage comparator including a differential amplifier can be used as the potential comparison circuit. Also,
If an inverter circuit having a threshold value, for example, an inverter circuit using a complementary field effect transistor pair is used,
It can also be used as a potential comparison circuit that uses the threshold as a comparison potential. In this case, the comparison potential can be adjusted within the voltage range of the operation power supply by adjusting the on-resistance of the transistor pair.

【0011】図3は本電位変換回路の動作をしめすタイ
ミング図である。揺動電源は対接地電位が揺動するが、
揺動電源のVDD、VSSは高電位揺動時にそれぞれ電
位V1、V3、低電位揺動時にV2、V4となる。V1
〜V3間電位とV2〜V4間電位は常に一定に保たれて
いる。ここで、タイミング図は接地を基準に描いてあ
る。電位変換回路に入力する論理信号の高電位レベルは
V2、低電位レベルはV3に一致している。非反転の入
力信号4は初め高電位レベルにあり、したがって反転入
力信号7は低電位レベルにある。比較電位5、8は揺動
電源が高電位揺動時には電位V2より高電位に、低電位
揺動時には電位V3より高電位に選ばれているが、揺動
電源内から見れば一定である。すなわち、揺動電源VS
Sから比較電位5、8間の電位差は一定である。ここで
比較電位5、8は前記条件を満足すれば揺動電源の位相
によって変化させても構わない。また、入力論理信号の
レベルと揺動電源のレベルをV2、V3で一致させてい
るが、比較電位が前記条件を満足すれば異なる電位をも
ちいてもよい。また、比較電位5と8も同一電位を用い
ているが同様に前記条件を満足されば異なる電位を用い
てもよい。
FIG. 3 is a timing chart showing the operation of the present potential conversion circuit. The swing power supply fluctuates with respect to ground potential,
VDD and VSS of the swing power supply become the potentials V1 and V3 when the high potential swings, and V2 and V4 when the low potential swings. V1
The potential between V3 and V2 and the potential between V2 and V4 are always kept constant. Here, the timing diagram is drawn based on the ground. The high potential level of the logic signal input to the potential conversion circuit matches V2, and the low potential level matches V3. The non-inverted input signal 4 is initially at a high potential level, and thus the inverted input signal 7 is at a low potential level. The comparison potentials 5 and 8 are selected to be higher than the potential V2 when the swing power source swings at a high potential and higher than the potential V3 when the swing power source swings, but are constant when viewed from inside the swing power source. That is, the swing power supply VS
The potential difference between S and the comparison potentials 5 and 8 is constant. Here, the comparison potentials 5 and 8 may be changed according to the phase of the oscillating power supply if the above conditions are satisfied. Although the level of the input logic signal and the level of the oscillating power supply are matched at V2 and V3, different potentials may be used as long as the comparison potential satisfies the above condition. Although the same potential is used for the comparison potentials 5 and 8, different potentials may be used as long as the above conditions are satisfied.

【0012】以上のような揺動電源、入力信号、および
比較電源のもとでの電位変換回路の動作を次に説明す
る。電位比較回路は入力信号が比較電位より高い場合に
低電位レベルLを、低い場合には高電位レベルHを出力
するものとする。ここでの論理レベルは揺動電源内で動
作する論理レベルで入力信号の論理レベルのことではな
い。初め時間T0で非反転信号は高電位レベルで揺動電
源は高電位側に揺動している。この時、電位比較回路1
の比較出力6はLレベルを出力する。時間T1で揺動電
源が低電位側に揺動する時、入力信号は比較電位を横切
るので比較出力6はHレベルに遷移し、時間T4で揺動
電源が高電位側に戻るときに再び比較電位を横切り比較
出力はLレベルに戻る。このように、比較出力6は揺動
と同期してその出力が変化する。次に反転信号側につい
て見ると、初め時間T0では低電位レベルにあるので電
位比較回路2の比較出力9は時間T2では前者に比べて
やや遅れてHレベルに遷移し、逆に時間T5ではやや早
めにLレベルに戻る。次に、時間T3で入力信号がそれ
ぞれ反転するので時間T4では非反転入力側の比較出力
6は反転側の比較出力9に比べてやや遅めにHレベルに
遷移し、時間T5では早めにLレベルに遷移する。つま
り、揺動電源が低電位側に揺動するときは、比較出力が
先に遷移した方の入力が高電位レベルにあり、逆に高電
位側に揺動するときは、先に遷移した方の入力が低電位
レベルにあることが検知されるのでこれを次に説明する
順序弁別回路3により弁別し論理出力10を得る。ここ
で比較出力は入力信号が比較電位より高い場合にLレベ
ル、低い場合にHレベルを用いたが、ここで重要なのは
レベルのH、Lではなく論理値の状態が遷移する順序で
あるので、正論理、負論理のどちらを用いてもよい。
The operation of the potential conversion circuit under the above-described swing power supply, input signal, and comparison power supply will now be described. The potential comparison circuit outputs a low potential level L when the input signal is higher than the comparison potential, and outputs a high potential level H when the input signal is low. The logic level here is a logic level operating in the swing power supply, not a logic level of the input signal. First, at time T0, the non-inverted signal is at the high potential level and the swing power supply swings to the high potential side. At this time, the potential comparison circuit 1
Outputs the L level. When the oscillating power supply oscillates to the lower potential side at time T1, the input signal crosses the comparison potential, so that the comparison output 6 transitions to the H level. At time T4, the comparison is made again when the oscillating power supply returns to the higher potential side. The comparison output returns to the L level across the potential. Thus, the output of the comparison output 6 changes in synchronization with the swing. Next, looking at the inversion signal side, the comparison output 9 of the potential comparison circuit 2 transitions to the H level at time T0 slightly later than the former at time T2, and conversely at time T5 at time T0. Return to L level early. Next, since the input signals are inverted at time T3, the comparison output 6 on the non-inversion input side transitions to the H level slightly later than the comparison output 9 on the inversion side at time T4, and changes to L level earlier at time T5. Transition to a level. In other words, when the swing power supply swings to the lower potential side, the input to which the comparison output transitions first is at the high potential level, and when the swing power supply swings to the higher potential side, the input to which the comparison output transitions first is higher. Is detected at the low potential level, and this is discriminated by the sequence discriminating circuit 3 described below to obtain the logical output 10. Here, the comparison output uses the L level when the input signal is higher than the comparison potential, and uses the H level when the input signal is lower than the comparison potential. Either positive logic or negative logic may be used.

【0013】次に順序弁別回路の実施例を図3とタイミ
ング図2を使って説明する。順序弁別回路はNANDゲ
ートを用いたセット・リセット型フリップフロップ20
とそのセット入力22とリセット入力23を発生する組
み合わせ回路21から構成されている。組み合わせ回路
は非反転入力側の比較出力6と反転入力側の比較出力9
を入力しセット信号とリセット信号を生成する。比較出
力6と9が共にLまたはHレベルの場合セット信号、リ
セット信号は共にHレベルとなりフリップフロップは保
持状態にある。タイミング図2にセット入力22とリセ
ット入力23と順序弁別回路の出力10をしめす。初め
に時刻T1での動作をみる。両比較出力がLからスター
トして比較出力6が先にHに遷移するとセット入力22
がLになり、つづいて比較出力9がHに遷移してセット
入力がHに戻ってフリップフロップがセットされる。時
刻T4では逆の順序で比較出力が変化してリセット入力
に負パルスは生じリセットされる。結局、Lからスター
トする場合、つまり揺動電源が低電位側に揺動するとき
は先に変化した側の入力4が高電位レベルであったこと
が検知できる。両比較出力がHからスタートする時刻T
2とT5について考えると、揺動電源が高電位側に揺動
するときは先に変化した側の入力が低電位レベルであっ
たことが検知できる。以上の実施例ではNAND型のフ
リップフロップを用いたが、NOR型を用いてもよい。
Next, an embodiment of the sequential discrimination circuit will be described with reference to FIG. The sequence discriminating circuit is a set / reset type flip-flop 20 using a NAND gate.
And a combination circuit 21 for generating a set input 22 and a reset input 23 thereof. The combination circuit has a comparison output 6 on the non-inverting input side and a comparison output 9 on the inverting input side.
To generate a set signal and a reset signal. When both the comparison outputs 6 and 9 are at the L or H level, the set signal and the reset signal are both at the H level, and the flip-flop is in the holding state. FIG. 2 shows the set input 22, the reset input 23, and the output 10 of the sequence discriminating circuit. First, the operation at the time T1 will be described. When both comparison outputs start from L and the comparison output 6 transitions to H first, the set input 22
Becomes L, the comparison output 9 transits to H, the set input returns to H, and the flip-flop is set. At time T4, the comparison output changes in the reverse order, a negative pulse is generated at the reset input, and the reset input is reset. After all, when starting from L, that is, when the swing power supply swings to the lower potential side, it can be detected that the input 4 on the previously changed side was at the higher potential level. Time T when both comparison outputs start from H
When T2 and T5 are considered, when the swing power source swings to the high potential side, it can be detected that the input on the previously changed side was at the low potential level. Although a NAND flip-flop is used in the above embodiment, a NOR flip-flop may be used.

【0014】次に、本発明による電位変換回路を液晶表
示装置の走査線ドライバーに使用する場合の実施例を図
4に示す。走査線ドライバーは従来例のタイミング図6
で示したように、通常は行クロックLPと先頭行を示す
FLM信号を入力し、LPの立ち下がりに同期して複数
の走査線出力S1〜Snに順次走査パルスを出力する
が、本実施例ではFLM信号にのみ本発明による電位変
換回路を用い、LP信号はFLM用電位変換回路を用い
走査線ドライバーの内部で発生する方式を用いている。
走査線ドライバーはS1からSnまでの走査線出力を有
し、それらを順次選択するための線順次アドレッシング
回路42と出力回路43より構成される。線順次アドレ
ッシング回路にはラッチ回路41を直列に接続してなる
シフトレジスター回路を用い、初段ラッチのデータ入力
にシフトデータSDを与え、全段ラッチに共通接続され
たクロック入力にシフトクロックCKを与えることでシ
フトデータをシフトし、選択信号を選択出力Q1〜Qn
に出力する。出力回路は選択出力と揺動電源の極性信号
POLを入力し、非選択走査線には非選択時の走査線出
力電位を出力し、選択走査線には揺動電源の揺動極性に
応じて走査線出力に正または負パルスを出力する。走査
線ドライバーを制御する入力信号としては一定電位電源
動作の論理信号を用い、非反転の入力信号FLMと反転
入力信号FLMBを本発明による電位変換回路40に入
力しその出力をシフトレジスターへのシフトデータSD
とする。電位変換回路の電位比較回路には相補型の電界
効果トランジスタ対からなるインバータ回路を用い、順
序弁別回路には図2に示した回路を用いる。通常LP信
号を使うはずのシフトクロックとしては、順序弁別回路
内のセット信号22とリセット信号23の論理積を論理
積ゲート47でとった信号を用いる。本実施例では線順
次アドレッシング回路にはシフトレジスター方式を用い
たが、カウンタ方式の線順次アドレッシング回路を用い
てもよい。ここで発生するシフトクロックには、図1に
示す電位変換回路における2つの電位比較回路の比較出
力6と9の排他論理和信号になっているが他の構成の排
他論理和回路を用いてもよい。
FIG. 4 shows an embodiment in which the potential conversion circuit according to the present invention is used for a scanning line driver of a liquid crystal display device. Scan line driver is timing chart of the conventional example 6
As shown in the figure, normally, the row clock LP and the FLM signal indicating the first row are input, and the scanning pulses are sequentially output to the plurality of scanning line outputs S1 to Sn in synchronization with the fall of LP. In this method, the potential conversion circuit according to the present invention is used only for the FLM signal, and the LP signal is generated inside the scanning line driver using the FLM potential conversion circuit.
The scanning line driver has scanning line outputs from S1 to Sn, and includes a line sequential addressing circuit 42 and an output circuit 43 for sequentially selecting them. A shift register circuit in which latch circuits 41 are connected in series is used as the line sequential addressing circuit. Shift data SD is applied to the data input of the first stage latch, and shift clock CK is applied to the clock input commonly connected to all the stage latches. To shift the shift data and select the selection signals Q1 to Qn.
Output to The output circuit inputs the selected output and the polarity signal POL of the oscillating power supply, outputs the scanning line output potential at the time of non-selection to the unselected scanning line, and outputs the selected scanning line to the selected scanning line in accordance with the oscillating polarity of the oscillating power supply. Outputs a positive or negative pulse to the scan line output. A logic signal of a constant potential power supply operation is used as an input signal for controlling the scanning line driver, a non-inverted input signal FLM and an inverted input signal FLMB are input to the potential conversion circuit 40 according to the present invention, and the output is shifted to a shift register. Data SD
And An inverter circuit composed of a pair of complementary field-effect transistors is used for the potential comparison circuit of the potential conversion circuit, and the circuit shown in FIG. 2 is used for the order discrimination circuit. As the shift clock that should normally use the LP signal, a signal obtained by calculating the logical product of the set signal 22 and the reset signal 23 in the sequence discriminating circuit by the logical product gate 47 is used. In this embodiment, the shift register system is used for the line sequential addressing circuit, but a line sequential addressing circuit of a counter system may be used. Although the shift clock generated here is an exclusive OR signal of the comparison outputs 6 and 9 of the two potential comparison circuits in the potential conversion circuit shown in FIG. 1, an exclusive OR circuit having another configuration may be used. Good.

【0015】次に動作タイミングを図5にしめす。揺動
電源VDD/VSSはV1/V3〜V2/V4に揺動
し、非選択時の走査線出力電位をVMとする。走査クロ
ックはLPは本実施例では走査線ドライバー内部で発生
するので使用しないが、参考のために示す。先頭行を示
すFLM信号は2発めのLPでHになる。FLMBはそ
の反転信号である。電位変換回路の出力10はFLMが
Hが状態で揺動電源が揺動することでHレベルを出力
し、次に揺動電源が揺動する時にLレベルに戻る。これ
をシフトレジスターのシフトデータSDに与える。一方
シフトクロックCKは図2に示す順序弁別回路のセット
信号22とリセット信号23の論理積からなるのでタイ
ミング図3からわかるように揺動電源が揺動する時に負
のパルスを出力する。このシフトクロックCKの立ち上
がりエッジでシフトデータSDをシフトすることで線順
次アドレッシング回路の出力Q1〜Qnが順次選択さ
れ、その時の揺動電源の状態を示す極性信号POLに応
じて走査線出力S1〜Snに正の選択パルスまたは負の
選択パルスを出力する。シフトクロックは通常のLP信
号のように揺動電源の揺動毎にパルス状の信号を発生す
るのでLP信号の代わりに使用することが可能である。
Next, the operation timing is shown in FIG. The swing power supply VDD / VSS swings from V1 / V3 to V2 / V4, and the scanning line output potential when not selected is VM. The scanning clock is not used because LP is generated inside the scanning line driver in this embodiment, but is shown for reference. The FLM signal indicating the first row becomes H in the second LP. FLMB is its inverted signal. The output 10 of the potential conversion circuit outputs the H level when the oscillating power supply oscillates while the FLM is at the H level, and returns to the L level when the oscillating power supply next oscillates. This is given to the shift data SD of the shift register. On the other hand, the shift clock CK is composed of the logical product of the set signal 22 and the reset signal 23 of the sequence discriminating circuit shown in FIG. 2 and therefore outputs a negative pulse when the oscillating power source oscillates as can be seen from the timing chart 3. By shifting the shift data SD at the rising edge of the shift clock CK, the outputs Q1 to Qn of the line-sequential addressing circuit are sequentially selected, and the scan line outputs S1 to S1 according to the polarity signal POL indicating the state of the oscillating power supply at that time. A positive selection pulse or a negative selection pulse is output to Sn. The shift clock generates a pulse-like signal every time the swing power supply swings like a normal LP signal, and thus can be used instead of the LP signal.

【0016】[0016]

【発明の効果】本発明の電位変換回路は揺動電源動作論
理回路に対し、揺動電源が揺動するときの論理情報を伝
送出来る。これによって揺動電源動作の高電圧出力駆動
回路の駆動波形を、外部の低定電圧回路の駆動情報に応
じて制御出来る。揺動電源構成によって、揺動動作集積
回路の電源電圧振幅よりも大電圧振幅出力を得る事が出
来る。例えば低定電圧回路電圧を5vの論理回路とし、
揺動電源電圧を25vとし、揺動電圧を20vにして揺
動正電位の最低電位を+5v、同揺動負電位の最高電位
を0vとすると、25v動作の駆動ICからー20vか
ら+25vまでの45vの論理振幅の駆動信号を出力す
る事が可能になる。また、揺動電源のが揺動するときに
パルス信号を発生することが出来るので、揺動電源の高
電位側および低電位側の両揺動時に同期した動作をする
回路に対し外部からの信号を供給することなく駆動制御
することが可能。また、本発明の電位変換回路は揺動電
源動作の半導体集積回路に搭載可能なため外部回路が不
要となりコストが低減する。
The potential conversion circuit according to the present invention can transmit logic information when the swing power supply swings to the swing power supply operation logic circuit. This makes it possible to control the drive waveform of the high-voltage output drive circuit in the swing power supply operation according to the drive information of the external low-constant voltage circuit. With the oscillating power supply configuration, it is possible to obtain a voltage amplitude output larger than the power supply voltage amplitude of the oscillating operation integrated circuit. For example, when the low constant voltage circuit voltage is a 5V logic circuit,
Assuming that the swing power supply voltage is 25 V, the swing voltage is 20 V, the minimum swing positive potential is +5 V, and the maximum swing negative potential is 0 V, the drive IC operating at 25 V can operate from −20 V to +25 V. It is possible to output a drive signal having a logic amplitude of 45v. In addition, since a pulse signal can be generated when the oscillating power supply oscillates, an external signal is supplied to a circuit that operates synchronously when the oscillating power supply oscillates on both the high potential side and the low potential side. Drive control without supplying Further, since the potential conversion circuit of the present invention can be mounted on a semiconductor integrated circuit that operates with a swing power supply, an external circuit is not required, and the cost is reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例における電位変換回路のブロッ
ク図である。
FIG. 1 is a block diagram of a potential conversion circuit according to an embodiment of the present invention.

【図2】本発明の実施例における順序弁別回路の回路の
例である。
FIG. 2 is an example of a circuit of a sequential discrimination circuit according to an embodiment of the present invention.

【図3】本発明の実施例における電位変換回路のタイミ
ング図である。
FIG. 3 is a timing chart of the potential conversion circuit in the embodiment of the present invention.

【図4】走査線ドライバーへの応用例を示すブロック図
である。
FIG. 4 is a block diagram showing an application example to a scanning line driver.

【図5】走査線ドライバーへの応用例のタイミング図で
ある。
FIG. 5 is a timing chart of an application example to a scanning line driver.

【図6】走査線ドライバーの動作を説明するタイミング
図である。
FIG. 6 is a timing chart illustrating the operation of the scanning line driver.

【図7】電位変換回路に要求される変換レベルを示す図
である。
FIG. 7 is a diagram illustrating conversion levels required for a potential conversion circuit.

【符号の説明】[Explanation of symbols]

1、2 第一および第二の電位比較回路 3 順序弁別回路 4、7 第一および第二の論理情報信号 5、8 第一および第二の比較電位 6、9 第一および第二の電位比較回路の比較出力 10 電位変換回路の論理出力 20 順序弁別回路を構成するセットリセット型フリッ
プフロップ回路 21 順序弁別回路を構成するセット信号およびリセッ
ト信号発生回路 22、23 セット信号およびリセット信号 40 本発明による電位変換回路 41 線順次アドレッシング回路を構成するデータラッ
チ回路 42 走査線ドライバーを構成する線順次アドレッシン
グ回路 43 走査線ドライバーを構成する走査線出力回路 47 シフトクロックを発生する論理積ゲート VDD 高電位側揺動電源 VSS 低電位側揺動電源 LP 走査線ドライバーを駆動する行クロック FLM、FLMB 走査線ドライバーの先頭行を示す信
号およびその反転信号 FLM、FLMB 走査線ドライバーの先頭行を示す信
号およびその反転信号 SD 線順次アドレッシング回路に入力されるシフトデ
ータ CK 線順次アドレッシング回路を駆動するシフトクロ
ック POL 揺動電源の揺動極性信号 Q1〜Qn 線順次アドレッシング回路の選択出力 S1〜Sn 走査線ドライバーの走査線 VM 非選択時の走査線出力電位 V1 高電位揺動時の高電位側揺動電源電位 V2 低電位揺動時の高電位側揺動電源電位 V3 高電位揺動時の低電位側揺動電源電位 V4 低電位揺動時の低電位側揺動電源電位 LP’ 電位変換後のLP信号 FLM’ 電位変換後のFLM信号
1, 2 First and second potential comparison circuit 3 Order discrimination circuit 4, 7 First and second logic information signal 5, 8 First and second comparison potential 6, 9 First and second potential comparison Comparison output of circuit 10 Logical output of potential conversion circuit 20 Set-reset type flip-flop circuit constituting sequence discrimination circuit 21 Set signal and reset signal generation circuit 22 constituting sequence discrimination circuit 22, 23 Set signal and reset signal 40 According to the present invention Potential conversion circuit 41 Data latch circuit forming a line-sequential addressing circuit 42 Line-sequential addressing circuit forming a scanning line driver 43 Scanning line output circuit forming a scanning line driver 47 Logical product gate for generating a shift clock VDD High potential swing Dynamic power supply VSS Low-potential-side swing power supply LP Row line driving scan line driver FLM, FLMB Signal indicating the first row of the scanning line driver and its inverted signal FLM, FLMB Signal indicating the first row of the scanning line driver and its inverted signal SD Shift data input to the SD line sequential addressing circuit CK The line sequential addressing circuit Shift clock to be driven POL Swing polarity signal of oscillating power supply Q1 to Qn Select output of line-sequential addressing circuit S1 to Sn Scan line of scan line driver VM Scan line output potential when non-selected V1 High potential during high potential swing Side swing power supply potential V2 High potential swing power supply potential at low potential swing V3 Low potential swing power supply potential at high potential swing V4 Low potential swing power supply potential at low potential swing LP 'potential LP signal after conversion FLM 'FLM signal after potential conversion

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 一定電位差を保ちつつ対接地電位が揺動
する揺動電源回路を備えた揺動電源動作の第一の信号処
理回路と、対接地電位が一定の定電位電源動作の第二の
信号処理回路とを備え、該第二の信号処理回路は論理情
報を該第一の信号処理回路に伝達し、該第一の信号処理
回路には揺動電源動作の第一の電位比較回路と、第二の
電位比較回路と、該第一の電位比較回路の出力と該第二
の電位比較回路の出力を入力し2つの電位比較回路の出
力の論理状態が遷移するときの時間的順序情報を処理す
る順序弁別回路とを備え、該第二の信号処理回路に入力
された第一の論理情報信号を該第一電位比較回路に与
え、第二の論理情報信号を該第二の電位比較回路に与
え、電位比較回路の出力変化情報を該順序弁別回路が処
理した結果を論理出力とし、第二の信号処理回路の論理
情報により該論理出力を制御する構造を備えた電位変換
回路。
1. A first signal processing circuit for oscillating power supply operation comprising an oscillating power supply circuit for oscillating a ground potential while maintaining a constant potential difference, and a second signal processing circuit for a constant potential power supply operation with a constant ground potential. Wherein the second signal processing circuit transmits logic information to the first signal processing circuit, and the first signal processing circuit includes a first potential comparison circuit for oscillating power supply operation. And a second potential comparison circuit, and a temporal sequence when the outputs of the first potential comparison circuit and the output of the second potential comparison circuit are input and the logic states of the outputs of the two potential comparison circuits transition. And a sequence discriminating circuit for processing information, the first logical information signal input to the second signal processing circuit is provided to the first potential comparison circuit, the second logical information signal is the second potential The result of processing the output change information of the potential comparison circuit by the order discrimination circuit is provided as a logical output to the comparison circuit. And a potential conversion circuit having a structure for controlling the logical output according to the logical information of the second signal processing circuit.
【請求項2】 一定電位差を保ちつつ対接地電位が揺動
する揺動電源回路を備えた揺動電源動作の第一の信号処
理回路と、対接地電位が一定の定電位電源動作の第二の
信号処理回路とを備え、該第二の信号処理回路は論理情
報を該第一の信号処理回路に伝達し、該第一の信号処理
回路には揺動電源動作の第一の電位比較回路と、第二の
電位比較回路と、該第一の電位比較回路の出力と該第二
の電位比較回路の出力を入力し2つの電位比較回路の出
力の論理状態が遷移するときの時間的順序情報を処理す
る順序弁別回路とを備え、該第一の信号処理回路に入力
された第一の論理情報信号を該第一電位比較回路に与
え、該第一の論理情報とは逆極性の第二の論理情報信号
を該第二の電位比較回路に与え、揺動電源揺動時に電位
比較回路の出力が変化するよう選んだ比較電位をそれぞ
れの電位比較回路に与え、電位比較回路の出力がある論
理状態からそれぞれ反転した論理状態に遷移するときの
時間的順序情報を該順序弁別回路が処理した結果を論理
出力とし、第二の信号処理回路の論理情報により該論理
出力を制御する構造を備えた電位変換回路。
2. A first signal processing circuit for oscillating power supply operation comprising an oscillating power supply circuit for oscillating a ground potential while maintaining a constant potential difference, and a second signal processing circuit for a constant potential power supply operation with a constant ground potential. Wherein the second signal processing circuit transmits logic information to the first signal processing circuit, and the first signal processing circuit includes a first potential comparison circuit for oscillating power supply operation. And a second potential comparison circuit, and a temporal sequence when the outputs of the first potential comparison circuit and the output of the second potential comparison circuit are input and the logic states of the outputs of the two potential comparison circuits transition. And a sequence discriminating circuit for processing information, the first logical information signal input to the first signal processing circuit is provided to the first potential comparison circuit, the first logical information of the opposite polarity of the first logical information The second logic information signal is supplied to the second potential comparison circuit, and the output of the potential comparison circuit changes when the power supply swings. Is applied to each potential comparison circuit, and the output of the potential comparison circuit processes the temporal order information at the time of transition from one logic state to the inverted logic state. A potential conversion circuit having a structure that outputs and controls the logical output according to logical information of a second signal processing circuit.
【請求項3】 一定電位差を保ちつつ対接地電位が揺動
する揺動電源回路を備えた揺動電源動作の第一の信号処
理回路と、対接地電位が一定の定電位電源動作の第二の
信号処理回路とを備え、該第二の信号処理回路は論理情
報を該第一の信号処理回路に伝達し、該第一の信号処理
回路には揺動電源動作の第一の電位比較回路と、第二の
電位比較回路と、該第一の電位比較回路の出力と該第二
の電位比較回路の出力を入力し2つの電位比較回路の出
力の論理状態が遷移するときの時間的順序情報を処理す
る順序弁別回路とを備え、該第二の信号処理回路に入力
された第一の論理情報信号を該第一電位比較回路に与
え、該第一および該第二の電位比較回路は閾値を有する
インバータ回路から構成され、第二の論理情報信号を該
第二の電位比較回路に与え、電位比較回路の出力変化情
報を該順序弁別回路が処理した結果を論理出力とし、第
二の信号処理回路の論理情報により該論理出力を制御す
る構造を備えた電位変換回路。
3. A first signal processing circuit for oscillating power supply operation comprising an oscillating power supply circuit for oscillating a ground potential while maintaining a constant potential difference, and a second signal processing circuit for constant power supply operation with a constant ground potential. Wherein the second signal processing circuit transmits logic information to the first signal processing circuit, and the first signal processing circuit includes a first potential comparison circuit for oscillating power supply operation. And a second potential comparison circuit, and a temporal sequence when the outputs of the first potential comparison circuit and the output of the second potential comparison circuit are input and the logic states of the outputs of the two potential comparison circuits transition. And a sequence discriminating circuit for processing information, the first logical information signal input to the second signal processing circuit is provided to the first potential comparison circuit, the first and second potential comparison circuit, A second logic information signal to the second potential comparison circuit. A potential conversion circuit having a structure in which a result obtained by processing the output change information of the potential comparison circuit by the order discriminating circuit is used as a logical output and the logical output is controlled by the logical information of the second signal processing circuit.
【請求項4】 一定電位差を保ちつつ対接地電位が揺動
する揺動電源回路を備えた揺動電源動作の第一の信号処
理回路と、対接地電位が一定の定電位電源動作の第二の
信号処理回路とを備え、該第二の信号処理回路は論理情
報を該第一の信号処理回路に伝達し、該第一の信号処理
回路には揺動電源動作の第一の電位比較回路と、第二の
電位比較回路と、該第一の電位比較回路の出力と該第二
の電位比較回路の出力を入力し2つの電位比較回路の出
力の論理状態が遷移するときの時間的順序情報を処理す
る順序弁別回路とを備え、該第一の信号処理回路に入力
された第一の論理情報信号を該第一電位比較回路に与
え、該第一の論理情報とは逆極性の第二の論理情報信号
を該第二の電位比較回路に与え、揺動電源揺動時に電位
比較回路の出力が変化するよう選んだ比較電位をそれぞ
れの電位比較回路に与え、該順序弁別回路は該第一の比
較出力と該第二の比較出力の反転信号との論理積ををセ
ット信号とし、該第二の比較出力と該第一の比較出力の
反転信号との論理積ををりセット信号をするセットリセ
ット型フリップフロップとから構成され、フリップフロ
ップの出力を該順序弁別回路の論理出力とし、第二の信
号処理回路の論理情報により該論理出力を制御する構造
を備えた電位変換回路。
4. A first signal processing circuit for oscillating power supply operation comprising an oscillating power supply circuit for oscillating a ground potential while maintaining a constant potential difference, and a second signal processing circuit for a constant potential power supply operation with a constant ground potential. Wherein the second signal processing circuit transmits logic information to the first signal processing circuit, and the first signal processing circuit includes a first potential comparison circuit for oscillating power supply operation. And a second potential comparison circuit, and a temporal sequence when the outputs of the first potential comparison circuit and the output of the second potential comparison circuit are input and the logic states of the outputs of the two potential comparison circuits transition. And a sequence discriminating circuit for processing information, the first logical information signal input to the first signal processing circuit is provided to the first potential comparison circuit, the first logical information of the opposite polarity of the first logical information The second logic information signal is supplied to the second potential comparison circuit, and the output of the potential comparison circuit changes when the power supply swings. To the respective potential comparison circuits, and the order discrimination circuit sets a logical product of the first comparison output and an inverted signal of the second comparison output as a set signal, and A set-reset flip-flop that performs a logical product of a comparison output and an inverted signal of the first comparison output to generate a set signal, the output of the flip-flop being a logic output of the sequence discrimination circuit, A potential conversion circuit having a structure for controlling the logic output based on logic information of a signal processing circuit.
【請求項5】 一定電位差を保ちつつ対接地電位が揺動
する揺動電源回路を備えた揺動電源動作の第一の信号処
理回路と、対接地電位が一定の定電位電源動作の第二の
信号処理回路とを備え、該第二の信号処理回路は論理情
報を該第一の信号処理回路に伝達し、該第一の信号処理
回路には揺動電源動作の第一の電位比較回路と、第二の
電位比較回路と、該第一の電位比較回路の出力と該第二
の電位比較回路の出力を入力し2つの電位比較回路の出
力の論理状態が遷移するときの時間的順序情報を処理す
る順序弁別回路とを備え、該第一の信号処理回路に入力
された第一の論理情報信号を該第一電位比較回路に与
え、該第一の論理情報とは逆極性の第二の論理情報信号
を該第二の電位比較回路に与え、揺動電源揺動時に電位
比較回路の出力が変化するよう選んだ比較電位をそれぞ
れの電位比較回路に与え、該第一電位比較回路の比較出
力と該第二の電位比較回路の比較出力の排他論理和を論
理出力として、揺動電源が揺動した時点で発生する該論
理出力を用いて該第一の信号処理回路を制御するする構
造を備えた電位変換回路。
5. A first signal processing circuit for oscillating power supply operation comprising an oscillating power supply circuit for oscillating a ground potential while maintaining a constant potential difference, and a second signal processing circuit for a constant potential power supply operation with a constant ground potential. Wherein the second signal processing circuit transmits logic information to the first signal processing circuit, and the first signal processing circuit includes a first potential comparison circuit for oscillating power supply operation. And a second potential comparison circuit, and a temporal sequence when the outputs of the first potential comparison circuit and the output of the second potential comparison circuit are input and the logic states of the outputs of the two potential comparison circuits transition. And a sequence discriminating circuit for processing information, the first logical information signal input to the first signal processing circuit is provided to the first potential comparison circuit, the first logical information of the opposite polarity of the first logical information The second logic information signal is supplied to the second potential comparison circuit, and the output of the potential comparison circuit changes when the power supply swings. To the respective potential comparators, and the oscillating power supply oscillates using the exclusive OR of the comparison output of the first potential comparator and the comparison output of the second potential comparator as a logical output. A potential conversion circuit having a structure for controlling the first signal processing circuit by using the logical output generated at the time when the potential conversion is performed.
【請求項6】 前記第一の信号処理回路を同一半導体集
積回路チップ上に形成し、外部に設けた前記第二の信号
処理回路からの論理情報を入力して揺動電源電位からな
る論理情報に電位変換し、該第一の信号処理回路を制御
する特許請求の範囲第1項から請求範囲第5項記載の電
位変換回路。
6. The first signal processing circuit is formed on the same semiconductor integrated circuit chip. Logic information from the second signal processing circuit provided externally is input to the first signal processing circuit to generate logic information comprising a swing power supply potential. 6. The potential conversion circuit according to claim 1, wherein the potential conversion circuit controls the first signal processing circuit.
JP10088523A 1998-04-01 1998-04-01 Potential conversion circuit Pending JPH11289247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10088523A JPH11289247A (en) 1998-04-01 1998-04-01 Potential conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10088523A JPH11289247A (en) 1998-04-01 1998-04-01 Potential conversion circuit

Publications (1)

Publication Number Publication Date
JPH11289247A true JPH11289247A (en) 1999-10-19

Family

ID=13945206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10088523A Pending JPH11289247A (en) 1998-04-01 1998-04-01 Potential conversion circuit

Country Status (1)

Country Link
JP (1) JPH11289247A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002039179A1 (en) * 2000-11-08 2002-05-16 Citizen Watch Co., Ltd. Liquid crystal display apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002039179A1 (en) * 2000-11-08 2002-05-16 Citizen Watch Co., Ltd. Liquid crystal display apparatus

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