JPH11288973A - Connection structure for semiconductor device, connection of semiconductor device, and semiconductor device - Google Patents
Connection structure for semiconductor device, connection of semiconductor device, and semiconductor deviceInfo
- Publication number
- JPH11288973A JPH11288973A JP8868798A JP8868798A JPH11288973A JP H11288973 A JPH11288973 A JP H11288973A JP 8868798 A JP8868798 A JP 8868798A JP 8868798 A JP8868798 A JP 8868798A JP H11288973 A JPH11288973 A JP H11288973A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- hole
- semiconductor
- film
- conductive member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＩＣチップ等の集積
回路体や、回路素子を搭載した基板の前記集積回路体を
他の回路基板の電気配線部と電気接続するための接続構
造又は接続方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure or a connection method for electrically connecting an integrated circuit such as an IC chip or an integrated circuit of a substrate on which circuit elements are mounted to an electric wiring portion of another circuit board. About.
【０００２】更に、本発明は、フイルムなどの薄いシー
ト部材上に半導体素子をボンデイングし、該半導体素子
を他の回路基板の電気配線部に、前記フイルム上の半導
体素子とのボンデイングする配線部上にメッキ材料を生
成し、該メッキ材料による電気的及び機械的接合を図る
半導体デバイス技術に関する。Further, the present invention relates to a method for bonding a semiconductor element on a thin sheet member such as a film, and connecting the semiconductor element to an electric wiring section of another circuit board on a wiring section for bonding with the semiconductor element on the film. The present invention relates to a semiconductor device technology for generating a plating material for electrical and mechanical bonding by the plating material.
【０００３】[0003]
【従来の技術】集積回路体を搭載した回路基板の接続構
造として、BGA（Ball Grid Array）と称する実装形態が
ある。2. Description of the Related Art As a connection structure of a circuit board on which an integrated circuit is mounted, there is a mounting form called a BGA (Ball Grid Array).
【０００４】該BGAは、プリント基板の一面に集積回路
体（ICチップ）を載せ、プリント基板上の配線部と集積
回路体の電極部をワイヤーボンデイング接続し、前記集
積回路体が載っているプリント基板上面を樹脂成形で覆
って集積回路体を封止し、前記プリント基板の他面側に
マトリックス状に形成した電極部上にはんだボールを載
せ、リフロ工程により前記ボールを溶融させ電極部と接
合させる構成である。In the BGA, an integrated circuit body (IC chip) is mounted on one surface of a printed circuit board, and a wiring portion on the printed circuit board is connected to an electrode portion of the integrated circuit body by wire bonding, and a printed circuit on which the integrated circuit body is mounted is mounted. The upper surface of the substrate is covered with resin molding to seal the integrated circuit body, and a solder ball is placed on an electrode portion formed in a matrix on the other surface side of the printed circuit board, and the ball is melted by a reflow process and joined to the electrode portion. It is a configuration to make it.
【０００５】このBGA形式のマトリックス状の電極部は
そのピッチ間隔は１．５ｍｍ，１．２７ｍｍ，１．００
ｍｍと、実装技術に要求される実装密度としては比較的
緩いピッチである。[0005] The pitch of the matrix-shaped electrodes of the BGA type is 1.5 mm, 1.27 mm, 1.00.
mm, which is a relatively loose pitch as a mounting density required for mounting technology.
【０００６】今日において、集積回路体の集積度の向
上、プリント基板の電気配線部の実装密度の向上などの
理由により、BGAの電極部のピッチ間隔の更なる狭小化
が求められている。[0006] Today, there is a demand for further narrowing the pitch interval between the electrode portions of the BGA for reasons such as an increase in the degree of integration of the integrated circuit body and an increase in the mounting density of the electric wiring portion of the printed circuit board.
【０００７】実装密度向上の技術として例えば、ＵＳＰ
５５９２０２５の提案がある。As a technology for improving the mounting density, for example, USP
There is a proposal of 5592025.
【０００８】該USP‘０２５は、半導体ｄｉｅ５０が基
板４０上のPad47にワイヤーボンデイングされ、複数の
はんだボール５６を基板に付着して、ダイ５０のための
外部電気接続を設けるように構成している。The USP'025 is configured such that a semiconductor die 50 is wire-bonded to a Pad 47 on a substrate 40 and a plurality of solder balls 56 are attached to the substrate to provide an external electrical connection for the die 50. .
【０００９】[0009]
【発明が解決しようとする課題】上記USP‘０２５に示
す実装形態は、電極部５６が基板４０に形成した穴の底
部に位置しているために、電極部のピッチが狭小化する
場合に、はんだボールが接続する電極部の面積が小さく
なり接続強度が弱く、プリント基板との接合を行った後
の接合信頼性が低下する。In the mounting form shown in the above USP '025, since the electrode portion 56 is located at the bottom of the hole formed in the substrate 40, when the pitch of the electrode portion is narrowed, The area of the electrode portion to which the solder ball connects is reduced, the connection strength is weak, and the bonding reliability after bonding with the printed circuit board is reduced.
【００１０】更に、前記ＵＳＰ‘０２５の基板の半田ボ
ール５６を他のプリント基板と接合させる時に、半田を
加熱溶融する際に、気化したフラックスの溶剤成分がは
んだ内に混入し、はんだ材が充填されていない空膨部
（ボイド）となる。そして、このボイドははんだ内を上
昇し、基板の穴内に進入する。Further, when the solder ball 56 of the USP'025 board is bonded to another printed board, when the solder is heated and melted, the solvent component of the vaporized flux is mixed into the solder and the solder material is filled. An unexpanded portion (void) is formed. Then, the voids rise in the solder and enter the holes of the substrate.
【００１１】これにより、基板とはんだボールとの接合
面積が減少することになり、この結果、接合信頼性を損
ねることになる。As a result, the joint area between the substrate and the solder ball is reduced, and as a result, the joint reliability is impaired.
【００１２】[0012]
【課題を解決するための手段】上記課題を解決するため
に本発明は、集積回路体を備えた第一の回路基板と第二
の回路基板を接続した半導体において、前記第一の回路
基板上の一方の面に電気接続配線部を設け、前記第一の
回路基板に、電気接続配線部が露出する穴が形成され、
穴を埋め込むように電極部を生成し、該生成した電極部
は前記穴の他面側表面上から突出形成し、前記突出形成
した電極部上に導通部材を載置し、導通部材を介して前
記第二の回路基板との電気的接続を行うようにしたこと
を特徴とした半導体の接続構造を提案する。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a semiconductor in which a first circuit board provided with an integrated circuit and a second circuit board are connected to each other. An electric connection wiring portion is provided on one surface of the first circuit board, and a hole through which the electric connection wiring portion is exposed is formed on the first circuit board,
An electrode part is generated so as to fill the hole, the generated electrode part is formed to protrude from the other surface of the hole, a conductive member is placed on the protruded electrode part, and A connection structure of a semiconductor, wherein the connection structure with the second circuit board is made electrically, is proposed.
【００１３】又、第一の基板の第一面側に配線部を設
け、該配線部に穴を形成し、前記配線部を底面として前
記穴内に電気導通部を生成し、該生成した電気導通部は
前記第一基板の他面側に突出させ、該突出した電気導通
部上に電極部材を配置し、電極部材を介して第二の基板
の電気導通部と電気接続させ、前記第一又は第二の基板
に半導体を接続するようにしたことを特徴とした半導体
の接続構造の提案により実装密度向上の課題の解決を図
る。A wiring portion is provided on the first surface side of the first substrate, a hole is formed in the wiring portion, and an electrical conduction portion is formed in the hole with the wiring portion serving as a bottom surface. The portion is protruded to the other surface side of the first substrate, an electrode member is disposed on the protruding electrical conduction portion, and electrically connected to the electrical conduction portion of the second substrate through the electrode member, Solution to the Problem of Improvement in Mounting Density by Proposal of a Connection Structure of a Semiconductor In Which a Semiconductor is Connected to a Second Substrate.
【００１４】更に、前記第一の基板に生成した電気導通
部はその突出面が平坦であることを特徴とした半導体の
接続構造とすることにより接合の信頼性の向上を図る。Further, the reliability of bonding is improved by adopting a semiconductor connection structure characterized in that the projecting surface of the electric conduction portion formed on the first substrate is flat.
【００１５】又、前記第一基板に生成した電気導通部の
突出面に凹部を形成したことを特徴とした半導体の接続
構造の態様を提案する。[0015] The present invention also proposes an aspect of a semiconductor connection structure, wherein a recess is formed on a protruding surface of an electric conduction portion formed on the first substrate.
【００１６】本発明の１つは、穴を形成した第一の回路
基板の該穴を塞ぐように回路配線部を配線して該配線部
に集積回路体を接続し、前記穴の開口側にメッキ材料で
前記配線部との電気的導通を保つ電極部を形成し、前記
電極部に導通部材を載せ、該導通部材を介して第二の回
路基板の導通部との電気的接続を行うようにしたことを
特徴とした半導体の接続構造を提案する。According to one aspect of the present invention, a circuit wiring portion is wired so as to cover the hole of a first circuit board having a hole formed therein, and an integrated circuit is connected to the wiring portion. An electrode portion for maintaining electrical continuity with the wiring portion is formed of a plating material, a conductive member is placed on the electrode portion, and an electrical connection with the conductive portion of the second circuit board is performed via the conductive member. We propose a semiconductor connection structure characterized by the following.
【００１７】更に、前記メッキ材料は前記第一回路基板
の穴から突出形成されていることを特徴とした半導体の
接続構造により信頼性の向上を図る。Further, the reliability is improved by the semiconductor connection structure, wherein the plating material is formed so as to protrude from the hole of the first circuit board.
【００１８】そして、前記メッキ材料は前記貫通穴から
突出して前記第一回路基板の一部の表面を覆うように形
成したことを特徴とすることにより、機械強度を図った
半導体の接続構造を提案する。Further, the present invention proposes a semiconductor connection structure with high mechanical strength, characterized in that the plating material is formed so as to project from the through hole and cover a part of the surface of the first circuit board. I do.
【００１９】更に、本発明の１つは、集積回路体を載せ
た樹脂材料製シート部材の前記集積回路体と電気接続す
る配線部の位置の前記シート部材に穴を形成し、前記穴
を電気メッキ材料を埋め込んで前記配線部と電気的導通
した導通部を前記シート部材の他面側に表出させ、前記
表出した導通部上にボール状導通部材を載せ、該導通部
材を介して回路基板の電気接続部と接続するようにした
ことを特徴とした半導体の接続構造とすることにより実
装構成の薄型化を図る。Further, according to one aspect of the present invention, a hole is formed in the sheet member at a position of a wiring portion electrically connected to the integrated circuit body of the sheet member made of a resin material on which the integrated circuit body is mounted, and the hole is electrically connected. A conductive portion that is electrically connected to the wiring portion by embedding a plating material is exposed on the other surface side of the sheet member, a ball-shaped conductive member is placed on the exposed conductive portion, and a circuit is connected through the conductive member. The thickness of the mounting structure is reduced by using a semiconductor connection structure characterized by being connected to the electrical connection portion of the substrate.
【００２０】そして、前記シート部材はフイルムである
ことを特徴とした半導体の接続構造としての特徴を図
る。The sheet member is a film, and is characterized as a semiconductor connection structure.
【００２１】又、本発明の１つは、集積回路体を載せた
第一の回路基板に第二の回路基板を接続するための半導
体の接続方法の特徴として、 ａ．前記第一の回路基板上の前記集積回路体と接続する
電気配線部に穴を設ける工程、 ｂ．前記第一回路基板の前記電気配線部を底面として前
記穴内に電極部を埋め込み生成し、該電極部を第一回路
基板の他面側に突出形成する工程、 ｃ．前記突出形成した電極部上にボール状導通部材を載
せる工程、 ｄ．前記ボール状導通部材を介して前記第一回路基板と
前記第二の回路基板とを電気的に接続する工程による製
造プロセスを提案することにより上記課題の解決を図
る。One aspect of the present invention is a feature of a method of connecting a semiconductor for connecting a second circuit board to a first circuit board on which an integrated circuit body is mounted, comprising: a. Providing a hole in an electric wiring portion connected to the integrated circuit body on the first circuit board; b. Forming an electrode portion in the hole by using the electric wiring portion of the first circuit board as a bottom surface and projecting the electrode portion to the other surface side of the first circuit board; c. Placing a ball-shaped conductive member on the protruding electrode portion; d. The above object is achieved by proposing a manufacturing process in which the first circuit board and the second circuit board are electrically connected via the ball-shaped conductive member.
【００２２】そして、前記発明の、前記第一回路基板上
に生成した電極部上面を平坦処理する工程を含む事を特
徴とした半導体の接続方法の提案により回路実装構造の
安定性の向上を図る。Further, the present invention aims at improving the stability of the circuit mounting structure by proposing a method of connecting semiconductors, characterized by including a step of flattening the upper surface of the electrode portion formed on the first circuit board. .
【００２３】又、前記第一回路基板上に生成した電極部
上面に凹部を形成する工程を含むことを特徴とした実施
態様を提案する。Further, an embodiment is proposed wherein the method includes a step of forming a concave portion on the upper surface of the electrode portion generated on the first circuit board.
【００２４】又、本発明の１つは、集積回路体を備えた
フイルムに回路基板を電気接続するための半導体の接続
方法の特徴として、 ａ．前記フイルム上に電気配線部を形成し、前記電気配
線部上のフイルム部分を除去して穴を形成する工程と、 ｂ．前記フイルム上の電気配線部を底面として前記穴内
をメッキ材料で埋め込んで該メッキ材料を介して前記電
気配線部の導通部を前記フイルムの他面側に表出させる
工程と、 ｃ．前記フイルムに集積回路体を載せ、前記電気配線部
と接続する工程と、 ｄ．前記導通部上に前記回路基板との電気接続のための
導通部材を載せる工程と、 ｅ．前記フイルムの貫通穴の前記メッキ材料と前記導通
部材を合金化させ、該導通部材の表面を略球形状にする
工程と、 ｆ．前記フイルム上の前記導通部材と前記回路基板の電
気接続部との電気的接続を行う工程から成る製造プロセ
スの提案をする。One aspect of the present invention is a feature of a semiconductor connection method for electrically connecting a circuit board to a film having an integrated circuit body. Forming an electrical wiring portion on the film, removing the film portion on the electrical wiring portion to form a hole, b. A step of embedding the inside of the hole with a plating material with the electric wiring portion on the film as a bottom surface and exposing a conductive portion of the electric wiring portion to the other surface of the film via the plating material; c. Placing an integrated circuit body on the film and connecting to the electric wiring portion; d. Placing a conductive member on the conductive portion for electrical connection with the circuit board; e. Alloying the plating material in the through-hole of the film with the conductive member to make the surface of the conductive member substantially spherical, f. The present invention proposes a manufacturing process including a step of making an electrical connection between the conductive member on the film and an electrical connecting portion of the circuit board.
【００２５】そして、前記記載の工程において、前記表
出部分は前記穴から突出し、突出面を平坦化する工程を
含むことを特徴とした半導体の接続方法による安定性の
向上を図る。In the above-described process, the exposed portion protrudes from the hole and includes a step of flattening the protruding surface, thereby improving the stability by the semiconductor connection method.
【００２６】更に本発明の１つは、フイルム基板上の電
気配線部とボンデイングした半導体素子と前記フイルム
基板に、電気配線部が露出した穴を形成し、露出した電
気配線部からメッキ材料から成る電極部を前記フイルム
基板表面より突出させて形成し、前記突出電極部上にボ
ール状導通部材を接合させ、前記ボール状導通部材を回
路基板の電極部と接続させるようにしたことを特徴とし
た半導体デバイスを提案する。Further, one aspect of the present invention is to form a hole in which the electric wiring portion is exposed in the semiconductor element bonded to the electric wiring portion on the film substrate and the film substrate, and to form a plating material from the exposed electric wiring portion. An electrode portion is formed so as to protrude from the surface of the film substrate, a ball-shaped conductive member is joined to the protruding electrode portion, and the ball-shaped conductive member is connected to an electrode portion of the circuit board. A semiconductor device is proposed.
【００２７】[0027]
【発明の実施の形態】（第一の実施例の説明）以下図を
参照して本発明の第一の実施例を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Explanation of First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.
【００２８】図１は半導体素子１４を載せた第一基板２
の要部断面を示し、図２は図１の第一回路基板２上の前
記半導体素子１４を第二の回路基板２４の電気配線部２
４ａにはんだボール２２を介して電気接続した要部断面
を示す。FIG. 1 shows a first substrate 2 on which a semiconductor element 14 is mounted.
FIG. 2 shows the semiconductor element 14 on the first circuit board 2 of FIG.
4a shows a cross section of a main part electrically connected via the solder ball 22.
【００２９】図３乃至図９は前記第一回路基板の製造プ
ロセスの説明図である。FIGS. 3 to 9 are explanatory views of the manufacturing process of the first circuit board.
【００３０】図３において、第一基板２はポリイミド樹
脂材料から作られたシート状フイルムである。In FIG. 3, the first substrate 2 is a sheet-like film made of a polyimide resin material.
【００３１】前記第一基板２の材料としては、ポリイミ
ド樹脂、エポキシ樹脂、ＢＴ樹脂、アラミド樹脂等の電
気配線印刷可能な材料であればよい。The material of the first substrate 2 may be any material such as a polyimide resin, an epoxy resin, a BT resin, an aramid resin or the like, on which electric wiring can be printed.
【００３２】また、アルミナ、窒化アルミ等の無機材料
でもよい。In addition, inorganic materials such as alumina and aluminum nitride may be used.
【００３３】厚さは２０〜１００μｍが好適である。The thickness is preferably from 20 to 100 μm.
【００３４】前記フイルム２に、パンチ、ドリルにより
貫通する穴２ａを加工する。A hole 2a is formed in the film 2 by punching and drilling.
【００３５】穴２ａの穴径は０．２５ｍｍである。The diameter of the hole 2a is 0.25 mm.
【００３６】次に、図４に示すように、前記穴２ａの設
けられたフイルムの一方の面に、ポリイミド接着剤４Ｃ
を介して銅箔４を貼り合わせる。Next, as shown in FIG. 4, a polyimide adhesive 4C is applied to one surface of the film provided with the holes 2a.
The copper foil 4 is stuck through.
【００３７】銅箔４の厚さは０．０１〜０．０２ｍｍで
ある。The thickness of the copper foil 4 is 0.01 to 0.02 mm.
【００３８】次に、この銅箔４の表面をメッキマスクレ
ジスト８で覆った後に、メッキ液中に浸し、銅箔４を電
源に接続して電気メッキ処理する。Next, after covering the surface of the copper foil 4 with a plating mask resist 8, the copper foil 4 is immersed in a plating solution, and the copper foil 4 is connected to a power source for electroplating.
【００３９】メッキ液としてピロリン酸銅メッキ液を使
用する場合、液温４０〜７０℃、陰極電流密度１〜１０
Ａ／ｄｍ2，液循環量２〜５サイクル／ｈとした。When a copper pyrophosphate plating solution is used as the plating solution, the solution temperature is 40 to 70 ° C., the cathode current density is 1 to 10
A / dm 2 , and the liquid circulation rate was 2 to 5 cycles / h.
【００４０】上記条件で、図５に示すメッキ工程で前記
基板２の配線部４上の穴２ａをメッキ材料のＣｕ１０で
埋め込む。Under the above conditions, the hole 2a on the wiring portion 4 of the substrate 2 is filled with a plating material Cu10 in the plating step shown in FIG.
【００４１】メッキ工程において図５、６に示すよう
に、メッキ槽内のメッキ液の攪拌を十分に行い、基板２
の穴２ａ内の露出している配線部上にＣｕが堆積生成
し、順次時間経過に伴いメッキ層１０が穴２ａ内を埋
め、メッキ材が穴２ａ内を埋めた後もメッキ作業を続け
ることにより、図６に示すようにメッキ材１０は穴２ａ
から突出するように生成する。In the plating step, as shown in FIGS. 5 and 6, the plating solution in the plating tank was sufficiently stirred,
Cu is deposited and formed on the exposed wiring portion in the hole 2a, the plating layer 10 sequentially fills the hole 2a with the passage of time, and the plating operation is continued even after the plating material fills the hole 2a. As a result, as shown in FIG.
Generated so as to protrude from
【００４２】該メッキ材１０は穴２ａ内の堆積後のフイ
ルム表面からは横方向への成長が可能となり図示するよ
うに略半球形状に成長する。The plating material 10 can grow laterally from the film surface after deposition in the hole 2a, and grows in a substantially hemispherical shape as shown in the figure.
【００４３】該メッキ工程により生成されたＣｕは前記
基板２上の配線部４と一体的に結合して電極部１０（図
６）を構成する。The Cu generated by the plating step is integrally combined with the wiring section 4 on the substrate 2 to form the electrode section 10 (FIG. 6).
【００４４】本例において、電極間ピッチ０．５ｍｍ，
穴径０．２５ｍｍ、突起電極部の半径を０．３ｍｍ，高
さを０．０２〜０．０３ｍｍになるようにした。In this example, the electrode pitch is 0.5 mm,
The hole diameter was 0.25 mm, the radius of the protruding electrode portion was 0.3 mm, and the height was 0.02 to 0.03 mm.
【００４５】次に、マスクレジスト８を剥離する。Next, the mask resist 8 is peeled off.
【００４６】その次に、前記突出した電極部側にマスク
レジストを塗布した後、銅箔４上にレジストを塗布し、
形成したパターンになるようにレジストを露光、現像す
る。Next, after applying a mask resist on the protruding electrode portion side, a resist is applied on the copper foil 4,
The resist is exposed and developed so as to form the formed pattern.
【００４７】その次に、塩化第二鉄等のエッチング液に
より露出している銅箔をエッチングし、レジスト、及
び、マスクレジストを除去する。Next, the exposed copper foil is etched with an etchant such as ferric chloride to remove the resist and the mask resist.
【００４８】そして、図７に示すように形成された配線
パターン上に、保護用レジストを塗布し、半導体素子と
接続する部分４Ｂが露出するように露光、現像する。Then, a protective resist is applied on the wiring pattern formed as shown in FIG. 7, and is exposed and developed so that the portion 4B connected to the semiconductor element is exposed.
【００４９】以上の工程により、フイルム基板２上に配
線部４の反対側の面に該配線部４と導通した突起電極部
１０を備えたフイルム基板２が出来上がる。Through the steps described above, the film substrate 2 having the projecting electrode portions 10 electrically connected to the wiring portions 4 on the surface opposite to the wiring portions 4 on the film substrate 2 is completed.
【００５０】このようにして形成したフイルム基板２の
配線部４を形成した面上にダイボンデイングペースト１
２を塗布し、半導体素子１４を載せ、半導体素子の電極
部と露出した配線部４ＢとをＡｕ線１６によるワイヤー
ボンデイング接続し、フイルム基板２上の半導体素子を
トランスファーモールデイング加工して樹脂材料１８に
より半導体素子１４を前記フイルム基板２上に封止固定
する。The die bonding paste 1 is applied on the surface of the film substrate 2 thus formed on which the wiring portions 4 are formed.
2, the semiconductor element 14 is mounted thereon, and the electrode part of the semiconductor element and the exposed wiring part 4 </ b> B are wire-bonded and connected by the Au wire 16, and the semiconductor element on the film substrate 2 is subjected to transfer molding processing to obtain a resin material 18. To seal and fix the semiconductor element 14 on the film substrate 2.
【００５１】その後、前記突起電極部１０上に粘着性フ
ラックス２０を塗布し、電極部１０上にはんだボール２
２を載置する。（図９）Thereafter, an adhesive flux 20 is applied on the protruding electrode portions 10 and the solder balls 2 are applied on the electrode portions 10.
2 is placed. (FIG. 9)
【００５２】はんだボール２２は直径０．２〜０．６ｍ
ｍのものを用いた。The solder ball 22 has a diameter of 0.2 to 0.6 m.
m.
【００５３】はんだボール２２のはんだ組成としては、
Ｐｂ―Ｓｎ、Ｐｂ−Ｓｎ−Ａｇ，Ｐｂ−Ｓｎ−Ｂｉ等を
使用する。The solder composition of the solder ball 22 is as follows:
Pb-Sn, Pb-Sn-Ag, Pb-Sn-Bi or the like is used.
【００５４】はんだボール２２を載せた基板２をはんだ
リフロー工程に通すことにより、はんだ融点以上に加熱
してはんだを溶融する。The substrate 2 on which the solder balls 22 are mounted is passed through a solder reflow process, so that the substrate 2 is heated to a temperature higher than the melting point of the solder to melt the solder.
【００５５】これによりフイルム基板２の電極部１０と
はんだボール２２とを合金化する。その際、はんだボー
ル２２は溶融しつつ突起電極部１０の表面上を覆い包む
とともに、表面張力作用により図１に示すように、その
先端部は略球形状を成す。その後、第二の回路基板２４
を用意する。Thus, the electrode portion 10 of the film substrate 2 and the solder ball 22 are alloyed. At this time, the solder ball 22 covers the surface of the protruding electrode portion 10 while melting, and the tip portion has a substantially spherical shape as shown in FIG. 1 by the action of surface tension. Then, the second circuit board 24
Prepare
【００５６】該第二回路基板２４は回路素子を電気接続
させるための配線電極部２４ａを備えている。The second circuit board 24 has a wiring electrode portion 24a for electrically connecting circuit elements.
【００５７】図２において、前記図３乃至図９に示した
工程で製作した第一の基板２のはんだボール２２と第二
の回路基板２４の配線電極部２４ａとを位置合せした後
に、リフロー工程に流すことにより第一基板２と第二回
路基板２４は電気的／機械的に接合され、第一基板２の
半導体素子１４は配線部４、メッキ材料の導通部突起１
０、はんだボール２２及び第二回路基板の配線電極部２
４ａと電気的に接続した状態になる。In FIG. 2, after the solder balls 22 of the first substrate 2 manufactured in the steps shown in FIGS. 3 to 9 are aligned with the wiring electrode portions 24a of the second circuit board 24, a reflow process is performed. The first substrate 2 and the second circuit board 24 are electrically / mechanically bonded to each other by flowing the semiconductor element 14 of the first substrate 2 into the wiring portion 4 and the conductive portion protrusion 1 of the plating material.
0, solder ball 22 and wiring electrode part 2 of second circuit board
4a.
【００５８】図２の構成において、第一基板（フイルム
２）と第二回路基板２４とは一体的に結合された半導体
デバイスを構成する。In the configuration shown in FIG. 2, the first substrate (film 2) and the second circuit board 24 constitute a semiconductor device integrally connected.
【００５９】本実施例によれば、半導体等の集積回路体
１４を備えた第一の基板２と第二の回路基板２４を接続
した半導体において、前記第一の基板上に電気接続配線
部４を設け、該電気接続配線部４に貫通穴２ａを形成
し、前記貫通穴２ａから表出している前記電気接続配線
部４上に、前記貫通穴を埋め込むように電極部１０を生
成し、該生成した電極部は前記貫通穴の他面側表面上か
ら突出形成し、前記突出形成した電極部上に導通部材２
２を載置し、導通部材２２を介して前記第二の回路基板
との電気的接続を行うようにした半導体の接続構造を得
る事ができた。According to this embodiment, in the semiconductor in which the first substrate 2 provided with the integrated circuit body 14 such as a semiconductor and the second circuit board 24 are connected, the electric connection wiring portion 4 is provided on the first substrate. A through hole 2a is formed in the electric connection wiring portion 4, and the electrode portion 10 is generated on the electric connection wiring portion 4 exposed from the through hole 2a so as to fill the through hole. The generated electrode portion is formed so as to protrude from the other surface of the through hole, and a conductive member 2 is formed on the protruded electrode portion.
2 was placed, and a semiconductor connection structure in which electrical connection with the second circuit board was made via the conductive member 22 was obtained.
【００６０】更に、第一の基板２の第一面側に配線部４
を設け、該配線部４に穴２ａを形成し、前記配線部を底
面として前記穴内に電気導通部１０を生成し、該生成し
た電気導通部は前記第一基板の他面側に突出させ、該突
出した電気導通部上に電極部材２２を配置し、電極部材
２２を介して第二の基板の電気導通部と電気接続させ、
前記第一又は第二の基板に半導体を接続するようにした
ことを特徴とした半導体の接合構造を得る事ができた。Further, the wiring portion 4 is provided on the first surface side of the first substrate 2.
Forming a hole 2a in the wiring portion 4, generating an electrical conduction portion 10 in the hole with the wiring portion as a bottom surface, and causing the generated electrical conduction portion to protrude to the other surface side of the first substrate; The electrode member 22 is disposed on the protruding electric conduction portion, and electrically connected to the electric conduction portion of the second substrate via the electrode member 22,
A semiconductor bonding structure characterized in that a semiconductor is connected to the first or second substrate can be obtained.
【００６１】更に、貫通穴２ａを形成した第一の基板２
の該穴を塞ぐように回路配線部４を配線して該配線部に
集積回路体１４を接続し、前記穴の開口側にメッキ材料
で前記配線部との電気的導通を保つ電極部１０を形成
し、前記電極部に導通部材２２を載せ、該導通部材を介
して第二の回路基板２４の導通部２４ａとの電気的接続
を行うようにしたことを特徴とした半導体の接続構造を
得る事ができた。Further, the first substrate 2 having the through holes 2a formed therein
The circuit wiring portion 4 is wired so as to cover the hole, the integrated circuit body 14 is connected to the wiring portion, and the electrode portion 10 for maintaining electrical conduction with the wiring portion with a plating material is provided on the opening side of the hole. A conductive member 22 is mounted on the electrode part, and the conductive member 22 is electrically connected to the conductive part 24a of the second circuit board 24 via the conductive member. I was able to do things.
【００６２】更に、集積回路体１４を載せた樹脂材料製
シート部材２の前記集積回路体と電気接続する配線部４
の位置の前記シート部材２に穴２ａを形成し、前記穴を
電気メッキ材料を埋め込んで前記配線部と電気的導通し
た導通部１０を前記シート部材の他面側に表出させ、前
記表出した導通部上にボール状導通部材２２を載せ、該
導通部材を介して回路基板の電気接続部と接続するよう
にしたことを特徴とした半導体の接続構造を得ることが
できた。Further, the wiring portion 4 of the resin material sheet member 2 on which the integrated circuit body 14 is mounted, which is electrically connected to the integrated circuit body.
A hole 2a is formed in the sheet member 2 at the position shown in FIG. 3, and the hole is filled with an electroplating material to expose a conductive portion 10 electrically connected to the wiring portion on the other surface side of the sheet member. A ball-shaped conductive member 22 was placed on the conductive portion thus formed, and the ball-shaped conductive member 22 was connected to the electrical connection portion of the circuit board via the conductive member, thereby obtaining a semiconductor connection structure.
【００６３】更に本発明は、集積回路体を載せた第一の
回路基板に第二の回路基板を接続するための半導体の接
続方法として、次に工程、 ａ．前記第一の回路基板上の前記集積回路体と接続する
電気配線部に穴を設ける工程、 ｂ．前記第一回路基板の前記電気配線部を底面として前
記穴内に電極部を埋め込み生成し、該電極部を第一回路
基板の他面側に突出形成する工程、 ｃ．前記突出形成した電極部上にボール状導通部材を載
せる工程、 ｄ．前記ボール状導通部材を介して前記第一回路基板と
前記第二の回路基板とを電気的に接続する工程による製
作工程を経ることで、上記の半導体の接続構造を得るこ
とができた。The present invention further provides a method of connecting a semiconductor for connecting a second circuit board to a first circuit board on which an integrated circuit is mounted, comprising the following steps: a. Providing a hole in an electric wiring portion connected to the integrated circuit body on the first circuit board; b. Forming an electrode portion in the hole by using the electric wiring portion of the first circuit board as a bottom surface and projecting the electrode portion to the other surface side of the first circuit board; c. Placing a ball-shaped conductive member on the protruding electrode portion; d. The semiconductor connection structure described above could be obtained through a manufacturing process of electrically connecting the first circuit board and the second circuit board via the ball-shaped conductive member.
【００６４】（第二の実施例）本実施例は前記第一の実
施例における、第一回路基板２と第二回路基板２４の機
械的結合を更に高めるための改良案である。(Second Embodiment) This embodiment is an improvement of the first embodiment for further enhancing the mechanical coupling between the first circuit board 2 and the second circuit board 24.
【００６５】以下図１０乃至図１3を参照して説明す
る。Hereinafter, description will be made with reference to FIGS. 10 to 13.
【００６６】本第二実施例の工程は前記第一実施例の図
３乃至図７の工程までは同一の工程を採用する。The steps of the second embodiment employ the same steps as those of the first embodiment shown in FIGS.
【００６７】即ち、ポリイミド材料から作られ、電気配
線部４を備えた厚さ２０μｍのフイルム２を用意し、前
記配線部４上のフイルム部分をエッチング加工で穴２ａ
を形成し、メッキ処理により前記穴２ａの配線部４を底
面として電極部１０を生成する。That is, a film 2 made of a polyimide material and having a thickness of 20 μm and provided with an electric wiring portion 4 is prepared, and the film portion on the wiring portion 4 is etched to form a hole 2a.
Is formed, and an electrode portion 10 is formed by plating using the wiring portion 4 of the hole 2a as a bottom surface.
【００６８】その後、図８に説明した工程と同様に、半
導体素子１４をボンデイング／樹脂封止する。（図１
２）Thereafter, the semiconductor element 14 is bonded / resin-sealed in the same manner as in the process described with reference to FIG. (Figure 1
2)
【００６９】本実施例では前記図７の工程までで製作し
た図７記載の第一回路基板（フイルムシート）の前記穴
２ａに形成した突起電極部１０の突起部表面を図１０に
示す成形工程により、該突起部表面を平坦化する。In this embodiment, the surface of the protruding portion of the protruding electrode portion 10 formed in the hole 2a of the first circuit board (film sheet) shown in FIG. 7 manufactured up to the process of FIG. Thereby, the surface of the projection is flattened.
【００７０】図１１は平坦化したフイルム２の要部断面
を示す。FIG. 11 shows a cross section of an essential part of the flattened film 2.
【００７１】図１０は平行平板２５Ａ，２５Ｂを有した
プレス機械により前記突起部分を平坦化する模式図を示
す。FIG. 10 is a schematic diagram of flattening the protruding portion by a press machine having parallel flat plates 25A and 25B.
【００７２】平行平板２５Ａ，２５Ｂの間に図７までの
工程で製造したフイルム基板を置き、１突起部当たり１
０〜１００ｇの荷重を印加して突起頂点の平坦化を実施
する。The film substrate manufactured in the process up to FIG. 7 is placed between the parallel plates 25A and 25B, and one film is formed for each protrusion.
A load of 0 to 100 g is applied to flatten the projection apex.
【００７３】次に、平坦化した突起電極部１０上に粘着
性フラックスを塗布し、その上に、はんだボール２２を
載せて（図１３）、リフロー工程に流して、メッキ工程
の生成電極部１０とはんだボール２２とを溶融して合金
化して図１４に示す構成にする。Next, an adhesive flux is applied on the flattened protruding electrode portion 10, and a solder ball 22 is placed thereon (FIG. 13), and then the reflow process is performed. And the solder ball 22 are melted and alloyed to obtain the configuration shown in FIG.
【００７４】その後、図２に示すように、第二の回路基
板２４の配線部２４ａと第一回路基板に形成した導通部
材１０とを位置合せしてはんだ工程に流して、導通部材
１０により第一回路基板と第二回路基板との電気的／機
械的接合を図る。Thereafter, as shown in FIG. 2, the wiring portion 24a of the second circuit board 24 and the conductive member 10 formed on the first circuit board are aligned and flowed through a soldering process. Electrical / mechanical joining between one circuit board and the second circuit board is achieved.
【００７５】本第二実施例ははんだボール２２を載せる
電極部１０のボール載置面を平坦部に形成したことで搬
送工程やはんだ工程でのはんだボールの位置ずれを防ぐ
事ができた。In the second embodiment, since the ball mounting surface of the electrode portion 10 on which the solder ball 22 is mounted is formed in a flat portion, the displacement of the solder ball in the transporting process and the soldering process can be prevented.
【００７６】又、平坦部上のはんだボール２２を載せて
溶融させて合金化する際に、メッキ材料による生成電極
部１０とはんだボール２２との接続の強度が増すことに
より機械的／電気的結合強度の向上を図る事が出来た。When the solder ball 22 on the flat portion is placed and melted to form an alloy, the strength of the connection between the generated electrode portion 10 and the solder ball 22 by the plating material is increased, so that the mechanical / electrical connection is increased. The strength could be improved.
【００７７】（第三の実施例）第三の実施例ははんだボ
ールの載置性の更なる向上を図る例を示す。(Third Embodiment) The third embodiment shows an example for further improving the mountability of the solder ball.
【００７８】本第三例は、第一実施例の工程説明とほぼ
同じ工程を採用する。The third example employs substantially the same steps as those of the first embodiment.
【００７９】図１５は前記の第一実施例に説明した図３
のフイルム部材２の穴生成の工程と同じ工程である。FIG. 15 is a view similar to FIG. 3 described in the first embodiment.
This is the same step as the step of forming a hole in the film member 2 described above.
【００８０】本例において、前記メッキ工程のメッキ槽
内で、メッキ液の攪拌操作を弱める事で、前記フイルム
の穴２ａ内のメッキ液の交換性を弱めることにより、穴
２ａの中央部の生成成長を低下させて穴の周壁のメッキ
成長のエッジ効果を強め、これにより、結果的に図１６
に示すようにメッキの電極部の中央部分が窪んだ凹部１
０ａを形成させる。（図１６）In this embodiment, the exchange of the plating solution in the hole 2a of the film is weakened by weakening the stirring operation of the plating solution in the plating tank in the plating step, thereby forming the center of the hole 2a. The growth is reduced to enhance the edge effect of plating growth on the peripheral wall of the hole, thereby resulting in FIG.
As shown in the figure, a concave portion 1 in which a central portion of a plated electrode portion is depressed.
0a is formed. (FIG. 16)
【００８１】メッキ処理の条件は、液温４０〜７０℃、
陰極電流密度２〜１２Ａ／ｄｍ2，液循環量は０〜３サ
イクル／ｈである。The conditions of the plating treatment are as follows:
The cathode current density is 2 to 12 A / dm 2 , and the liquid circulation amount is 0 to 3 cycles / h.
【００８２】上記メッキの処理工程は図１７に示すよう
に、メッキ電極部１０が穴２ａ内で成長し、穴の表面上
に突出し、メッキ電極部がフイルムの穴２ａの周囲上面
２ｂ上に堆積するまで続ける。（図１７）In the plating process, as shown in FIG. 17, the plating electrode portion 10 grows in the hole 2a, protrudes above the surface of the hole, and the plating electrode portion is deposited on the upper surface 2b around the hole 2a of the film. Continue until you do. (FIG. 17)
【００８３】上記メッキ作業の条件でフイルムの穴の上
面までメッキ電極の成長を行い、フイルム上のメッキの
厚さが０．０２〜０．０３ｍｍの処でメッキ作業を停止
する。The plating electrode is grown to the upper surface of the film hole under the conditions of the plating operation, and the plating operation is stopped when the thickness of the plating on the film is 0.02 to 0.03 mm.
【００８４】本例では電極部１０の表面の凹部は直径が
０．０２〜０．０３ｍｍ，深さ０．０１〜０．０２ｍｍ
となった。In this embodiment, the concave portion on the surface of the electrode portion 10 has a diameter of 0.02 to 0.03 mm and a depth of 0.01 to 0.02 mm.
It became.
【００８５】メッキ電極の製作工程の終了後マスクレジ
ストの剥離を行う。図１８次に、前記図１８までの工程
で製作した第一の回路基板２上に、半導体素子１４を載
せワイヤーボンデイングと樹脂封止を行う。（図１９）After the production process of the plating electrode is completed, the mask resist is peeled off. FIG. 18 Next, the semiconductor element 14 is mounted on the first circuit board 2 manufactured in the steps up to FIG. 18 and wire bonding and resin sealing are performed. (FIG. 19)
【００８６】その後、前記電極部１０上に粘着性フラッ
クスを塗布し、はんだボール２２を前記凹部１０ｂ上に
載せ、リフロー工程に流し、前記メッキ生成電極部１０
とはんだボール２２の溶融による合金化を行う。（図２
０）Thereafter, an adhesive flux is applied on the electrode portion 10, the solder ball 22 is placed on the concave portion 10b, and the reflow process is performed.
Then, alloying is performed by melting the solder balls 22. (Figure 2
0)
【００８７】図２０に示す第一回路基板の作成後、第二
回路基板の配線部と該第一回路基板の合金化した導通部
２２との位置合せを行いはんだ接合を行って第一回路基
板と第二回路基板の電気的／機会的接合を実施して半導
体の回路接続を行う。図２１。After the first circuit board shown in FIG. 20 has been prepared, the wiring portion of the second circuit board and the conductive portion 22 of the first circuit board are aligned and soldered to form the first circuit board. And the second circuit board are electrically / opportunistically joined to make a semiconductor circuit connection. FIG.
【００８８】本例はメッキ生成電極部１０上を凹部に形
成したのではんだボール２２を載せる工程での安定性を
確保でき、それにより第二回路基板２２との接合のため
の合金化された導通部を穴２ａの中心位置に形成できる
ので第二回路基板と第一回路基板の接合を正確に行う事
が出来た。In the present embodiment, since the recessed portion is formed on the plating generation electrode portion 10, stability in the step of mounting the solder ball 22 can be ensured, and as a result, alloyed conduction for bonding with the second circuit board 22 can be achieved. Since the portion can be formed at the center position of the hole 2a, the joining between the second circuit board and the first circuit board can be performed accurately.
【００８９】[0089]
【発明の効果】本発明に係る半導体の接合を用いること
により第一回路基板と第二回路基板は第一回路基板上の
合金化され、かつ第二回路基板の配線部と接触する部分
が表面張力により丸み形状部分で溶融結合するようにな
るので第一回路基板の配線部４と第二回路基板の配線部
２４ａとの接合の安定性の保証が得られ、回路実装の安
定性が保証できる。According to the present invention, the first circuit board and the second circuit board are alloyed on the first circuit board by using the bonding of the semiconductor according to the present invention, and the portion in contact with the wiring portion of the second circuit board has a surface. Since the melted connection occurs at the rounded portion due to the tension, the stability of the connection between the wiring portion 4 of the first circuit board and the wiring portion 24a of the second circuit board can be guaranteed, and the stability of the circuit mounting can be guaranteed. .
【００９０】又、第一回路基板の合金化導通電極部１０
はメッキ生成した電極部１０を包む込むように形成され
るのではんだ形状の急激な変局部を持たず応力集中しに
くくなるから、接合の信頼性を高くすることができる。The alloyed conductive electrode portion 10 of the first circuit board
Is formed so as to enclose the electrode portion 10 formed by plating, so that it does not have an abrupt change in the shape of the solder and hardly concentrates stress, so that the reliability of bonding can be increased.
【図１】半導体素子を載せた第一回路基板の要部断面
図。FIG. 1 is a sectional view of a main part of a first circuit board on which a semiconductor element is mounted.
【図２】第一回路基板と第二回路基板を接合した要部断
面図。FIG. 2 is an essential part cross-sectional view in which a first circuit board and a second circuit board are joined.
【図３】第一実施例の工程説明の図面であり、第一回路
基板（フイルム）に穴を形成する工程の説明図。FIG. 3 is a drawing for explaining a step in the first embodiment, and is an explanatory view of a step of forming a hole in a first circuit board (film).
【図４】第一実施例の工程説明の図面であり、穴内にメ
ッキ生成する工程の説明図。FIG. 4 is a drawing of a process description of the first embodiment, and is an explanatory diagram of a process of generating plating in a hole.
【図５】第一実施例の工程説明の図面でありメッキ生成
の説明図。FIG. 5 is a drawing for explaining a process of the first embodiment, and is an explanatory diagram of plating generation.
【図６】第一実施例の工程説明の図面であり、メッキに
よる突起の生成の説明図。FIG. 6 is a drawing for explaining the steps of the first embodiment, and is an explanatory view of generation of projections by plating.
【図７】第一実施例の工程説明の図面であり、レジスト
剥離後の説明図。FIG. 7 is a drawing for explaining a step in the first embodiment, and is an explanatory view after resist is stripped.
【図８】第一実施例の工程説明の図面であり、第一回路
基板上に半導体素子を載せる説明図。FIG. 8 is a drawing of a process description of the first embodiment, and is an explanatory view of mounting a semiconductor element on a first circuit board.
【図９】第一実施例の工程説明の図面であり、第二回路
基板との接合のための導通部材２２の説明図。FIG. 9 is a drawing for explaining a step in the first embodiment, and is an explanatory view of a conductive member 22 for bonding to a second circuit board.
【図１０】第二実施例の説明図であり、メッキ生成した
電極部の上面の平坦化の説明図。FIG. 10 is an explanatory view of the second embodiment, and is an explanatory view of flattening the upper surface of an electrode portion formed by plating.
【図１１】第二実施例の説明図であり、第一回路基板の
説明図。FIG. 11 is an explanatory view of the second embodiment, and is an explanatory view of a first circuit board.
【図１２】第二実施例の説明図であり、第一回路基板に
半導体素子を載せる説明図。FIG. 12 is an explanatory view of the second embodiment, and is an explanatory view of mounting a semiconductor element on a first circuit board.
【図１３】第二実施例の説明図であり、はんだボール２
２を載せる説明図。FIG. 13 is an explanatory view of the second embodiment, showing solder balls 2;
FIG.
【図１４】第二実施例の説明図であり、半田ボールの合
金化の説明図。FIG. 14 is an explanatory view of the second embodiment, illustrating an alloying of solder balls.
【図１５】第三実施例の説明図であり、第三実施例の第
一回路基板の説明図。FIG. 15 is an explanatory view of the third embodiment, illustrating the first circuit board of the third embodiment.
【図１６】第三実施例の説明図であり、メッキ生成の説
明図。FIG. 16 is an explanatory view of the third embodiment, and is an explanatory view of plating generation.
【図１７】第三実施例の説明図であり、メッキ生成の説
明図。FIG. 17 is an explanatory view of the third embodiment, and is an explanatory view of plating generation.
【図１８】第三実施例の説明図であり、レジスト剥離後
の第一基板の説明図。FIG. 18 is an explanatory view of the third embodiment, which is an explanatory view of the first substrate after the resist is stripped.
【図１９】第三実施例の説明図であり、半導体素子を載
せる説明図。FIG. 19 is an explanatory diagram of the third embodiment, and is an explanatory diagram in which a semiconductor element is mounted.
【図２０】第三実施例の説明図であり、はんだボールの
合金化の説明図。FIG. 20 is an explanatory view of the third embodiment, and is an explanatory view of alloying a solder ball.
【図２１】第三実施例の説明図であり、合金化された導
通電極部を備える第一回路基板の説明図。FIG. 21 is an explanatory view of the third embodiment, and is an explanatory view of a first circuit board provided with an alloyed conductive electrode portion.
２ 第一回路基板 ２ａ 第一回路基板２に形成した貫通穴 ４ 第一回路基板２に設けた配線部 ６ レジスト ８ マスクレジスト １０ メッキ生成の導通電極部 １４ 半導体素子 １８ 樹脂封止部材 ２２ はんだボール Reference Signs List 2 first circuit board 2a through hole formed in first circuit board 2 4 wiring section provided in first circuit board 2 6 resist 8 mask resist 10 conductive electrode section formed by plating 14 semiconductor element 18 resin sealing member 22 solder ball
Claims (18)
二の回路基板を接続した半導体において、前記第一の回
路基板上の一方の面に電気接続配線部を設け、前記第一
の回路基板に、電気接続配線部が露出する穴が形成さ
れ、穴を埋め込むように電極部を生成し、該生成した電
極部は前記穴の他面側表面上から突出形成し、前記突出
形成した電極部上に導通部材を載置し、導通部材を介し
て前記第二の回路基板との電気的接続を行うようにした
ことを特徴とした半導体の接続構造。1. A semiconductor in which a first circuit board provided with an integrated circuit body is connected to a second circuit board, wherein an electric connection wiring portion is provided on one surface on the first circuit board, A hole for exposing an electrical connection wiring portion is formed in the circuit board, an electrode portion is generated so as to fill the hole, and the generated electrode portion protrudes from the other surface of the hole to form the protruding portion. A connection structure for a semiconductor, wherein a conductive member is mounted on the electrode portion and the electrical connection with the second circuit board is performed via the conductive member.
ことを特徴とした請求項１記載の半導体の接続構造。2. The semiconductor connection structure according to claim 1, wherein said conductive member has a ball shape.
該第一の基盤に配線部が露出する穴を形成し、前記配線
部を底面として前記穴内に電気導通部を生成し、該生成
した電気導通部は前記第一基板の他面側に突出させ、該
突出した電気導通部上に電極部材を配置し、電極部材を
介して第二の基板の電気導通部と電気接続させ、前記第
一又は第二の基板に半導体を接続するようにしたことを
特徴とした半導体の接続構造。3. A wiring portion is provided on the first surface side of the first substrate,
A hole through which a wiring portion is exposed is formed in the first substrate, an electric conduction portion is generated in the hole with the wiring portion serving as a bottom surface, and the generated electric conduction portion is projected to the other surface side of the first substrate. And disposing an electrode member on the protruding electrical conduction portion, electrically connecting the electrical conduction portion of the second substrate via the electrode member, and connecting a semiconductor to the first or second substrate. A semiconductor connection structure characterized by the following.
その突出面が平坦であることを特徴とした請求項３記載
の半導体の接続構造。4. The semiconductor connection structure according to claim 3, wherein the electrically conductive portion formed on the first substrate has a flat protruding surface.
出面に凹部を形成したことを特徴とした請求項３記載の
半導体の接続構造。5. The semiconductor connection structure according to claim 3, wherein a concave portion is formed on a protruding surface of the electric conduction portion generated on the first substrate.
特徴とした請求項３乃至５記載の半導体の接続構造。6. The semiconductor connection structure according to claim 3, wherein said electrode member has a ball shape.
ぐように回路配線部を配線して該配線部に集積回路体を
接続し、前記穴の開口側にメッキ材料で前記配線部との
電気的導通を保つ電極部を形成し、前記電極部に導通部
材を載せ、該導通部材を介して第二の回路基板の導通部
との電気的接続を行うようにしたことを特徴とした半導
体の接続構造。7. A circuit wiring portion is wired so as to cover the hole of the first circuit board having the hole formed therein, an integrated circuit body is connected to the wiring portion, and the wiring is formed of a plating material on the opening side of the hole. Forming an electrode portion for maintaining electrical continuity with the portion, placing a conductive member on the electrode portion, and electrically connecting to the conductive portion of the second circuit board via the conductive member. Semiconductor connection structure.
から突出形成されていることを特徴とした請求項７記載
の半導体の接続構造。8. The semiconductor connection structure according to claim 7, wherein said plating material is formed so as to protrude from a hole of said first circuit board.
記第一回路基板の一部の表面を覆うように形成したこと
を特徴とした請求項７記載の半導体の接続構造。9. The semiconductor connection structure according to claim 7, wherein said plating material is formed so as to project from said hole and cover a part of the surface of said first circuit board.
部材の前記集積回路体と電気接続する配線部の上部の前
記シート部材に穴を形成し、前記穴を電気メッキ材料を
埋め込んで前記配線部と電気的導通した導通部を前記シ
ート部材の他面側に表出させ、前記表出した導通部上に
ボール状導通部材を載せ、該導通部材を介して回路基板
の電気接続部と接続するようにしたことを特徴とした半
導体の接続構造。10. A hole is formed in the sheet member above a wiring portion of a resin material sheet member on which an integrated circuit body is mounted and electrically connected to the integrated circuit body, and the hole is filled with an electroplating material to form the wiring. A conductive portion electrically connected to the portion is exposed on the other surface side of the sheet member, a ball-shaped conductive member is placed on the exposed conductive portion, and connected to the electrical connection portion of the circuit board via the conductive member. A semiconductor connection structure characterized in that:
を特徴とした請求項１０記載の半導体の接続構造。11. The semiconductor connection structure according to claim 10, wherein said sheet member is a film.
第二の回路基板を接続するための半導体の接続方法は次
の工程を含む事を特徴とする； ａ．前記第一の回路基板上の前記集積回路体と接続する
電気配線部に穴を設ける工程、 ｂ．前記第一回路基板の前記電気配線部を底面として前
記穴内に電極部を埋め込み生成し、該電極部を第一回路
基板の他面側に突出形成する工程、 ｃ．前記突出形成した電極部上にボール状導通部材を載
せる工程、 ｄ．前記ボール状導通部材を介して前記第一回路基板と
前記第二の回路基板とを電気的に接続する工程。12. A semiconductor connection method for connecting a second circuit board to a first circuit board on which an integrated circuit body is mounted includes the following steps: a. Providing a hole in an electric wiring portion connected to the integrated circuit body on the first circuit board; b. Forming an electrode portion in the hole by using the electric wiring portion of the first circuit board as a bottom surface and projecting the electrode portion to the other surface side of the first circuit board; c. Placing a ball-shaped conductive member on the protruding electrode portion; d. Electrically connecting the first circuit board and the second circuit board via the ball-shaped conductive member.
上面を平坦処理する工程を含む事を特徴とした請求項１
２記載の半導体の接続方法。13. The method according to claim 1, further comprising a step of flattening an upper surface of the electrode portion generated on the first circuit board.
3. The method for connecting a semiconductor according to 2.
上面に凹部を形成する工程を含むことを特徴とした請求
項１２記載の半導体の接続方法。14. The method according to claim 12, further comprising the step of forming a concave portion on the upper surface of the electrode portion formed on the first circuit board.
板を電気接続するための半導体の接続方法は次の工程を
含むことを特徴とする； ａ．前記フイルム上に電気配線部を形成し、前記電気配
線部上のフイルム部分を除去して穴を形成する工程と、 ｂ．前記フイルム上の電気配線部を底面として前記穴内
をメッキ材料で埋め込んで該メッキ材料を介して前記電
気配線部の導通部を前記フイルムの他面側に表出させる
工程と、 ｃ．前記フイルムに集積回路体を載せ、前記電気配線部
と接続する工程と、 ｄ．前記導通部上に前記回路基板との電気接続のための
導通部材を載せる工程と、 ｅ．前記フイルムの貫通穴の前記メッキ材料と前記導通
部材を合金化させ、該導通部材の表面を略球形状にする
工程と、 ｆ．前記フイルム上の前記導通部材と前記回路基板の電
気接続部との電気的接続を行う工程。15. A method of connecting a semiconductor for electrically connecting a circuit board to a film having an integrated circuit body, comprising the following steps: a. Forming an electrical wiring portion on the film, removing the film portion on the electrical wiring portion to form a hole, b. A step of embedding the inside of the hole with a plating material with the electric wiring portion on the film as a bottom surface and exposing a conductive portion of the electric wiring portion to the other surface of the film via the plating material; c. Placing an integrated circuit body on the film and connecting to the electric wiring portion; d. Placing a conductive member on the conductive portion for electrical connection with the circuit board; e. Alloying the plating material in the through-hole of the film with the conductive member to make the surface of the conductive member substantially spherical, f. Making an electrical connection between the conductive member on the film and an electrical connection portion of the circuit board.
出面を平坦化する工程を含むことを特徴とした請求項１
５記載の半導体の接続方法。16. The method according to claim 1, wherein the exposed portion protrudes from the hole and includes a step of flattening a protruding surface.
6. The method for connecting a semiconductor according to 5.
むことを特徴とした請求項１５記載の半導体の接続方
法。17. The method according to claim 15, further comprising the step of forming a concave portion on the protruding surface.
イングした半導体素子と前記フイルム基板に、電気配線
部が露出した穴を形成し、露出した電気配線部からメッ
キ材料から成る電極部を前記フイルム基板表面より突出
させて形成し、前記突出電極部上にボール状導通部材を
接合させ、前記ボール状導通部材を回路基板の電極部と
接続させるようにしたことを特徴とした半導体デバイ
ス。18. An electric wiring portion on a film substrate and a semiconductor element bonded to the film substrate and a hole in which the electric wiring portion is exposed are formed in the film substrate, and the electrode portion made of a plating material is formed from the exposed electric wiring portion to the film substrate. A semiconductor device characterized by being formed so as to protrude from a surface, joining a ball-shaped conductive member on the protruding electrode portion, and connecting the ball-shaped conductive member to an electrode portion of a circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8868798A JPH11288973A (en) | 1998-04-01 | 1998-04-01 | Connection structure for semiconductor device, connection of semiconductor device, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8868798A JPH11288973A (en) | 1998-04-01 | 1998-04-01 | Connection structure for semiconductor device, connection of semiconductor device, and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11288973A true JPH11288973A (en) | 1999-10-19 |
Family
ID=13949760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8868798A Withdrawn JPH11288973A (en) | 1998-04-01 | 1998-04-01 | Connection structure for semiconductor device, connection of semiconductor device, and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11288973A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006073689A (en) * | 2004-09-01 | 2006-03-16 | Sony Corp | Manufacturing method of substrate and of semiconductor package |
| KR100999907B1 (en) | 2002-06-19 | 2010-12-13 | 신꼬오덴기 고교 가부시키가이샤 | Method of plugging through-holes in silicon substrate |
| JP2014168094A (en) * | 2004-06-25 | 2014-09-11 | Tessera Inc | Micro electronic component package and method therefor |
-
1998
- 1998-04-01 JP JP8868798A patent/JPH11288973A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100999907B1 (en) | 2002-06-19 | 2010-12-13 | 신꼬오덴기 고교 가부시키가이샤 | Method of plugging through-holes in silicon substrate |
| JP2014168094A (en) * | 2004-06-25 | 2014-09-11 | Tessera Inc | Micro electronic component package and method therefor |
| JP2006073689A (en) * | 2004-09-01 | 2006-03-16 | Sony Corp | Manufacturing method of substrate and of semiconductor package |
| JP4670284B2 (en) * | 2004-09-01 | 2011-04-13 | ソニー株式会社 | Substrate manufacturing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050607 |