JPH11288945A - Dielectric isolation semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device produced by a method, in which the time tstg for completing sweep-out of carries when a bipolar transistor is switched off. SOLUTION: This semiconductor device comprises a collector region 11 having a first conductivity-type semiconductor region, which is formed in a semiconductor layer and separated like islands, an insulator 12 embedded in a trench for isolation which is so formed as to surround the collector region 11, a base region 13 having a diffused layer with a conductivity type opposite to the first conductivity type formed on a part of the surface layer of the collector region 11, an emitter region 14 consisting of a first conductivity-type diffused region 13 formed on a part of the surface layer of the base region, a collector- extraction region 15, consisting of a second conductivity-type diffused region formed on a part of the surface layer of the collector region, a diffused region 13 formed so as to surround at least a part of the collector-extraction region and be given a potential equal to the base region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dielectric isolation type semiconductor device, and more particularly to a structure of a bipolar transistor in a semiconductor integrated circuit using a dielectric isolation method for element isolation.

[0002]

2. Description of the Related Art FIG. 8 shows SOI as a dielectric isolation method.
(Silicon on Insulator) An example of a planar pattern of a conventional NPN transistor using a substrate and trench processing is shown. 9A and 9B show an example of a cross-sectional structure along the line AA in FIG.

The NP shown in FIGS. 8 and 9 (a) and (b)
In the N-transistor, reference numeral 51 denotes a collector region composed of an N @-type semiconductor region having a relatively low impurity concentration, which is divided into a plurality of islands in a semiconductor layer formed on an insulating substrate, and 52 denotes a periphery of the collector region. Trenches (grooves) formed in the semiconductor layer so as to surround the trenches
An insulator (or polycrystalline silicon, etc.) buried therein, 53 is a base region composed of a P-type diffusion region formed in a part of the surface layer of the collector region, and 54 is one surface layer of the base region. An emitter region formed of an N-type diffusion region formed in the collector region; 55, a collector extraction region formed of an N-type diffusion region formed in a part of the surface layer of the collector region; 56, an emitter wiring contact region for the emitter region; 57 is a base wiring contact area for the base area, and 58 is a collector wiring contact area for the collector take-out area.

FIG. 9A shows a state where electrons e- are injected into the collector region 51 when the NPN transistor is in the ON state of the saturation region. In this case, in the saturation region of the NPN transistor, the PN junction between the base and the collector is biased in the forward direction.
Holes h + are also injected from base region 53 to collector region 51, and excess electrons and holes are present in collector region 51.

FIG. 9B shows a state in which carriers are extracted from the collector region when the NPN transistor switches off. In this case, the electrons e− accumulated in the collector region 51 during the operation in the saturated region are extracted to the collector extraction region 55 on the high potential side, and the holes h + are extracted to the base region 53 on the low potential side. The carrier region is depleted from the base region 53 toward the collector region 51 due to the absence of carriers in the collector region 51, so that the collector region 51 is turned off. Here, 59 represents a depletion layer.

FIG. 10 shows typical waveforms during the switching operation of the bipolar transistor of FIG. The switching operation includes a time tr from when the base current IB is turned on until the collector current Ic is completely stabilized, a time tstg from when the base current is turned off to when the collector current Ic starts to be cut off, and when the collector current Ic is turned off. It is divided into a time tf from the start to the end of the cut.

In this case, the time until the sweeping of the carrier from the collector region 51 is completed at the time of the switching-off appears at the time tstg, and the time tstg until the sweeping is completed cannot be shortened.

The reason is that, in a bipolar transistor in a semiconductor integrated circuit using the dielectric isolation method, when the saturation region is in the ON state, there is no depletion layer in the collector region 51 and the carrier accumulation region is wide.

On the other hand, a bipolar transistor in a conventional semiconductor integrated circuit using a junction isolation system for element isolation has a planar pattern as shown in FIG.
2 (a) and 2 (b), the depletion layer 89 extends from the element isolation P-type diffusion region 82 around the transistor, and the effective volume of the collector region 81 decreases. Since the region in which carriers accumulate when the saturation region is in the on state is narrow, the time tstg required to complete the sweeping out of carriers from the collector region 81 when switching off is short.

FIG. 11 and FIGS. 12 (a) and 12 (b)
In the NPN transistor using the junction isolation method for inter-element insulation, a collector region 80 is a P-type semiconductor substrate, and a collector region 81 is an N- type semiconductor region having a relatively low impurity concentration and divided into islands in the surface layer of the substrate. Reference numeral 90 denotes a buried layer made of an N + type semiconductor region having a relatively high impurity concentration buried in the bottom of the collector region 81, and 82 is formed in a surface layer of the substrate so as to surround the periphery of the collector region 81. An element isolation region composed of a P-type semiconductor region, 83
Is a base region, 84 is an emitter region, 85 is a collector extraction region, 86 is an emitter wiring contact region, 87
Is a base wiring contact area, and 88 is a collector wiring contact area. Then, the depletion layer 89 is greatly expanded in the vicinity of the element isolation P-type diffusion region 82.

[0011]

As described above, the bipolar transistor in the conventional dielectric isolation type semiconductor device has a wide carrier accumulation region in the collector region and a time tsg until the carrier is completely swept out at the time of switching off. There was a problem that can not be shortened.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and the time required for the carrier accumulation region in the collector region of the bipolar transistor to become narrower and the carrier to be completely swept when the bipolar transistor is switched off is completed. An object of the present invention is to provide a dielectric isolation type semiconductor device capable of shortening tstg.

[0013]

According to the present invention, there is provided a dielectric isolation type semiconductor device, comprising: a collector region comprising a plurality of semiconductor regions of a first conductivity type, each of which is divided into islands in a semiconductor layer; A trench for element isolation formed in the semiconductor layer so as to surround the periphery of the semiconductor layer, an insulator buried in the trench, and the first conductivity type formed in a part of a surface layer of the collector region. A base region formed of a diffusion region of a second conductivity type having a reverse conductivity type, an emitter region formed of a diffusion region of the first conductivity type formed in a part of a surface layer of the base region, and the collector region A collector extraction region formed of a diffusion region of the first conductivity type formed in a part of the surface layer portion of the first region, and formed so as to surround at least a part of a periphery of the collector extraction region;
And a diffusion region of the second conductivity type to which the same potential as the base region is applied.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows, as a first embodiment of a dielectric isolation type semiconductor device of the present invention, an example of a plane pattern of an NPN transistor in which inter-element insulation is performed using a SOI substrate and trench processing.

FIG. 2 shows an example of a cross-sectional structure along the line CC in FIG. In the NPN transistor shown in FIGS. 1 and 2, reference numeral 20 denotes an insulating substrate, for example, an insulating film such as an oxide film 10a formed on a silicon substrate 10 for a base substrate.

Reference numeral 11 denotes a collector region formed of an N @-type semiconductor region having a relatively low impurity concentration, which is divided into a plurality of islands in a semiconductor layer formed on the insulating substrate 20, and 12 denotes a collector region. An insulator (or polycrystalline silicon or the like) embedded in an element isolation trench (groove) formed in the semiconductor layer so as to surround the periphery. Reference numeral 10b denotes an insulating film such as an oxide film formed on the inner surface of the trench.

Reference numeral 13 denotes a base region composed of a P-type diffusion region formed in a part of the surface layer of the collector region. Reference numeral 14 denotes N which has a relatively high impurity concentration formed in a part of the surface layer of the base region 13. An emitter region composed of a + type diffusion region,
Reference numeral 13a denotes a base extraction region formed of a P + -type diffusion region having a relatively high impurity concentration formed in a part of the surface layer of the base region. Reference numeral 15 denotes an impurity concentration formed in a part of the surface layer of the collector region 11. Is a collector extraction region in the form of, for example, a square pattern formed of a relatively high N + type diffusion region. In this case, the base region 13 is formed so as to partially surround the collector extraction region 15 in, for example, a square pattern.

Further, 16 is a contact region of the emitter wiring connected to the emitter region 14, 17 is a contact region of the base wiring connected to the base region, and 18 is connected to the collector extraction region 15. This is a contact region for the collector wiring.

When the NPN transistor having the above structure is in the ON state of the saturation region, electrons e- are injected from the emitter region 14 to the collector region 11, but the PN junction between the base and the collector is biased in the forward direction. Therefore, holes h + are also injected from base region 13 to collector region 11, and excessive electrons and holes are present in collector region 11 (particularly in a region from below emitter region 14 to below collector extraction region 15). It is in a state to do.

FIG. 2 shows a state in which carriers e− and h + are extracted from the collector region 11 when the NPN transistor is switched off.
In the structure of FIG. 1, the voltage applied to the PN junction between the base and the collector when the transistor is switched off is biased in the reverse direction, and the impurity concentration is low in the two semiconductor regions forming the collector-base junction. More depletion layers 19 extend in one collector region 11.

As a result, during the operation in the saturation region, the excess carriers (e−) accumulated in the collector region 11 are pushed out (extracted) from the collector region 11 to the collector extraction region 15 on the high potential side. .

In this case, since a part of the base region 13 is formed so as to surround the periphery of the collector extraction region 15, not only the lower portion of the base region 13 but also the periphery of the collector extraction region 15 is surrounded. Since the depletion layer 19 extends, excess carriers accumulated in the collector region 11, particularly in a region below the collector extraction region 15, are pushed out to the collector extraction region 15.

In other words, since the effective collector region at the time of carrier sweeping is small, the base current I
The time tstg from when B is turned off to when the collector current Ic starts to be cut is shortened.

Then, the carrier is lost in the collector region 11 and depleted from the base region 13 toward the collector region 11, whereby the collector region 11 is turned off. As a result, the time from when the base current is turned off to when the collector current Ic ends is shortened, and the switching-off operation is speeded up.

The NPN of the conventional example having the structure shown in FIG.
Even in the case of a transistor, the base region 53 to the collector region 5
1, but the base region 53 is not formed so as to surround the periphery of the collector extraction region 55. Therefore, the right corner of the collector region 51 (with the base region 53 across the collector extraction region 55). Is the opposite area)
Carrier was not easily swept out, and the time tstg became long.

The pattern shape of the base region 13 surrounding the collector extraction region 15 is not limited to a continuous shape as shown in FIG. 1, but may be, for example, as shown in FIG. 5 (a) or (b). Even if a part of the pattern is missing such that the depletion layer 19 is continuously generated, the above-described effect can be obtained.

The distance between the outer edge of the collector extraction region 15 and the inner edge of the base region 13 surrounding the collector extraction region 15 has an inverse relationship to the breakdown voltage and operating speed of the NPN transistor. For example, it is desirable to carry out as shown in FIG.

The structure of the NPN transistor shown in FIG.
Compared to the structure of the NPN transistor shown in FIG. 1, the collector extraction region 15 and the base region 13 surrounding the collector extraction region 15 are formed in a circular pattern, respectively, and are otherwise the same.

According to the structure of the NPN transistor shown in FIG. 6, the distance between the outer edge of the collector extraction region 15 and the inner edge of the base region 13 surrounding the collector extraction region 15 is equal over the entire circumference. The operation speed characteristics are improved.

FIG. 3 shows, as a second embodiment of the dielectric isolation type semiconductor device of the present invention, an example of a plane pattern of an NPN transistor in which inter-element insulation is performed using a SOI substrate and trench processing. .

FIG. 4 shows an example of a sectional structure taken along line DD of FIG. The NPN transistor shown in FIG.
Compared to the NPN transistor described above with reference to FIG.
Further, a diffusion region 30 of the same conductivity type (P type in this example) and a deeper region than the base diffusion region is formed in the outer peripheral portion of the base diffusion region 13, and the other portions are the same, and are the same as those in FIG. The same reference numerals are given.

When the P-type diffusion region 30 is formed as described above, when the transistor is switched off, as shown in FIG. 4, the region of the depletion layer 19 in the peripheral region in the collector region 11 is further expanded, and the carrier is increased. Since the effective collector area at the time of sweeping is further reduced, the switching-off operation becomes faster.

In addition, depletion layer 1 formed in collector region 11 so as to surround collector take-out region 15 is formed.
Since the region 9 is deeper in the depth direction, the collector region 1 is larger than the NPN transistor having the structure shown in FIG.
Even when the thickness of 1 is large, excess carriers accumulated in the collector region 11, particularly in a region below the collector extraction region 15, can be easily pushed out to the collector extraction region 15.

The structure of the NPN transistor shown in FIG.
Compared to the structure of the NPN transistor according to the second embodiment shown in FIG. 3, the positions of the base extraction region 13a and the emitter region 14 in the base region 13 are interchanged, The difference is that the diffusion region 30 is a region including the base extraction region 13a and is formed in a wide region until approaching the emitter region 14, and the other is the same.

According to the structure of the NPN transistor shown in FIG. 7, if the P-type diffusion region 30 is a region including the base extraction region 13a and formed in a wide region until it approaches the emitter region 14, When the transistor is switched off, the region of the depletion layer expands to the vicinity of the region below the emitter region 14 in the collector region 11, and the effect of pushing out excess carriers accumulated below the emitter region 14 is improved.

[0036]

As described above, according to the present invention, there is provided a dielectric isolation type semiconductor device capable of shortening the time tstg required for completing the carrier sweeping when the bipolar transistor is switched off. can do.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a plane pattern of an NPN transistor according to a first embodiment of a dielectric isolation type semiconductor device of the present invention.

FIG. 2 is a diagram illustrating an example of a cross-sectional structure taken along line CC in FIG. 1 for explaining movement of carriers when a transistor is on and when switching is off.

FIG. 3 is a view showing an example of a plane pattern of an NPN transistor according to a second embodiment of the present invention.

FIG. 4 is a view showing an example of a cross-sectional structure along the line DD in FIG. 3;

FIG. 5 is a diagram showing a first modification of the plane pattern of the NPN transistor of FIG. 1;

FIG. 6 is a diagram showing a modification 2 of the plane pattern of the NPN transistor of FIG. 1;

FIG. 7 is a view showing a modification of the planar pattern of the NPN transistor of FIG. 3;

FIG. 8 is a diagram showing an example of a plane pattern of an NPN transistor of a conventional dielectric isolation type semiconductor device.

FIG. 9 is a view showing an example of a cross-sectional structure along the line AA in FIG. 8;

FIG. 10 is a view showing a typical waveform at the time of a switching operation of the bipolar transistor of FIG. 8;

FIG. 11 is a diagram showing an example of a plane pattern of an NPN transistor of a conventional junction separation type semiconductor device.

FIG. 12 is a diagram showing an example of a cross-sectional structure along the line BB in FIG. 11;

[Explanation of symbols]

 11: collector region, 12: insulator buried inside the element isolation trench, 13: base region, 13a: base extraction region, 14: emitter region, 15: collector extraction region, 19: vacancy layer

Claims (9)

[Claims] A collector region formed of a plurality of semiconductor regions of a first conductivity type, each of which is divided into islands in the semiconductor layer; and an element isolation formed in the semiconductor layer so as to surround a periphery of the collector region. A trench embedded in the trench; an insulator buried in the trench; and a first trench formed in a part of a surface layer of the collector region.
A base region formed of a diffusion region of a second conductivity type having a conductivity type opposite to the conductivity type; an emitter region formed of a diffusion region of the first conductivity type formed in a part of a surface layer of the base region; The first region formed on a part of the surface portion of the collector region;
A collector extraction region formed of a conductive diffusion region; and a second conductivity type diffusion region formed so as to surround at least a part of the periphery of the collector extraction region and to which a potential equal to that of the base region is applied. A dielectric isolation type semiconductor device characterized by the above-mentioned. 2. The dielectric isolation type semiconductor device according to claim 1, wherein said diffusion region is continuous with said base region and is formed so as to surround the entire periphery of said collector extraction region. Body-separated semiconductor device. 3. The dielectric isolation type semiconductor device according to claim 1, wherein said diffusion region is formed so as to be continuous with said base region and to surround a part of a periphery of said collector extraction region. Dielectric isolation type semiconductor device. 4. The dielectrically isolated semiconductor device according to claim 1, wherein said diffusion region is formed separately from said base region. 5. The dielectric isolation type semiconductor device according to claim 1, wherein the base region and the diffusion region have a higher impurity concentration than the collector region. Body-separated semiconductor device. 6. The dielectric isolation type semiconductor device according to claim 1, further comprising: a second conductive layer formed deeper than the base region in an outer peripheral portion of the base region and the diffusion region. 1. A dielectric isolation type semiconductor device comprising a diffusion region of a die type. 7. The dielectric isolation type semiconductor device according to claim 1, further comprising: a part of a surface layer of said base region, said collector region being interposed between said collector region and said emitter region. A base isolation region formed on the opposite side and comprising the first conductivity type diffusion region. 8. The dielectric isolation type semiconductor device according to claim 7, further comprising a diffusion region of the second conductivity type formed deeper than the base region in an outer peripheral portion of the base region including a base extraction region. And a dielectric isolation type semiconductor device. 9. The dielectric isolation type semiconductor device according to claim 1, wherein said semiconductor layer is a silicon layer formed on an insulating substrate. Type semiconductor device.