JPH11284797A - Linear image sensor ic, ic mounting substrate and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image sensor IC which reduces a manufacturing price and can make an extremely thin chip by forming an LOCOS separation layer between the edge of the main scanning direction of a linear image sensor IC which is the nearest to the row of photodetective elements and the light receiving part of the photodetective elements. SOLUTION: The LOCOS separation layer is formed between the edge of the main scanning direction of the linear image sensor IC which is the nearest to the row of the photodetective elements and the light receiving part of the photodetective elements. This image sensor IC forms a P-base diffusion layer 112, a P + diffusion layer 113, an N + diffusion layer 114, an LOCOS oxide film 115, etc., on an N-silicon substrate 111. The layer 114 is fixed to a power source voltage through AL 117 to stabilize the potential of the substrate 111 being the collector region of a phototransistor. An intermediate insulating layer 118, etc., is formed on the layer 113. A distance L between a chip edge 120 and the layer 112 can be made shorter than 40 μm by this structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-dimensional image sensor IC or an IC for thermal transfer printing which receives reflected light from a light-irradiated original and converts it into an electric signal.
It is applied to an image reading apparatus such as X. Also,
The present invention relates to an IC mounting board on which the one-dimensional image sensor IC or the IC for thermal transfer printing is mounted and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 2 shows a block diagram of a contact type one-dimensional image sensor IC2 used in a conventional facsimile reading apparatus. As shown in FIG. 2, a phototransistor row 21 in which a plurality of phototransistors having dimensions one-to-one corresponding to a document in the scanning direction are arranged in a straight line, and the phototransistor row 21 is similarly arranged in parallel in the scanning direction. , And a scanning circuit array 3 including a plurality of shift registers for sequentially switching the respective switching transistors are elongated and arranged in parallel in the scanning direction. The driving circuit 4 for moving the scanning circuit is arranged between pads which are external electric extraction terminals.

The above-described contact type phototransistor one-dimensional image sensor is disclosed in Japanese Patent Laid-Open No. 61-12417.
No. 1. Further, there is a contact type image sensor head as an IC mounting substrate on which the ICs are arranged one-dimensionally. FIG. 38C is a perspective view of the image sensor head. A plurality of image sensor ICs 2 are provided on the surface of the mounting board 6 in a straight line. Image sensor IC
The signal is supplied to the wiring on the substrate by a wire bond 23. The image sensor head is manufactured by the following method.

As shown in FIG. 38A, an image sensor IC 2 is formed on the surface of a silicon wafer 11 in a matrix. Thereafter, the electrical characteristics of the IC are measured using a tester, and bad marks 12 are marked on defective products. Next, the silicon wafer 1 is cut along the scribe line to separate each IC. Next, only non-defective products are selected and FIG.
It is arranged on the tray 13 as shown in FIG. Next, FIG.
As shown in (c), the components are sequentially arranged on the surface of the mounting substrate 6 from the tray 13 and bonded to complete.

FIG. 40 is a plan view of an IC arranged on an IC mounting board. The IC 2 has four or more pads 5 for power supply, signal supply and output terminals. In addition, the light receiving elements 32 of the same shape, each of which is composed of a phototransistor or a photodiode, are periodically arranged in plural numbers along the length direction of the chip. The light receiving elements 32 are provided one-dimensionally at a reading pitch cycle along the scanning direction.
The charge stored in the light receiving element is output from the output terminal in order from the leftmost light receiving element. As can be seen from FIG. 40, the rows of the light receiving elements 32 and the rows of the pads 5 are arranged separately.

FIG. 70 is a plan view (FIG. 70) of a multi-chip type image sensor of a facsimile image reading unit.
(A)) and sectional drawing (FIG. 70 (b)). A plurality of image sensor ICs 2 having a length of about 8 mm are linearly and continuously arranged on the surface of the substrate 14 on which the wiring is printed. A4
In the case of reading paper of a size in close contact, it is necessary to arrange a plurality of sheets by the width of A4 size paper. Electrical connection between the substrate 14 and each of the image sensor ICs 2 is made by bonding leads 23 as shown in FIG. Image sensor IC
2 has a very narrow shape of about 0.6 mm. In the image sensor IC2, a photosensor is formed along the length of the IC at a reading cycle in the length of the IC.

[0007] The thermal head of the facsimile output section has the same configuration. In the case of a thermal head, the thermal head driver ICs are arranged like the image sensor IC2. In the case of an image sensor, it is necessary that the respective ICs are arranged with almost no separation. However, in the case of a thermal head, the ICs are arranged substantially linearly at a certain interval. In the case of a thermal head, a resistor for heat sensitivity is provided on the surface of the substrate 14, and a current flows through each resistor via wiring on the substrate 14 and a bonding lead. Resistance is about 64 pieces / 8mm
It is provided in a linear shape with a density of 2. The thermal paper is discolored by Joule heat and printed out. Therefore, each driver IC has 64 driver transistors.
C are provided along the length direction. Each driver transistor is provided with an output pad which is electrically connected to the driver transistor. Therefore, the output pad is about 8m
64 ICs are bonded to the m ICs at intervals of about 10 μm along the length direction of the ICs.

[0008]

However, in such a one-dimensional image sensor, it is difficult to reduce the cost because the chip size cannot be simply reduced as in an ordinary memory IC. That is, the chip length in the scanning direction cannot be reduced because it must be the same as the length of the document. Further, the chip width in the scanning direction and the vertical direction can be reduced to only about 0.7 mm because the sensor, the switch, the scanning circuit, and the driving circuit are all arranged in parallel.

Further, in such an IC mounting board,
There is a problem that cost reduction is difficult because the length of the IC cannot be shortened in principle. When the width of the IC is reduced, the size of the bad mark is large and the alignment accuracy is low. Further, since the IC has a generally planar shape, it cannot be mounted on a cylindrical mounting substrate.

Further, in such a method of manufacturing an IC mounting board, when testing the electrical characteristics of the IC, it is impossible to measure two chips at a time in order to reduce the manufacturing cost of the IC. That is, when two adjacent ICs are simultaneously probed and tested for two chips at the same time in the direction in which the pixels of the ICs are arranged and in the vertical direction, the ICs are all arranged in the same direction. In this case, uniform light cannot be applied to the light receiving element array due to the shadow of the probing needle. Therefore, accurate pass / fail judgment cannot be made, and it is difficult to test two chips simultaneously.

In the case of an image sensor IC,
The sensitivity of the light receiving element varies within the silicon wafer. This is considered to be caused by non-uniformity of heat distribution in the wafer surface in the IC manufacturing process and non-uniformity of the thickness of various insulating films. Therefore, the sensitivity tends to change continuously in the wafer.
Therefore, if the distance between the light receiving elements on the wafer is short, the sensitivity difference may be small, and if the distance is long, the sensitivity difference may be large. For example, in FIG. 40, assuming that the sensitivity becomes higher as going to the right, if ICs adjacent in the direction perpendicular to the direction in which the light receiving elements of the IC 2 are arranged are arranged on the mounting board 6 in FIG. FIG. 44 shows the output when uniform light is irradiated. FIG. 44 shows output waveforms of a conventional image sensor head, in which the number of IC chips is six. Since the adjacent IC chips have the same orientation on the wafer, the output slope always rises to the right.
Therefore, there is an output step at the connection portion of the chip. In other words, the sensitivity has changed abruptly, and the output must be corrected for each bit. As a result, there has been a problem that an applied product of this image sensor, such as a facsimile, cannot be reduced in price.

Further, when the width of the IC is reduced, the size of the bad mark is large and the alignment accuracy is low.

[0013] Further, as the width of the IC is reduced, as a problem in mounting the IC, there have been the following problems in a conventional image sensor and a multi-chip electronic device such as a thermal head. (1) When the width of the IC is made very thin, the supporting strength is reduced.

(2) If the width of the IC is made much smaller,
Handling becomes difficult. (3) If the width of the IC is made much smaller, it becomes difficult to make an electrical connection with the substrate. That is, since it is more difficult to make the width of the IC much smaller than (1), (2), and (3), the cost of the IC cannot be reduced, and as a result, the cost of the multi-chip electronic device can be reduced. was difficult.

Accordingly, an object of the present invention is to provide an image sensor IC which can be manufactured at a low production cost and can be formed into an extremely fine chip in order to solve the conventional problems as described above. Also,
It is an object of the present invention to provide an IC mounting substrate that reduces manufacturing costs and allows non-planar substrates.

It is another object of the present invention to provide an IC mounting substrate having a small output step at a connection portion of a chip. Another object of the present invention is to provide a low-cost electronic device that can be mounted on an IC having a width smaller than the thickness of the IC and a width smaller than 0.35 mm.

[0017]

Means for Solving the Problems In order to solve the above problems, the present invention provides a method for manufacturing an image sensor IC and an IC mounting board as follows. (1) In a linear image sensor IC including a plurality of switch circuits connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, the linear image sensor IC is closest to the row of the light receiving elements. An edge in the main scanning direction of the linear image sensor IC;
A linear image sensor IC is characterized in that a LOCOS separation layer is formed between the light receiving portions of the light receiving elements.

(2) The linear image sensor IC according to (1), wherein the distance L between the edge of the linear image sensor IC and the light receiving portion of the light receiving element is 40 μm or less. (3) In a linear image sensor IC including a plurality of switch circuits respectively connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, the linear image sensor IC is closest to the row of the light receiving elements. An edge in the main scanning direction of the linear image sensor IC;
A linear image sensor IC is characterized in that no light-shielding layer such as AL is formed between the light-receiving portions of the light-receiving elements.

(4) The linear image sensor IC according to (3), wherein the sum of the distance L and the width of the light receiving section in the sub-scanning direction is equal to or less than the distance between adjacent light receiving elements. (5) In a linear image sensor IC including a plurality of switch circuits serially connected to a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, a switch is provided between adjacent light receiving elements. A linear image sensor IC is characterized in that at least a part of the circuit is arranged.

(6) In a linear image sensor IC comprising a plurality of switch circuits respectively connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, the light receiving of the light receiving elements A linear image sensor IC is characterized in that the region is elongated in a plane with respect to the main scanning direction.

(7) In a linear image sensor IC including a plurality of switch circuits connected in series with a plurality of phototransistors, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, the linear image sensor IC includes a plurality of phototransistors. A linear image sensor IC comprising a collector electrode disposed between base regions of transistors.

(8) An image sensor circuit including a plurality of switch circuits connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit is formed on the chip surface. In the linear image sensor IC, the relationship between the thickness Z, the length X in the scanning direction, and the width Y of the linear image sensor IC is Y ≦ Z.
<X: a linear image sensor IC characterized by being
And

(9) The linear image sensor IC according to (8), wherein Y ≦ 350 μm. (10) In a linear image sensor IC including a plurality of switch circuits serially connected to a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, scanning is performed between adjacent light receiving elements. A linear image sensor IC is characterized in that at least a part of the circuit is arranged.

(11) The linear image sensor IC according to (10), wherein the area of the light receiving element is elongated in a plane with respect to the scanning direction. (12) The linear image sensor IC according to (10), wherein the light receiving element is a phototransistor and a collector electrode is arranged between the base regions of the adjacent phototransistors.

(13) The linear image sensor IC according to (10), wherein the relationship among the thickness Z, the length X in the scanning direction, and the width Y of the linear image sensor IC is Y ≦ Z <X.
And (14) Y ≦ 350 μm (1)
3) The linear image sensor IC was used.

(15) In a linear image sensor IC comprising a plurality of switch circuits respectively connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, an adjacent light receiving element A linear image sensor IC is characterized in that at least a part of the switch circuit and the scanning circuit is disposed between them.

(16) The linear image sensor IC according to (15), wherein the area of the light receiving element is elongated in a plane with respect to the scanning direction. (17) The linear image sensor IC according to (15), wherein the light receiving element is a phototransistor and a collector electrode is arranged between base regions of adjacent phototransistors.

(18) The linear image sensor IC according to (15), wherein the relationship among the thickness Z, the length X in the scanning direction, and the width Y of the linear image sensor IC is Y ≦ Z <X.
And (19) Y ≦ 350 μm (1)
8) The linear image sensor IC was used.

(20) In a linear image sensor IC comprising a plurality of switch circuits connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, the light receiving element is " And a linear image sensor IC characterized by being disposed adjacent to a switch circuit and a scanning circuit.

(21) The linear image sensor IC according to (20), wherein the relationship among the thickness Z, the length X in the scanning direction, and the width Y of the image sensor IC is Y ≦ Z <X. (22) Y ≦ 350 μm (2)
The linear image sensor IC of 1) was used.

(23) In a linear image sensor IC comprising a plurality of switch circuits connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit, the light receiving element has a concave shape. Thus, a linear image sensor IC is provided which is arranged adjacent to the switch circuit and the scanning circuit.

(24) The linear image sensor IC according to (23), wherein the relationship among the thickness Z, the length X in the scanning direction, and the width Y of the image sensor IC is Y ≦ Z <X.
And (25) Y ≦ 350 μm (2)
4) The linear image sensor IC was used.

(26) A linear image sensor circuit comprising a plurality of switch circuits connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit is formed on the chip surface. In the linear image sensor IC, the length Xp of the pad electrode in the main scanning direction of the linear image sensor IC,
The length Yp of the pad electrode in the sub-scanning direction of the linear image sensor IC is Yp = <80 μm, and Xp> Yp.

(27) A linear image sensor circuit comprising a plurality of switch circuits connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit is formed on the chip surface. In the linear image sensor IC, the tip of the probe that comes into contact with the pad electrode for inspection is made to enter substantially parallel to the main scanning direction of the linear image sensor IC, and the main scanning of the scar of the pad electrode attached by the tip of the probe is performed. An image sensor IC characterized in that the length in the direction is longer than the length of the scar in the sub-scanning direction.

(28) A plurality of photoelectric conversion elements arranged linearly on a semiconductor substrate for reading image information, and an input terminal connected to the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. In a linear image sensor including a plurality of connected switching elements and a scanning circuit that drives a control terminal of the switching element, an output terminal of the switching element is connected to a common line, and the common line is further connected to an input terminal of a reset gate. , And the output terminal of the reset gate is connected to the reset power supply terminal.

(29) A plurality of photoelectric conversion elements for reading image information arranged linearly on a semiconductor substrate, and an input terminal for the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. In a linear image sensor composed of a plurality of connected switching elements and a scanning circuit that drives a control terminal of the switching element, an output terminal of the switching element is connected to an input terminal of the reset gate, and an output terminal of the reset gate is connected to the output terminal of the reset gate. Connect to the reset power supply terminal, drive the scanning circuit with a clock pulse of 1 / fCK second cycle, synchronize with the control of the switching element, control the reset gate, read out the signal from the photoelectric conversion element, and output the signal from the photoelectric conversion element. A linear image sensor wherein the terminal is fixed at a reset potential for 1 / fCK seconds or more. It was.

(30) A plurality of photoelectric conversion elements for reading image information arranged linearly on a semiconductor substrate, and an input terminal connected to the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. In a linear image sensor including a plurality of connected switching elements and a scanning circuit that drives a control terminal of the switching element, the scanning circuit is driven by a clock pulse having a period of 1 / fCK seconds,
Inputting data of 2 / fCK seconds or more to a scanning circuit, synchronizing with control of a switching element, controlling a reset gate, reading a signal from a photoelectric conversion element, and keeping a conduction state of the switching element longer than a reading period. The feature was a linear image sensor.

(31) A plurality of photoelectric conversion elements for reading image information arranged linearly on a semiconductor substrate, and an input terminal connected to the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. In a linear image sensor including a plurality of connected switching elements and a scanning circuit that drives a control terminal of the switching element, the output terminals of the switching elements are connected to a common line, and a plurality of common lines are provided. The common line is connected to the input terminal of the reset gate, the output terminal of the reset gate is connected to the reset power supply terminal, and the switching element changes from non-conductive to conductive state, and the output terminal of the photoelectric conversion element during reading is performed. The potential of the common lines other than the common line which is in a conductive state with the potential of the common line is fixed.

(32) In an IC mounting board in which ICs are repeatedly provided one-dimensionally on the surface of the mounting board,
The IC is an IC mounting board characterized in that it is elongated by repeating a plurality of light receiving elements or transistors one-dimensionally and that the width of the IC is 0.4 mm or less.

(33) In an IC mounting board in which ICs are repeatedly provided one-dimensionally on the surface of the mounting board,
The IC is an IC mounting substrate characterized in that the IC is formed to be elongated by repeating a plurality of light receiving elements or transistors one-dimensionally, and that the width of the IC is formed smaller than the thickness.

(34) An IC mounting board comprising a step of repeatedly forming a plurality of ICs in a matrix on the surface of a silicon wafer, a step of cutting the silicon wafer, and a step of one-dimensionally arranging the ICs on the mounting board. Production method. (35) A step of repeatedly forming a plurality of ICs in a matrix on the surface of the silicon wafer, a step of bonding a tape to the back surface of the silicon wafer, a step of cutting the silicon wafer, and one-dimensionally attaching the IC to a mounting substrate. And an arranging step.

(36) The method for manufacturing an IC mounting substrate according to (35), wherein the adhesive strength of the tape to the silicon wafer is controlled by irradiation with ultraviolet rays. (37) A step of repeatedly forming a plurality of ICs in a matrix on the surface of a silicon wafer, and measuring electrical characteristics of the ICs and storing data of the electrical characteristics in an electrically readable manner in accordance with the coordinates of the matrix. A method of manufacturing an IC mounting board, comprising: a probe test step of writing into a means, a step of cutting a silicon wafer, and a step of one-dimensionally arranging ICs sequentially selected in accordance with data in the storage means on a mounting board. .

(38) From the step of repeatedly forming a plurality of ICs in a matrix on the surface of a silicon wafer, the step of a probe test for measuring the electrical characteristics of the ICs, and the step of spatially separating the ICs by cutting the silicon wafer In the method of manufacturing an IC, when the IC is formed on the surface of the silicon wafer, the ICs adjacent to each other in the direction in which the light receiving elements of the IC are arranged and in the vertical direction are formed so as to have a point-symmetric relationship with each other. An IC manufacturing method was adopted.

(39) In the probe test step, I
Two ICs that are vertically adjacent to the direction in which
An IC manufacturing method is characterized in that probing and testing are performed simultaneously for each chip.

(40) In a method of manufacturing an IC mounting substrate comprising a step of one-dimensionally arranging ICs on the mounting substrate, the ICs which are adjacent to each other in a direction perpendicular to the direction in which the light receiving elements of the ICs are arranged on the surface of the silicon wafer are mutually separated. A method of manufacturing an IC mounting board characterized by being arranged adjacent to each other.

(41) In a silicon wafer on which a plurality of linear image sensor ICs are repeatedly formed in a matrix, the ICs adjacent to each other in the direction in which the light receiving elements of the ICs are arranged and in the vertical direction are formed so as to have a point symmetrical relationship with each other. A silicon wafer characterized by having been subjected to the above.

(42) A multi-chip in which a linear image sensor IC in which a plurality of light receiving elements are arranged one-dimensionally and a plurality of chips are arranged on a mounting substrate at substantially equal intervals in the arrangement direction of the light receiving elements. In the linear image sensor of the system, the linear image sensor IC has a bidirectional scanning function.

(43) A multi-chip in which a plurality of light receiving elements are arranged one-dimensionally and a plurality of chips are arranged on a mounting substrate at substantially equal intervals in the arrangement direction of the light receiving elements. In the linear image sensor of the system, the linear image sensor IC has a bidirectional scanning function, and one-chip linear image sensor IC of at least one pair of linear image sensor ICs adjacent to each other is paired. Linear image sensor IC
The linear image sensor is characterized in that the linear image sensor is arranged to be rotated by 180 degrees on the plane of the mounting substrate.

(44) The method of manufacturing a multi-chip linear image sensor according to (42), wherein the linear image sensor IC is cut out from a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix. From above, at least one pair of the linear image sensor ICs which are adjacent in the vertical direction to the arrangement direction in which the light receiving elements are arranged or in the vicinity in the vertical direction are cut out and arranged so as to be adjacent to each other, and at least one of the pairs is arranged.
The linear image sensor IC of one chip of the pair is arranged to be rotated by 180 degrees on the plane of the mounting substrate with respect to the other linear image sensor ICs of the pair.
2) A method for manufacturing a linear image sensor.

(45) In the method for manufacturing a multi-chip linear image sensor according to (43), the linear image sensor IC is cut out from a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix, and
(43) The linear image sensor IC rotated by 0 degrees is a linear image sensor IC that is vertically adjacent to or vertically adjacent to the arrangement direction of the light receiving elements from the silicon wafer. A method for manufacturing a linear image sensor was adopted.

(46) In the linear image sensor IC of (43), the input / output terminals including the power supply of the linear image sensor IC are arranged along the line of the light receiving elements and sandwich the light receiving elements. (43) The linear image sensor according to (43).

(47) In the multi-chip type linear image sensor of (42), the linear image sensor IC is cut out from a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix. At least one or more pairs of the linear image sensor ICs which are adjacent to each other in the vertical direction with respect to the arrangement direction in which the elements are arranged or which are close to each other in the vertical direction are cut out and arranged so as to be adjacent to each other. This one-chip linear image sensor IC is one chip
Linear image sensor IC that is arranged by rotating by 80 degrees
(42) The linear image sensor according to (42), wherein the scanning direction is also reversed.

(48) In the manufacturing method of (43), wherein the linear image sensor IC is cut out from a silicon wafer having a plurality of linear image sensor ICs arranged in a matrix and the multi-chip type linear image sensor of (43) is manufactured, The linear image sensor IC that is rotated by an angle is a linear image sensor IC that is adjacent to or vertically adjacent to the arrangement direction of the light receiving elements from the silicon wafer in the vertical direction.
(43) is a linear image sensor characterized in that the scanning directions are reversed.

(49) A reading means comprising a linear image sensor IC in which a plurality of light receiving elements are arranged one-dimensionally and a plurality of chips arranged on a mounting substrate at substantially equal intervals in the arrangement direction of the light receiving elements. A color linear image sensor unit comprising a multi-chip type linear image sensor and color separation means including a light source and a lens, wherein the linear image sensor IC has a bidirectional scanning function. And

(50) A reading means comprising a linear image sensor IC in which a plurality of light receiving elements are arranged one-dimensionally and a plurality of chips arranged on a mounting substrate at substantially equal intervals in the arrangement direction of the light receiving elements. In a color linear image sensor unit comprising a multi-chip type linear image sensor and a color separation means including a light source and a lens, the linear image sensor ICs have a bidirectional scanning function and are adjacent to each other. One-chip linear image sensor I of at least one pair of
C is a pair of other linear image sensor ICs,
The color linear image sensor unit is characterized by being arranged by being rotated by 180 degrees on the plane of the mounting substrate.

(51) In the method for manufacturing a multi-chip type linear image sensor according to (49), the linear image sensor IC is cut out from a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix. From above, at least one pair of the linear image sensor ICs which are adjacent in the vertical direction to the arrangement direction in which the light receiving elements are arranged or in the vicinity in the vertical direction are cut out and arranged so as to be adjacent to each other, and at least one of the pairs is arranged.
The linear image sensor IC of one chip of the pair is arranged to be rotated by 180 degrees on the plane of the mounting substrate with respect to the other linear image sensor ICs of the pair.
9) A method of manufacturing a color linear image sensor unit.

(52) In the method for manufacturing a multi-chip type linear image sensor according to (50), the linear image sensor IC is cut out from a silicon wafer in which a plurality of the linear image sensor ICs are arranged in a matrix, and
The linear image sensor IC rotated by 0 degrees is a linear image sensor IC that is adjacent to the silicon wafer in the vertical direction with respect to the arrangement direction in which the light receiving elements are arranged, or is the linear image sensor IC near the vertical direction (50). And a method for manufacturing a color linear image sensor unit.

(53) In the linear image sensor IC of (50), the input / output terminals including the power supply of the linear image sensor IC are arranged along the line of the light receiving elements and sandwich the light receiving elements. (50) The color linear image sensor unit according to (50).

(54) The method of manufacturing a multi-chip linear image sensor according to (49), wherein the linear image sensor IC is cut out from a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix. From the above, at least one pair of linear image sensor ICs which are adjacent in the vertical direction to the arrangement direction in which the light receiving elements are arranged or in the vicinity in the vertical direction are cut out and arranged so as to be adjacent to each other, and at least one pair is selected from the pair. The one-chip linear image sensor IC is rotated by 180 degrees on the plane of the mounting substrate with respect to the other linear image sensor IC to be paired, and the scanning direction in the linear image sensor IC is also reversed. Features (49)
And a method for manufacturing a color linear image sensor unit.

(55) In the method for manufacturing a multi-chip type linear image sensor according to (50), the linear image sensor IC is cut out from a silicon wafer in which a plurality of the linear image sensor ICs are arranged in a matrix, and
The linear image sensor IC that is rotated by 0 degrees is a linear image sensor IC that is adjacent to or vertically adjacent to the array direction in which the light receiving elements are arranged from the silicon wafer, and that is within the linear image sensor IC. A method for manufacturing a color linear image sensor unit according to (50), wherein the scanning direction is also reversed.

(56) In a semi-finished silicon wafer in which ICs are repeatedly provided in a matrix form on the surface of a silicon wafer, the ICs are composed of a plurality of light receiving elements or transistors arranged one-dimensionally and repeatedly. And at least one IC has a diameter of 100
A semi-finished silicon wafer characterized by having a bad mark of about 200 μm.

(57) A step of repeatedly forming a plurality of ICs in a matrix form on the surface of a silicon wafer, a probe test step of measuring electric characteristics of the ICs, and a bad mark for defective ICs. A method of manufacturing a semi-finished silicon wafer, comprising the step of: marking a bad mark by laser irradiation to a size of 100 to 200 μm in diameter. .

(58) The marking step is a step of emitting a laser beam from a YAG laser, a step of transmitting the laser beam to the vicinity of the silicon wafer with an optical fiber thinner than 100 μm, and a step of applying the laser beam from the optical fiber to the surface of the IC by an engineering lens. Forming a heat-damaged region by condensing the silicon wafer.

(59) An electronic device comprising a support base and an IC provided on a substrate so as to be in contact with each other along the length direction, wherein the width of the IC is smaller than the thickness. (60) The length of the IC is at least 20 times the width (5
The electronic device of 9) was used.

(61) Three or more ICs are linearly arranged along the length direction of the substrate (5).
The electronic device of 9) was used. (62) It is composed of a substrate provided with a groove linearly in the length direction, and an IC arranged in contact with the front groove at a side portion.
The electronic device was characterized in that the width of C was smaller than the thickness.

(63) The electronic device according to (62), wherein the IC has a larger contact area with the side of the groove than with the bottom of the groove. (64) The electronic device according to (62), wherein the width of the IC is smaller than 0.35 mm.

(65) In an electronic device in which a plurality of elongated ICs are linearly arranged on the surface of a flat and elongated substrate,
An electronic circuit is formed on the surface of C and an IC
The electronic device is characterized in that the bonding area between the side of the substrate and the substrate is larger than the bonding area between the bottom of the IC and the substrate.

(66) In an electronic device comprising a substrate on which electric wiring is printed and an IC provided on the surface of the substrate, the width of the IC is elongated compared to its thickness, and the electrical connection between the IC and the substrate is reduced. The electronic device is characterized in that the electrical connection is made via an electrical connection plate.

(67) The electronic device according to (66), further comprising a support provided on the surface of the substrate in contact with the IC. (68) The electronic device according to (67), wherein an electric connection plate is provided so as to bridge the surface of the IC and the support base.

[0070]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram of an image sensor IC according to the present invention. In the image sensor IC2, phototransistors and switch transistors electrically connected in series with the phototransistors are alternately arranged, and form a row 20 with a period of a reading pitch linearly in the scanning direction. Further, immediately after the phototransistor, a scanning circuit row for sequentially switching and controlling the switch transistor is configured in parallel with the scanning direction. Further, the pad 5 which is an external electric extraction terminal is arranged along the scanning circuit row 3.
And a driving circuit 4 for moving the scanning circuit.

FIGS. 3, 4, and 5 are electric circuit diagrams showing the circuit block diagram of FIG. 1 in more detail. Sensors S1 to S
Reference numeral 64 denotes a bipolar transistor having a floating base region potential. The collector electrode is VDD
Connected to The emitter electrode is a switch circuit M
It is connected to the drain electrodes of OS transistors SW1 to SW64. The source electrodes of the MOS transistors are connected to each other by a common line in even and odd order. M
The gate electrode of the OS transistor is controlled by signals from shift registers FF0 to FF64, which are scanning circuits.

When light is irradiated to the phototransistor, which is a sensor, the light induced charge is charged in the base region. At the time of charging, the switch circuit is turned off to receive light information. Next, at the time of reading, the switch circuit is turned ON to detect charges flowing out to the emitter region. Each MOS transistor is sequentially switched on and off by a shift register. The scanning circuit including the shift register is controlled by a driving circuit. The phototransistor, the switch transistor, and the shift register constitute one block, and one block is periodically linearly arranged in the scanning direction at a reading pick interval.

FIG. 6 is a timing chart of the circuit diagrams of FIGS. By inputting SI and CLK pulses, outputs of SO and SIG are obtained. When SO is input to SI of the next chip, SIG output is continuously obtained.
FIG. 7 is a cross-sectional view of the phototransistor side taken along the line AA ′ in FIG. P-base diffusion layer 112, P + diffusion layer 113, N + diffusion layer 114, L
An OCOS oxide film 115 and an N ± isolation layer 116 are formed. The N + diffusion layer 114 is fixed at the power supply voltage through the AL 117, and stabilizes the potential of the N- silicon substrate 111, which is the collector region of the phototransistor.
On the P + diffusion layer 113, an intermediate insulating layer 118 and a passivation film 119 are formed.

According to this structure, P-base diffusion layer 11
2 is suppressed by the N ± diffusion layer under the LOCOS oxide film and is surely separated from the chip edge 120;
Even if some cracks are formed from the chip edge 120 at the time of cutting the IC, no leak occurs between the P-base diffusion layer 112 and the N-silicon substrate 111 which is a collector region. Also, since the AL 117 blocks light that is going to enter between the P-base diffusion layer 112, which is a light receiving portion, and the chip edge 120, generation of minority carriers in the N-silicon substrate 111 due to light incidence is prevented. . When the minority carrier reaches the P-base diffusion layer 112, the minority carrier may deteriorate the MTF in the sub-scanning direction. An N + diffusion layer 114 is provided between the AL 117 and the chip edge 120, and functions to shorten the life of the minority carriers generated by light incident on this portion.

With such a structure, the distance L between the chip edge 120 and the P-base diffusion layer 112 serving as the light receiving portion can be reduced to 40 μm or less. This allows
It is possible to make the IC longer than conventional in the scanning direction. Further, another structure is shown. FIG. 8 is a sectional view taken along line AA ′ of FIG.
FIG. 8 is a cross-sectional view of the cross section on the phototransistor side, in which AL117 is removed from the structure of FIG. 7. In this structure, light is incident on a region between the chip edge 120 and the P-base diffusion layer 112, and minority carriers are generated in the N-silicon substrate 111. This minority carrier reaches the nearest P-base diffusion layer 112 and becomes part of the output of this phototransistor. In this case, P- in the sub-scanning direction
If the sum of the width and L of the base diffusion layer 112 is set to be equal to or less than the pixel pitch determined from the required resolution, the MTF in the sub-scanning direction does not deteriorate.

According to this structure, the area between the chip edge 120 and the P-base diffusion layer 112 is used as a part of the light receiving section, so that a more elongated IC can be obtained.

FIG. 9 is a plan view of one reading circuit block of the image sensor IC of the present invention. One reading circuit block 31 that is periodically arranged includes a phototransistor 38, a switch transistor 36, and a shift register 37. An emitter region 34 is arranged inside a base region 33 which is a photoelectric conversion region. A collector region is arranged around the base region 33. The collector electrode 35 is provided adjacent to the base region 33 in the scanning direction. Further, the switch transistor 36 is also provided next to the base region 33 in the scanning direction. The collector electrode 35 and the switch transistor 36 are arranged next to each other, and are each arranged on the same scanning direction side with respect to the base region 33. The switch transistor 36 is a phototransistor 3
8 inside. Therefore, the width of the read block (the length in the direction perpendicular to the scanning direction) can be reduced by the width of the switch transistor as compared with the related art. Further, as shown in FIG. 9, the base region 33 is formed to be elongated in the scanning direction. The shift register 37 is disposed immediately adjacent to the phototransistor 38. By making the plan view as shown in FIG.
0.35 mm.

FIG. 10 is a perspective view of a FAX reading sensor bed in which a plurality of image sensor ICs of the present invention are further arranged in series. The sensor ICs 2 are linearly arranged in series in the scanning direction on the sensor bed substrate 14. Each of the sensor ICs 2 is mechanically arranged at the sensor IC connection portion 44 with almost no gap. As shown in FIG. 10, the thickness of the sensor IC is 350 μm. After scribing, the width of the image sensor IC has become smaller than the thickness of the IC. Therefore, the sensor head can be formed very thin.

FIG. 11 shows an image sensor IC 2 of the present invention.
FIG. 4 is a plan view showing an arrangement of one reading block in the scanning direction corresponding to the image of the original. A row 122 of phototransistors and switch transistors and a scanning circuit row 123 including shift registers are arranged in parallel in the scanning direction. One read block of a phototransistor and a switch transistor is indicated by B. The scanning circuit of one reading block is indicated by C. As shown in FIG. 11, the shift registers C are all arranged in the same scanning direction. However, one read block of the phototransistor and the switch transistor is different at both ends in the scanning direction of the IC. That is, in the reading block on the scanning start side, as shown in FIG. 9, the base region is arranged on the scanning start side, and the switch transistor is arranged on the scanning side.

On the other hand, the reading block on the scanning end side
Unlike the base region shown in FIG. 9, the base region is arranged in a plan view as shown in FIG. That is, the switch transistor 36 is provided on the start side in the scanning direction with respect to the base region 33. By arranging the base region and the switch transistor as shown in FIG. 11, the scanning start side and the scanning end side can each be formed by the base region. With this arrangement, in a sensor bed in which a plurality of image sensor ICs are connected in series as shown in FIG. 10, a difference in sensor output between both sides of the connection portion can be reduced.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a circuit block diagram of the image sensor IC of the present invention. In the image sensor IC2, a light receiving element and scanning circuits for sequentially switching and controlling switch transistors electrically connected in series to the light receiving element are arranged alternately with each other, and the scanning circuits are linearly arranged in the scanning direction at a period of a read pitch.
4. Immediately after the light receiving element, a switch transistor array 26 is configured in parallel with the scanning direction. Further, a pad 5 serving as an external electric extraction terminal and a driving circuit 4 for moving a scanning circuit are arranged along the switch transistor row 26. Further, the switch transistor row 26 can be arranged and arranged on the opposite side of the pad 5 and the drive circuit 4 for moving the scanning circuit with the row 24 interposed therebetween.

The electric circuit diagram and the operation are the same as in the first embodiment.

FIG. 14 is a plan view of one reading circuit block of the image sensor IC according to the second embodiment of the present invention. One reading circuit block 41 that is periodically arranged includes a phototransistor 38, a switch transistor 36, and a shift register 37. An emitter region 34 is arranged inside a base region 33 which is a photoelectric conversion region. A collector region is arranged around the base region 33. The collector electrode 35 is provided adjacent to the base region 33 in the scanning direction. Further, the scanning circuit 37 is similarly provided next to the base region 33 in the scanning direction. The collector electrode 35 and the scanning circuit 37 are disposed next to each other, and the collector electrode 3
5 and a power supply electrode of the scanning circuit 37, and are arranged on the same scanning direction side with respect to the base region 33. As shown in FIG. 14A, the width of the scanning circuit 37 is equal to that of the phototransistor 38, or as shown in FIG. 14B, the width of the scanning circuit 37 is slightly larger than that of the phototransistor 38. Are located.
Therefore, the width of the read block (length in the direction perpendicular to the scanning direction) can be reduced by the width of the scanning circuit as compared with the related art. Further, as shown in FIG. 14, the base region 33 is formed to be elongated in the scanning direction. Switch transistor 36
Are arranged in parallel with the phototransistor 38.
With the plan view as shown in FIG. 14, the width of the image sensor IC can be set to 0.2 to 0.35 mm.

As in the first embodiment, the sensor head can be formed very thin as shown in FIG.

FIG. 15 is a plan view showing the arrangement in the scanning direction of one reading block corresponding to the image of the original of the image sensor IC according to the second embodiment of the present invention. A row 124 of scanning circuits such as phototransistors and shift registers and a row 125 of switch transistors are arranged in parallel in the scanning direction. One reading block of the phototransistor and the scanning circuit is indicated by B. The switch transistor of one read block is indicated by C. FIG.
5, the switch transistors C are all arranged in the same direction in the scanning direction. However, one reading block of the phototransistor and the scanning circuit is different at both ends in the scanning direction of the IC. That is, in the reading block on the scanning start side, the base area is arranged on the scanning start side as shown in FIG. 14, and the scanning circuit is arranged on the scanning side.

On the other hand, the reading block on the scanning end side
Unlike the base region shown in FIG. 14, the base region is arranged in a plan view as shown in FIG. That is, the scanning circuit 37 is
Is provided on the start side in the scanning direction. By arranging the base region and the scanning circuit as shown in FIG. 15, the scanning start side and the scanning end side can be formed by the base region, respectively. By arranging in this manner, in a sensor head in which a plurality of image sensor ICs are connected in series as shown in FIG. 10, a difference between sensor outputs on both sides of the connection portion can be reduced. Further, a similar arrangement can be made even when the light receiving element is a photodiode.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a circuit block diagram of the image sensor IC of the present invention. The image sensor IC1 includes light receiving elements, switch transistors electrically connected in series with the light receiving elements, and scanning circuit rows for sequentially switching and controlling the switch transistors, which are alternately arranged with each other. Is composed. Further, the light receiving element, the switch transistor, and the scanning circuit row 12
Along with 6, a pad 5 which is an external electric extraction terminal and a drive circuit 4 for moving a scanning circuit are arranged.

The electric circuit diagram and operation are the same as in the first embodiment.

FIG. 18 is a plan view of one reading circuit block of the image sensor IC according to the third embodiment of the present invention. One reading circuit block 51 that is periodically arranged includes a phototransistor 38, a switch transistor, and a scanning circuit 52 such as a shift register. An emitter region 34 is arranged inside a base region 33 which is a photoelectric conversion region. A collector region is arranged around the base region 33. Collector electrode 35
Are provided next to the base region 33 in the scanning direction. Further, the switch transistor and the scanning circuit 52 are similarly provided next to the base region 33 in the scanning direction. The collector electrode 35, the switch transistor, and the scanning circuit 52 are arranged adjacent to each other. The collector electrode 35 is shared with the power supply electrode of the switch transistor and the scanning circuit 52, and the same scanning is performed on the base region 33. It is arranged on the direction side. The width of the switch transistor and the scanning circuit 52 is equal to the width of the phototransistor 38 as shown in FIG. 18A, or the width of the switch transistor and the scanning circuit 52 is slightly larger than the phototransistor 38 as shown in FIG. At least a part of the width is arranged. Therefore, the width of the reading block (length in the direction perpendicular to the scanning direction) can be reduced by the width of the switch transistor and the scanning circuit as compared with the related art. Further, as shown in FIG. 18, the base region 33 is formed to be elongated in the scanning direction. Therefore, the width of the image sensor IC is set to 0.2 to 0.35 by making the plan view as shown in FIG.
mm.

As in the first embodiment, the sensor head can be formed very thin as shown in FIG.

FIG. 19 is a plan view showing the arrangement in the scanning direction of one reading block corresponding to the image of the original of the image sensor IC according to the third embodiment of the present invention. Columns 127 each including a phototransistor, a switch transistor, and a shift register are arranged in parallel in the scanning direction.
One read block of the phototransistor, the switch transistor, and the shift register is indicated by B. FIG.
As described above, one reading block of the phototransistor, the switch transistor, and the scanning circuit is different at both ends in the scanning direction of the IC. That is, the read block on the scanning start side has the base area arranged on the scanning start side as shown in FIG.
The switch transistor and the scanning circuit are arranged on the scanning side.

On the other hand, the reading block on the scanning end side
Unlike the base region shown in FIG. 18, the base region is arranged in a plan view as shown in FIG. That is, the switch transistor and the scanning circuit 52 are provided on the start side in the scanning direction with respect to the base region 33. By arranging the base region and the switch transistor as shown in FIG. 19, the scanning start side and the scanning end side can be formed by the base region, respectively. With this arrangement, in a sensor head in which a plurality of image sensor ICs are connected in series as shown in FIG.
The difference between the sensor outputs on both sides of the connection can be reduced.

Further, even when the light receiving element is a photodiode, the same arrangement can be made. Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a circuit block diagram of the image sensor IC of the present invention. The image sensor IC2 includes a light receiving element, a switch transistor electrically connected in series with the light receiving element, and a scanning circuit row for sequentially switching and controlling the switch transistor. ing. Further, a pad 5 serving as an external electric extraction terminal and a driving circuit 4 for moving the scanning circuit are arranged along the light receiving element, the switch transistor, and the scanning circuit row 126.

The electric circuit diagram and the operation are the same as in the first embodiment.

FIG. 21 shows an image sensor I according to the fourth embodiment.
It is a top view of one reading circuit block of C. One reading circuit block 53 that is periodically arranged includes:
It comprises a phototransistor 38, a switch transistor and a scanning circuit 52. The base region 33, which is a photoelectric conversion region, is “formed in a mold. Base area 3
The emitter region 34 is arranged inside the element 3. A collector region is arranged around the base region 33. At least two sides of the collector electrode 35 are provided adjacent to and adjacent to the base region 33. Further, the switch transistor and the scanning circuit 52 are similarly provided next to the base region 33. The collector electrode 35, the switch transistor, and the scanning circuit 36 are arranged adjacent to each other, and the collector electrode 35 is shared with the switch transistor and the power supply electrode of the scanning circuit 36, as shown in FIG. The switch transistor and the scanning circuit 52 are arranged in contact with at least two sides inside the width of the light receiving element 38.
Alternatively, as shown in FIG. 21B, the switch transistor and the scanning circuit 52 have the same or slightly larger width as the light receiving element 38 and are arranged so that at least three sides are in contact with each other. Therefore, the width of the reading block (length in the direction perpendicular to the scanning direction) can be reduced by the width of the switch transistor and the scanning circuit as compared with the related art. Therefore, the width of the image sensor IC is set to 0.2 to 0.
It can be 35 mm. Further, as shown in FIG. 21, light is emitted by making the width of the base region 33 as narrow as possible in the scanning direction of one reading circuit block 53 and approaching the pitch width of one light receiving element having the resolution of the image sensor IC. The range can be widened in the scanning direction, and the information in the area is averaged.

[0096]

As in the first embodiment, the sensor head can be formed very thin as shown in FIG.

FIG. 19 shows an image sensor I according to the fourth embodiment.
FIG. 9 is a plan view showing the arrangement of one reading block in the scanning direction corresponding to the image of the document C2. A column 127 of a scanning circuit including a light receiving element, a switch transistor, and a shift register is arranged in the scanning direction. One reading block of the light receiving element, the switch transistor and the scanning circuit is B
Indicated by. As shown in FIG. 19, one reading block of the light receiving element, the switch transistor, and the scanning circuit is different at both ends in the scanning direction of the IC. That is, as shown in FIG. 21, the reading block on the scanning start side has a base region arranged on the scanning start side, and a switch transistor and a scanning circuit 52 arranged on the scanning side.

On the other hand, the reading block on the scanning end side
Unlike the base region shown in FIG. 21, the base region is arranged in a plan view as shown in FIG. That is, the switch transistor and the scanning circuit 52 are provided on the start side in the scanning direction with respect to the base region 33. By arranging the base region and the switch transistor as shown in FIG. 19, the scanning start side and the scanning end side can be formed by the base region, respectively. Further, even in the place where the circuit block of FIG. 21 and the circuit block of FIG. 22 are adjacent to each other, the base region 33 is arranged close to the pitch width of one light receiving element having a resolution in the scanning direction. 22 and the circuit output of FIG. 22 can be reduced. Further, in a sensor head in which a plurality of image sensor ICs are connected in series as shown in FIG. 10, a difference between sensor outputs on both sides of the connection portion can be reduced. Also,
A similar arrangement can be made even when the light receiving element is a photodiode.

Next, a fifth embodiment of the present invention will be described with reference to the drawings. The arrangement of the circuit blocks and the electric circuit are the same as in the fourth embodiment. FIG. 23 is a plan view of one reading circuit block of the linear image sensor IC according to the fifth embodiment. One reading circuit block 54 that is periodically arranged includes the phototransistor 38, the switch transistor, and the scanning circuit 52. The base region 33, which is a photoelectric conversion region, is formed in a concave shape.
Emitter region 34 is arranged inside base region 33. A collector region is arranged around the base region 33. At least two sides of the collector electrode 35 are provided adjacent to and adjacent to the base region 33. Further, the switch transistor and the scanning circuit 52 are similarly connected to the base region 3.
3. The collector electrode 35, the switch transistor, and the scanning circuit 52 are arranged adjacent to each other. The collector electrode 35 is shared with the power supply electrode of the switch transistor and the scanning circuit 52, and the same scanning is performed on the base region 33. It is arranged on the direction side.

As shown in FIG. 23A, the switch transistor and the scanning circuit 52 are arranged in contact with at least two sides inside the width of the light receiving element 38. Alternatively, FIG.
(b) As shown in FIG.
Is equal to or slightly larger than the width of the light receiving element 38, and at least three sides are arranged in contact with each other. As a result, the width of the read block (the length in the direction perpendicular to the scanning direction) can be reduced by the width of the switch transistor and the scanning circuit as compared with the related art. Therefore, the width of the image sensor IC is set to 0.2 to 0.35 mm by forming a plan view as shown in FIG.
Can be. Further, as shown in FIG. 23, the base area 33 is formed as long as possible in the scanning direction of one reading circuit block 54. By making the width of the base region 33 as narrow as possible in the scanning direction of one reading circuit block 54 and approaching the pitch width of one light receiving element having the resolution of the image sensor IC, the range of light irradiation can be widened in the scanning direction. The information in the area is averaged.

As in the first embodiment, the sensor head can be formed very thin as shown in FIG.

FIG. 24 is a plan view showing the arrangement of one reading block in the scanning direction corresponding to the image of the original of the linear image sensor IC according to the fifth embodiment of the present invention. A column 128 of a scanning circuit including a light receiving element, a switch transistor, and a shift register is arranged in the scanning direction. One reading block of the light receiving element, the switch transistor, and the scanning circuit is indicated by B. As shown in FIG. 24, one reading block of the light receiving element, the switch transistor, and the scanning circuit is all arranged in the same scanning direction of the IC.
That is, the read block is the base area 3 as shown in FIG.
24 are disposed on both sides of the scanning start side and the scanning end side with the switch transistor and the scanning circuit 52 interposed therebetween.
By arranging the base region, the switch transistor, and the scanning circuit as described above, the scanning start side and the scanning end side can be respectively formed by the base region. By arranging in this manner, in a sensor head in which a plurality of image sensor ICs are connected in series as shown in FIG. 10, a difference between sensor outputs on both sides of the connection portion can be reduced. Further, a similar arrangement can be made even when the light receiving element is a photodiode.

Next, a sixth embodiment of the present invention will be described with reference to the drawings. The present invention can be applied in combination with all the embodiments described so far, or can be carried out alone. The circuit and operation are the same as in the first embodiment. FIG. 25 is a plan view showing the pad shape of the image sensor IC of the present invention. The pad 5 is formed of AL or the like.
The pad electrode 55 is a portion where the protective film on the pad such as AL is removed by etching or the like, and is a portion where electrical contact is possible. Xp52 is the length of the pad electrode 55 in the main scanning direction, and the size is 100 μm. Yp 53 is the length of the pad electrode 55 in the sub-scanning direction, and the size is 80 μm.
m. Therefore, the pad is elongated in the main scanning direction. 26 shows the case where the pad electrode is octagonal, and FIG. 27 shows the case where the pad electrode is elliptical. In any case, the length Xp of the pad electrode 55 in the main scanning direction is longer than the length Yp of the pad electrode 55 in the sub-scanning direction. Yp is set to 80 μm or less.

FIG. 28 is a plan view showing the image sensor IC of the present invention at the time of inspection. Probes 1 to 3 44 and 4 to 6 pins for measuring the electrical characteristics of the image sensor IC are provided on the pad 5, which is an external electric extraction terminal, along the light receiving element, the switch transistor row 20, and the scanning circuit row 3. 55 is in a state where the tip of 55 is in contact with pad 5.

Probe 1 to 3 pins 44 and probe 4
Each of the pins 6 to 55 has a three-layer multi-stage structure, and is all parallel to the length direction of the image sensor IC.
Also, they all overlap in the vertical direction. Therefore, even if light is irradiated from above, the row 20 of the phototransistors and the switch transistors does not become a shadow of the probe.

FIG. 29 is a sectional view showing the image sensor IC of the present invention at the time of inspection. Probe 1 pin to 3 pin 4
4 and the probe pins 4 to 6 are each a three-layer multi-stage type, are all parallel to the vertical direction of the image sensor IC 2, and all overlap in the vertical direction. Direction 156 is the drive direction of the probe, which moves vertically.

Direction 257 is probe pins 1 to 3
The leading end of 44 is the approach direction when the pad 5 comes into contact with the pad 5 and is overdriven, and moves to the right almost parallel to the length direction of the image sensor IC 1. The direction 358 is the approach direction when the tip of the probe 4 pin to the 6 pin 55 contacts the pad 5 and is overdriven, and moves leftward almost in parallel with the length direction of the image sensor IC 1.

FIG. 30 is a plan view showing a probe mark of a pad at the time of inspection of the image sensor IC of the present invention. The direction 460 is the approach direction of the tip of the probe,
Is substantially parallel to the length direction of The probe scar 59
This can be achieved by the probe tip contacting the pad electrode 55 and the probe tip entering. Therefore, the pad 5 is formed to be elongated in a direction substantially parallel to the length direction of the pad 5 and at the same width as the diameter of the distal end surface of the probe.

Therefore, Yp can be reduced to a size equal to or slightly larger than the diameter of the probe tip surface. On the other hand, Xp needs to be large in size by the displacement of the probe tip. As apparent from FIG. 28, the width of the image sensor IC can be reduced by reducing the width Yp of the pad electrode. For example, if the conventional Yp is 100 μm, but is changed to 80 μm, the image sensor IC
Can be reduced by 20 μm.

By reducing the width of the pad in this manner, the width of the image sensor IC is reduced to 0.2 to 0.35 m.
m. Also, when the approach direction of the tip of the probe is not parallel to the length direction of the pad, the length of the scar can be increased by making the tip of the probe approach substantially parallel to the diagonal direction of the electrode of the pad, The width of the pad can be reduced.

Next, the circuit of the present invention will be described. Although the circuit of the present invention is shown in FIGS. 3, 4, and 5, the reset state of the output terminal of the photoelectric conversion element is one of the clock pulse CLK.
Since only the HIGH period of the cycle is performed, the DUTY width of the clock pulse CLK changes, and the shorter the HIGH period, the shorter the reset period and the larger the residual charge amount.

Therefore, another circuit will be described as a seventh embodiment of the present invention. In this circuit, the reset period is constant irrespective of the duty of the clock pulse, and the reset period can be long, so that the residual charge can be reduced. Further, since the number of elements does not need to be increased so much, a chip size similar to that of the circuits shown in FIGS.

FIGS. 31 and 32 are schematic diagrams of a circuit of a linear image sensor according to a seventh embodiment of the present invention. The output terminals of the photoelectric conversion elements S2n, S2n + 1 are connected to the input terminals of the switching elements SW2n, SW2n + 1, and the output terminals of the switching elements SW2n, SW2n + 1 are When the switching elements are odd-numbered, they are connected to the first common line SL1, and when they are even-numbered, they are connected to the second common line SL2. The first common line SL1 is connected to the input terminal of the first read gate G1 and the input terminal of the first reset gate RG1, and the second common line SL2
Are connected to the input terminal of the second read gate G2 and the input terminal of the second reset gate RG2. The output terminals of the first and second read gates G1 and G2 are short-circuited to each other and are connected to a third common line SL3.

The third common line SL3 is connected to the signal output terminal SIG to the outside and the input terminal of the third reset gate RG3. The output terminals of the first, second, and third reset gates are connected to the third common line SL3. , Which are connected to a reset power supply for giving a reset potential. (For convenience, this circuit is set to GND.) Also, switching elements... SW2n, SW2n + 1
Are controlled by the scanning circuit S of the shift register.
NOR of the inverted output of the output terminal M and the inverted output of Q in each stage of the flip-flop C of FF2n, FF2n + 1,.
Obtained on output. That is, the n-th stage flip-flop F
NOR of inverted output of output terminal M of Fn and inverted output of Q
The output is connected to the control terminal of the n-th switching element SWn.

The operation of the above circuit will be described with reference to the time chart of FIG. In FIG. 3, PCLK indicates a clock pulse having a period of 1 / fCK seconds, and flip-flops.
FF2n, FF2n + 1... And the clock terminal CLK of the control circuit CC. PSI indicates a start pulse,
Flip-flop FF of scan circuit SC of shift register
The data is input to the data terminal D of 2n-1 and changes the state of the falling edge of the clock pulse PCLK in the shift register to transfer data for two cycles of the clock pulse. PSWi
Denotes a pulse for controlling the i-th (i = 2n, 2n + 1...) Switching element, and PGj denotes (j = 1,
2) indicates a pulse for controlling the j-th read gate Gj, and PRGk (k = 1, 2, 3) indicates a pulse for controlling the k-th reset gate RGk. Here, at the High level of the control pulses PSWi, PGj, and PRGk, the switching element SWi, the read gate Gj, and the input terminal of the reset gate RGk become conductive,
It is designed to be non-conductive at a low level. That is, the first and second read gates G1 and G2 are turned on / off with phases opposite to each other.

The first read gate G1 and the first reset gate RG1 are also turned on / off with phases opposite to each other. Similarly, the first and second reset gates RG1
, RG2 are conductive / non-conductive with phases opposite to each other. Also, the second read gate G2 and the second reset gate RG2 are turned on / off with phases opposite to each other.

The conductive / non-conductive state of third reset gate RG3 is repeated at substantially the same timing as clock pulse PCLK. The timing at which the conductive / non-conductive state change occurs is such that the switching element SWi is driven by the clock pulse PC.
When LK falls, one cycle of maintaining the conductive state corresponds to one and a half cycle of the clock pulse PCLK. Further, the read gate Gj and the reset gate RGk change state at the time of the rising of the clock pulse PCLK, and one cycle of maintaining the conduction state is designed to correspond to one cycle of the clock pulse PCLK.

Next, a plurality of photoelectric conversion elements Sl (l =...)
2n, 2n + 1,...) Will be described below. First,
FF2n, FF
The data PSI having a period larger than the number of BITs of the shift register composed of 2n + 1... Is input, transferred in synchronization with the falling edge of the clock, and the plurality of switching elements SWi are sequentially turned on one by one. Generate a signal. here,
For example, the signal obtained by the (2n + 1) -th photoelectric conversion element S2n + 1 indicates that the first readout gate G1 and the third reset gate RG3 become conductive at the rising of the clock pulse PCLK. ) -Th switching element SW (2n + 1) is in a non-conductive state,
1) The signal obtained by the photoelectric conversion element S (2n + 1) has not been read out to the first common line yet. Therefore, a reset voltage is output from the signal output terminal SIG because the third reset gate RG3 is in a conductive state. Next, when the clock pulse PCLK falls, the reset gate of title 3 becomes nonconductive, and the (2n + 1) th switching element SW2n + 1 becomes conductive with a slight delay, and the (2n) th switching element SW2n + 1 becomes conductive.
The signal obtained by the (+1) -th photoelectric conversion element S2n + 1 passes through the switching element SW2n + 1, the first common line SL1, the first read gate RG1, and the third common line SL3, and the signal is output to the signal output terminal SIG. Is read out to the outside. At this time, the second read gate G2, the first reset gate RG1, and the third reset gate are non-conductive, the second reset gate RG2 is conductive, and the second common line SL2 is reset. Fixed to voltage.

Next, at the rising of the clock pulse PCLK, the first read gate G1 shifts to the non-conductive state,
First reset gate RG1 and second read gate G
2 and the third reset gate are turned on. At this time, since the (2n + 1) -th switching element SW2n + 1 is in a conductive state, the (2n + 1) -th photoelectric conversion element S2n + 1 includes the switching element SW2n + 1 and the first common line SL1 and the first common line SL1. Is connected to a reset power supply via the reset gate RG1. At this time, the second (n + 1) -th switching element SW2 (n + 1)
Is in a non-conducting state, the signal obtained by the second (n + 1) -th photoelectric conversion element S2 (n + 1) has not yet been read out to the second common line. Therefore, from the signal output terminal SIG,
Since the third reset gate RG3 is conductive, a reset voltage is output.

Next, when the clock pulse PCLK falls, the third reset gate RG3 is turned off, and the second (n + 1) th switching element SW2 (n + 1) is turned on with a slight delay. The signal obtained by the second (n + 1) -th photoelectric conversion element S2 (n + 1) includes the switching element SW2 (n + 1), the second common line SL2, the second read gate G2, and the third common line. The signal is read out to the outside through the signal output terminal SIG through SL3. Further, the first read gate G1 is in a non-conductive state, the signals of the (2n + 1) -th photoelectric conversion element S2n + 1 do not overlap, and the first reset gate RG1 is in a conductive state and the first reset gate RG1 is in the first common state. Line SL1 is fixed at the reset voltage. Therefore, the (2n + 1) -th switching element SW2n + 1 is in a conductive state, and the (2n + 1) -th photoelectric conversion element S2n + 1 is in a reset state.

Next, at the rising of the clock pulse PCLK, the second read gate G2 shifts to the non-conductive state,
The (2n + 1) -th switching element SW2n + 1 becomes non-conductive and the (2n + 1) -th photoelectric conversion element S2n + 1
Is released from the reset state and enters a charge accumulation state which is a photoelectric conversion state. The second reset gate RG2 and the first
Read gate G1 and the third reset gate are turned on. At this time, since the second (n + 1) -th switching element SW2 (n + 1) is in the conductive state, the second (n +)
1) The first photoelectric conversion element S2 (n + 1) is connected to a reset power supply via the switching element SW2 (n + 1), the second common line SL2 and the second reset gate RG2, and Become. Also, at this time, the second (n + 1) + 1-th switching element SW2 (n + 1) +1 is in a non-conducting state, and therefore the second (n + 1) + 1-th photoelectric conversion element S2 (n + 1) +1.
Have not been read out to the second common line yet. Therefore, a reset voltage is output from the signal output terminal SIG because the third reset gate RG3 is in a conductive state.

Next, when the clock pulse PCLK falls, the third reset gate RG3 becomes non-conductive,
With a slight delay, the (2n + 1) + 1-th switching element SW2n + 1 + 1 becomes conductive, and the signal obtained by the (2n + 1) + 1-th photoelectric conversion element S (2n + 1) +1 is the switching element SW ( 2n + 1) +1, the first common line SL1, the first read gate G1, and the third common line SL3, and are read out to the outside via the signal output terminal SIG. At this time,
The second read gate is non-conductive, and the second reset gate RG2 is conductive and the second common line SL2
Are fixed to the reset voltage. Therefore, the (2n +
The 1) th switching element SW2n + 1 is in a conductive state, and the (2n + 1) th photoelectric conversion element S2n + 1 is in a reset state.

Next, at the rising of the clock pulse PCLK, the first read gate G1 shifts to the non-conductive state, and
The second (n + 1) th switching element SW2 (n + 1) becomes non-conductive, and the second (n + 1) th photoelectric conversion element S2
(n + 1) is released from the reset state and enters a charge storage state which is a photoelectric conversion state. The first reset gate RG1
And the second read gate G2 and the third reset gate are turned on. At this time, since the second (n + 1) + 1-th switching element SW2 (n + 1) +1 is in a conductive state, the second (n + 1) + 1-th photoelectric conversion element S2 (n + 1) +1
Represents the switching element SW2 (n + 1) +1 and the first common line SL
1 and a reset power supply via the first reset gate RG1 to enter a reset state.

By this repetition, signals obtained by the plurality of photoelectric conversion elements are sequentially read to the outside, and the reset state becomes one cycle of the clock pulse PCLK. Even if the DUTY width of the clock pulse changes, the reset state is reset. The operation cycle does not change. In addition, when any of the switching elements and the read gates are changed from the non-conductive state to the conductive state to read a signal to the outside, since the read gate Gk is already in a steady state, the fixed pattern noise and the switching noise of the read gate are converted by photoelectric conversion. The signal does not overlap, and the S / N ratio does not decrease. Thus, the operation of the linear image sensor is obtained.

Next, FIGS. 34, 35 and 36 show an eighth embodiment of the present invention.
It is a schematic diagram of a circuit of an image sensor of an example. In this embodiment, the number of common lines connected to the output terminals of the switching elements of the image sensor of the present invention shown in FIGS. 31 and 32 is increased by a plurality. Photoelectric conversion element: S4n
+1 and S4n + 2 ... output terminals are switching elements
The input terminals of SW4n + 1, SW4n + 2,... Are connected, and the output terminals of the switching elements, SW4n + 1, SW4n + 2, are the first common line SL1 in the first case. And the second
The third case is connected to the second common line SL2, the third case is connected to the third common line SL3, and the fourth case is connected to the fourth common line SL4.

The first common line SL1 is connected to the input terminal of the first read gate G1 and the input terminal of the first reset gate RG1, and the second common line SL2 is connected to the input terminal of the second read gate G2. The third common line SL3 is connected to the input terminal of the third read gate G3 and the input terminal of the third reset gate RG3, and the fourth common line SL4 is connected to the input terminal of the second reset gate RG2. The input terminal of the fourth read gate G4 and the input terminal of the fourth reset gate RG4 are connected.

First, second, third and fourth read gates G
The output terminals of 1, G2, G3 and G4 are short-circuited to each other,
Are connected to a common line SL5. Fifth common line SL5
Is connected to the signal output terminal SIG to the outside and the input terminal of the fifth reset gate RG5.
The output terminals of the third, fourth, and fifth reset gates are connected to a reset power supply that provides a reset potential. (For convenience, this circuit is assumed to be GND.) The signals for controlling the switching elements... SW4n + 1, SW4n + 2. FF4n + 2... Are obtained by NOR output of the inverted output of the output terminal M and the inverted output of Q at each stage. That is, the NOR output of the inverted output of the output terminal M and the inverted output of Q of the n-th flip-flop FFn is connected to the control terminal of the n-th switching element SWn.

The operation of the above circuit will be described with reference to the time chart of FIG. In FIG. 37, PCLK is 1 / fCK
Indicates a clock pulse with a cycle of second, flip-flop
FF4n + 1, FF4n + 2,... And the clock terminal CLK of the control circuit CC. PSI indicates a start pulse. The start pulse is input to the data terminal D of the flip-flop FF4n + 1 of the scan circuit SC of the shift register, and a state change occurs in the shift register at the falling edge of the clock pulse PCLK. Will be transferred. PSW
i denotes a pulse for controlling the i-th (i = 4n + 1, 4n + 2...) switching element, and PGj denotes (j =
1, 2, 3, 4) indicate pulses for controlling the j-th read gate Gj, and PRGk (k = 1, 2, 3, 4, 4)
5) shows a pulse for controlling the k-th reset gate RGk.

Here, the above-described control pulses PSWi and PG
j and PRGk at the high level, the switching element S
Wi and the input terminals of the read gate Gj and the reset gate RGk are designed to be conductive and nonconductive at a LOW level. That is, the j-th read gate Gj and the k-th reset gate RGk are turned on / off with phases opposite to each other (j = k = 1, 2, 3, 3).
4). The fifth reset gate RG5 receives the clock pulse P
The conduction / non-conduction state is repeated at substantially the same timing as CLK. The timing at which the conduction / non-conduction state is changed is when the switching element SWi falls at the falling edge of the clock pulse PCLK, and one cycle of maintaining the conduction state corresponds to three and a half cycles of the clock pulse PCLK. Further, the read gate Gj and the reset gate RGk change state every four cycles of the clock pulse PCLK at the rise of the clock pulse PCLK, and one cycle of maintaining the conductive state corresponds to one cycle of the Gj clock pulse PCLK. The reset gate RGk is designed to correspond to three periods of the clock pulse PCLK.

Next, a plurality of photoelectric conversion elements Sl (l =...)
4n + 1, 4n + 2,...) And the reset operation of the signals. First, a flip-flop... FF4n +
The data PSI having a cycle larger than the number of BITs of the shift register composed of 1, FF4n + 2... Is input and transferred in synchronization with the falling edge of the clock, and a plurality of switching elements SW
A scanning signal is generated such that i is sequentially turned on one stage at a time. Here, for example, the signal obtained by the (4n + 1) -th photoelectric conversion element S4n + 1 is supplied to the first read gate G1 and the fifth reset gate RG5 by the clock pulse PCLK.
At the rising edge of the switch, the (4n + 1) -th switching element SW4n + 1 is in a non-conductive state.
The signal obtained by the (4n + 1) -th photoelectric conversion element S4n + 1 has not been read out to the first common line yet. Therefore, from the signal output terminal SIG, the fifth reset gate RG5
Is in a conductive state, a reset voltage is output.

Next, when the clock pulse PCLK falls, the fifth reset gate RG5 becomes non-conductive,
The (4n + 1) th switching element SW with a slight delay
4n + 1 becomes conductive, and the signal obtained by the (4n + 1) -th photoelectric conversion element S4n + 1 is the switching element SW4n + 1.
And the first common line SL1 and the first read gate G1
And read out to the outside through the signal output terminal SIG through the fifth common line SL5. At this time, the second, third, and fourth read gates G2, G3, G4 are in a non-conductive state, and the second, third, and fourth reset gates RG2, R4
G3 and RG4 are conductive and the second, third and fourth common lines S
L2, SL3 and SL4 are fixed to the reset voltage.

Next, at the rising of the clock pulse PCLK, the first read gate G1 shifts to the non-conductive state, and
First reset gate RG1 and second read gate G
2 and the fifth reset gate RG5 are turned on. At this time, the (4n + 1) th switching element S
Since W4n + 1 is in a conductive state, the (4n + 1) -th photoelectric conversion element S4n + 1 is connected to the switching element SW4n + 1 and the first
Is connected to a reset power supply via the common line SL1 and the first reset gate RG1 to be in a reset state. At this time, the (4n + 2) th switching element SW
Since 4n + 2 is in a non-conductive state, the signal obtained by the (4n + 2) -th photoelectric conversion element S4n + 2 has not been read out to the second common line yet. Therefore, a reset voltage is output from the signal output terminal SIG because the fifth reset gate RG5 is in a conductive state.

Next, when the clock pulse PCLK falls, the fifth reset gate is turned off, and the (4n + 2) th switching element SW4n + 2 is turned on with a slight delay, and the (4n + 2) th switching element SW4n + 2 is turned on. Photoelectric conversion element S
The signal obtained by 4n + 2 is read out to the outside via the signal output terminal SIG through the switching element SW4n + 2, the second common line SL2, the second read gate G2, and the fifth common line SL5. The first, third, and fourth read gates G1, G3, and G4 are non-conductive, and the first, third, and fourth reset gates RG1, RG3, and RG are not connected.
4 is a conducting state, and the first, third, and fourth common lines SL1, SL
3 and SL4 are fixed to the reset voltage. Therefore, the (4n + 1) -th switching element SW4n + 1 is in a conductive state, and the (4n + 1) -th switching element SW4n + 1 is in a conductive state.
Is in the reset state.

Next, at the rising of the clock pulse PCLK, the second read gate G2 shifts to the non-conductive state, and
Second reset gate RG2 and third read gate G
3 and the fifth reset gate RG5 are turned on. At this time, the (4n + 2) th switching element S
Since W4n + 2 is in a conductive state, the (4n + 2) th photoelectric conversion element S4n + 2 is connected to the switching element SW4n + 2 and the second
Through a common line SL2 and a second reset gate RG2 to enter a reset state. At this time, the (4n + 3) th switching element SW
Since 4n + 3 is off, the signal obtained by the (4n + 3) -th photoelectric conversion element S4n + 3 has not been read out to the third common line yet. Therefore, a reset voltage is output from the signal output terminal SIG because the fifth reset gate RG5 is in a conductive state.

Next, when the clock pulse PCLK falls, the fifth reset gate is turned off, the (4n + 3) th switching element SW4n + 3 is turned on with a slight delay, and the (4n + 3) th switching element SW4n + 3 is turned on. Photoelectric conversion element S
The signal obtained by 4n + 3 is read out to the outside via the signal output terminal SIG through the switching element SW4n + 3, the third common line SL3, the third read gate G3, and the fifth common line SL5. The first, second, and fourth read gates G1, G2, and G4 are non-conductive, and the first, second, and fourth reset gates RG1, RG2, and RG
4 is a conducting state, and the first, second, and fourth common lines SL1, SL
2 and SL4 are fixed to the reset voltage. Therefore, the (4n + 1) -th switching element SW4n + 1 and the (4n + 2) -th switching element SW4n + 2 are in a conductive state, and the reset state of the photoelectric conversion elements S4n + 1 and S4n + 2 continues.

Next, at the rising of the clock pulse PCLK, the third read gate G3 shifts to the non-conductive state, and
Third reset gate RG3 and fourth read gate G
4 and the fifth reset gate RG5 are turned on. At this time, the (4n + 3) th switching element S
Since W4n + 3 is in a conductive state, the (4n + 3) th photoelectric conversion element S4n + 3 is connected to the switching element SW4n + 3 and the third
Through a common line SL3 and a third reset gate RG3 to be in a reset state. At this time, the (4n + 4) th switching element SW
Since 4n + 4 is off, the signal obtained by the (4n + 4) -th photoelectric conversion element S4n + 4 has not been read to the fourth common line yet. Therefore, a reset voltage is output from the signal output terminal SIG because the fifth reset gate RG5 is in a conductive state.

Next, when the clock pulse PCLK falls, the fifth reset gate is turned off, the (4n + 4) th switching element SW4n + 4 is turned on with a slight delay, and the (4n + 4) th switching element SW4n + 4 is turned on. Photoelectric conversion element S
The signal obtained at 4n + 4 is read out to the outside via the signal output terminal SIG through the switching element SW4n + 4, the fourth common line SL4, the fourth read gate G4, and the fifth common line SL5. At this time, the first, second, and third read gates G1, G2, G3 are in a non-conductive state, and the first, second, and third reset gates RG1, RG2, RG
3 is a conducting state, and the first, second, and third common lines SL1, SL
2 and SL3 are fixed to the reset voltage. Therefore, the (4n + 1) th switching element SW4n + 1, the (4n + 2) th switching element SW4n + 2 and the (4n + 1) th
The (n + 3) th switching element SW4n + 3 is in a conductive state, and the photoelectric conversion elements S4n + 1, S4n + 2, SW4n + 3.
Reset state continues.

Next, at the rising of the clock pulse PCLK, the fourth read gate G4 shifts to the non-conductive state, and
The (4n + 1) -th switching element SW4n + 1 becomes non-conductive, and the (4n + 1) -th photoelectric conversion element S4n + 1
Are released from the reset state and enter a charge storage state which is a photoelectric conversion state. Further, the fourth reset gate RG4 and the first
Read gate G1 and the fifth reset gate RG
5 goes into conduction. At this time, since the (4n + 4) th switching element SW4n + 4 is in the conductive state, the (4n + 4) th switching element SW4n + 4
The (n + 4) -th photoelectric conversion element S4n + 4 is connected to the reset power supply via the switching element SW4n + 4, the fourth common line SL4, and the fourth reset gate RG4, and enters a reset state. At this time, since the (4n + 5) th switching element SW4n + 4 is in a non-conductive state,
The signal obtained by the (n + 5) -th photoelectric conversion element S4n + 5 has not yet been read to the first common line. Therefore, a reset voltage is output from the signal output terminal SIG because the fifth reset gate RG5 is in a conductive state.

Next, when the clock pulse PCLK falls, the fifth reset gate is turned off, the (4n + 5) th switching element SW4n + 5 is turned on with a slight delay, and the (4n + 5) th switching element SW4n + 5 is turned on. Photoelectric conversion element S
The signal obtained at 4n + 5 is again applied to the switching element SW4n + 5
Through the first common line SL1, the first read gate G1, and the fifth common line SL5, and the signal output terminal SI
It is read out via G.

By this repetition, the signals obtained by the plurality of photoelectric conversion elements are sequentially read out to the outside, and the reset state becomes three cycles of the clock pulse PCLK, which is three times that of the first embodiment. , 1 / (3 × fCK) seconds, the reset state is the same period, and the amount of reduction in the residual charge amount is the same. Further, even if the duty width of the clock pulse changes, the cycle of the reset state does not change. In addition, when any of the switching elements and the read gate are changed from the non-conductive state to the conductive state to read a signal to the outside, the read gate Gk has already been read.
Is in a steady state, the fixed pattern noise and the switching noise of the read gate do not overlap with the photoelectrically converted signal, and the S / N ratio does not decrease. In this way, if the number of common lines connected to the output terminals of the switching elements of the image sensor is further increased to m, the period of the reset state is 1 / ((m−
1) × fck) is obtained.

As described above, according to the seventh embodiment and the eighth embodiment, since the cycle for resetting each photoelectric conversion element is changed, only the addition of the circuit in the flip-flop for the scanning circuit is performed. The size can also be realized with the minimum size. Therefore, the cycle of the reset operation can be extended without increasing the number of elements and keeping the chip size small and small. In addition, the residual charge amount can be reduced without depending on the duty of the clock pulse, and the afterimage characteristic can be improved.
Further, a good image signal can be obtained without switching noise and fixed pattern noise of a gate for switching a plurality of common lines and a reset gate.

Next, an IC mounting board and a method of manufacturing the same according to the present invention will be described as a ninth embodiment with reference to the drawings. FIG. 39A is a plan view of a silicon wafer for obtaining an IC used for the IC mounting substrate of the present invention.

A plurality of ICs 2 having the same pattern are printed in a matrix on the surface of the silicon wafer 1 by using ordinary photolithography technology. Each IC has a scribe line 15 provided vertically in the horizontal and vertical directions.
Separated by Further, the IC used for the IC mounting board of the present invention has a width of at least a pad width (typically 50 to 100).
μm) longer than 400 μm. IC length is 5m to reduce the number of chips used for mounting
m to 15 mm. Processing is performed using a stepper to make the width of the IC smaller than 400 μm. Therefore, the length of the IC is within the maximum transfer length of the stepper of 15 mm. Further, in order to obtain a very thin and long chip, the length is kept within 15 mm to maintain the mechanical strength. The silicon wafer 1 is processed to a thickness of about 600 μm in the case of processing such as oxidation and etching in an IC process, and in the case of a 6-inch wafer. Since the IC is elongated, the IC can be efficiently printed by using a large-diameter wafer of 6 inches or more. As the diameter of the wafer becomes larger, the thickness of the wafer becomes 4 to maintain the mechanical strength of the wafer.
ICs are printed and processed with a size of 00 μm or more.

Since the width of the IC used in the present invention is extremely narrow, that is, 400 μm or less, it is necessary to lower the center of gravity in order to stably dispose the IC on a mounting board. Therefore, after the IC is printed on the front surface of the silicon wafer 1, the back surface of the silicon wafer 1 is thinned to about 350 μm by polishing (polishing).

Next, the electrical characteristics of all ICs on the wafer are measured by a tester. The measurement results of all ICs are stored on a floppy disk 9 which is an electrically readable storage means. Data for discriminating good / defective products of all ICs is stored corresponding to the coordinates of the matrix-shaped ICs 2 of the silicon wafer 1. Next, the ultraviolet adhesive tape 16 is adhered to the back surface of the silicon wafer 1. This tape is easily deformed elastically, and the adhesive strength can be controlled by irradiation with ultraviolet rays. When the silicon wafer 1 is scribed, it is sufficiently adhered to the silicon wafer so that the silicon wafer 1 does not come off. By irradiating the ultraviolet ray adhesive tape with ultraviolet rays, air bubbles are not generated between the silicon wafer and the tape, and the tape can be uniformly adhered along the surface without irregularities.

Next, scribing is performed by repeating vertical and horizontal reciprocating motions along the scribe line 15 from the surface of the silicon wafer 1. The scribes spatially separate the ICs that have been mechanically connected to each other by the silicon wafer. Next, as shown in FIG. 39B, the adhesive tape 16 is two-dimensionally stretched along the tape surface. Then, each IC separated by the scribe further separates. Leave more than the width of the scribe line.

Next, as shown in FIG. 39C, the ICs 2 separated by the robot 7 are taken out and placed on the head substrate 14. The robot 7 is controlled by a computer 8. The computer 8 reads out the electrical characteristic data in the wafer for the probing test from the floppy disk 9, selects only non-defective products, and controls the robot 7 to arrange the IC. In the case of an image sensor IC, the sensor sensitivity differs within a silicon wafer. By using the manufacturing method of the present invention, it is easy to mount an IC having similar characteristics. By programming the computer 8 so that the ICs having characteristics close to each other are sequentially arranged, it is possible to greatly reduce the variation between the mounted sensors.

In the IC mounting board of the present invention, a plurality of ICs are arranged one-dimensionally to form a spatially long function such as an image sensor or a current driver. Therefore, in an image sensor, it is important to reduce the difference in sensor sensitivity between both ends of the mounting board. In a current driver, it is important to reduce the difference between the current values at both ends of the mounting board so that, for example, the color of the thermal paper does not become uneven. By sequentially selecting and arranging each IC on the mounting board in accordance with the characteristic data of the IC of the floppy disk, the difference in the characteristics of the IC in the mounting can be made very small.

FIG. 40 is a plan view of an IC used for the IC mounting board of the present invention. The IC chip 2 has four or more pads 5 for power supply, signal supply and output terminals. Also, transistors 32 of the same shape are periodically arranged along the length direction of the chip. For example, in an image sensor IC, photodiodes or phototransistors are provided one-dimensionally at a read pitch cycle along a scanning direction. Further, in a thermal head IC for flowing a current to the resistance of the thermal paper, driver transistors are periodically and one-dimensionally arranged corresponding to the resistance provided for each thermal paper pitch. The width of the chip is formed larger than the pad width of 50 to 100 μm and smaller than 400 μm. The width of the image sensor IC we have developed is 33 after scribing.
The thickness is 0 μm and smaller than the chip thickness of 350 μm. By making such a thin IC, mounting on a mounting substrate 42 on a cylinder as shown in FIG. 41 becomes possible. If the mounting substrate 42 is straight in the disposing direction, the chip is extremely thin even if the cross section is circular as shown in the figure, so that the mounting substrate and the I
The adhesive strength with C can be sufficiently maintained.

Next, the image sensor ICs and I of the present invention will be described.
A C-mount substrate and a method of manufacturing the same will be described as a tenth embodiment with reference to the drawings. FIG. 39 (a) is a plan view of a silicon wafer for obtaining an IC arranged on the IC mounting substrate of the present invention.

A plurality of ICs 2 having the same pattern are printed in a matrix on the surface of the silicon wafer 1 by using ordinary photolithography technology. Each IC has a scribe line 15 provided vertically in the horizontal and vertical directions.
Separated by Further, the IC used for the IC mounting board of the present invention has a narrow width of, for example, 400 μm. I
The length of C is set to 5 mm to 15 mm in order to reduce the number of chips used for mounting. Processing is performed using a stepper to reduce the width of the IC. Therefore, the length of the IC is within the maximum transfer length of the stepper of 15 mm. In addition, the length must be reduced to 15
mm or less to maintain the mechanical strength. The silicon wafer 1 is processed to a thickness of about 600 μm in the case of processing such as oxidation and etching in an IC process, and in the case of a 6-inch wafer. Since the IC is elongated, the IC can be efficiently printed by using a large-diameter wafer of 6 inches or more. In order to maintain the mechanical strength of the wafer as the wafer becomes larger in diameter, the thickness of the wafer should be 400 μm or more and I
C is printed and processed.

FIG. 40 is a plan view of an IC arranged on the IC mounting board of the present invention. The IC 2 has four or more pads 5 for power supply, signal supply and output terminals. In addition, the light receiving elements 32 of the same shape, each of which is composed of a phototransistor or a photodiode, are periodically arranged in plural numbers along the length direction of the chip. The light receiving elements 32 are provided one-dimensionally at a reading pitch cycle along the scanning direction. The charge stored in the light receiving element is output from the output terminal in order from the leftmost light receiving element.
The width of the chip is, for example, 400 μm and the length is, for example, 8 mm, which is considerably elongated.

FIG. 42 is an enlarged view of a part of the surface of the silicon wafer 1. In FIG. 42, ICs adjacent to each other in the direction in which the light receiving elements of the ICs are arranged and in the vertical direction are formed so as to have a point-symmetric relationship with each other. For example, IC2A is
The pattern is obtained by rotating the IC 2B by 180 °. That is, a pattern in which two chips arranged symmetrically with respect to a point are set as one set is repeatedly arranged. A scribe line 15 is provided between each IC as a space for separating the IC later. To form such a pattern, a reticle to be set on a stepper,
What is necessary is just to mount a plurality of patterns in which two chips arranged in point symmetry are set as one set.

Since the width of the IC is very small, about 400 μm, it is necessary to lower the center of gravity in order to stably dispose it on a mounting board. Therefore, after the IC is printed on the front surface of the silicon wafer 1, the back surface of the silicon wafer 1 is thinned to about 350 μm by polishing (polishing).

Next, the wafer 1 is placed on the wafer stage of the prober, and the electric characteristics of all ICs on the wafer are measured by a tester. FIG. 43 is an enlarged view of a central portion of a probe card attached to a prober for testing IC 2 in wafer 1. The test of the IC 2 is performed by bringing the tip of the needle 45 attached to the probe card into contact with the pad 5 of the IC 2. The needle 45 has a function of bringing the IC tester and the IC 2 into electrical contact. I
The C tester determines the quality of IC2. In the present invention, the downward needle 45 is positioned so as to contact the pad of the IC 2A in FIG. 43, and the upward needle 45 is positioned so as to contact the pad of the IC 2B in FIG. That is, two chips can be tested simultaneously. Then, the wafer stage is moved at a pitch twice the pitch of the short side of the IC, and the next two chips are tested. In this method, the test time per wafer can be reduced to about half as compared with a normal method for testing one chip at a time.

In the test of the image sensor IC, the light must be applied to the light receiving element of the IC.
A and 2B are irradiated. At this time, since the light receiving element rows face each other and the ICs 2A and 2B are located on the opposite sides of the light receiving element row where the pads face each other, the needle does not block light incident on the light receiving element during the probe test. .
On the other hand, when all the ICs are arranged in the same direction, the light receiving element of one of the two chips is
5, the uniform light cannot be applied to the light receiving element array. Therefore, accurate pass / fail judgment cannot be made, and it is difficult to test two chips simultaneously. That is, according to the present invention, an IC that is vertically adjacent to the direction in which
Are formed so as to have a point symmetrical relationship with each other, so that an accurate test can be performed simultaneously on two chips.

Next, a bad mark is formed on the IC determined to be defective based on the test result. Alternatively, the pass / fail judgment result is recorded on a floppy disk or the like together with the IC coordinate data. Next, an ultraviolet adhesive tape is adhered to the back surface of the silicon wafer. This tape is easily deformed elastically, and the adhesive strength can be controlled by irradiation with ultraviolet rays. When the silicon wafer is scribed, it is sufficiently adhered to the silicon wafer so as not to peel off.

Next, scribing is performed by repeating vertical and horizontal reciprocating motions along the scribe line 15 from the surface of the silicon wafer 1. The scribes spatially separate the ICs that have been mechanically connected to each other by the silicon wafer. Next, as shown in FIG. 39B, the adhesive tape is two-dimensionally stretched along the tape surface. Then, each IC separated by the scribe further separates. Leave more than the width of the scribe line.

Next, as shown in FIG. 39 (c), the ICs 2 separated by the robot 7 are taken out and placed on the head substrate 14. The robot 7 is controlled by a computer 8. The computer 8 reads out the electrical characteristic data in the wafer for the probing test from the floppy disk 9, selects only non-defective products, and controls the robot to place the IC2. Alternatively, a bad mark hit on a defective IC chip is image-recognized and only good products are selected.

In the present invention, adjacent IC chips are sequentially picked up by the robot 7 and arranged on the mounting board 14. At this time, by arranging the IC chips so as to be connected in order, the chips adjacent on the wafer can be also adjacent on the mounting substrate 14. For example, the lowermost non-defective chips C in the next row are arranged after the IC chips of B are arranged in order from the uppermost non-defective chips A in the rightmost column shown in FIG. Next, they are arranged in order from C, and thereafter, D and E are similarly arranged. On the way, when the mounting board 6 has been arranged, it is arranged on the next mounting board 6. In addition, since the IC chips 2 have opposite directions in the even-numbered rows and the odd-numbered rows on the wafer, it is necessary to alternately arrange the IC chips 2 at 180 °.

In the case of the image sensor IC, the sensitivity of the light receiving element varies within the silicon wafer. This is because
The sensitivity tends to change continuously within the wafer because it is considered that the heat distribution in the IC manufacturing process is non-uniform in the wafer surface and the thickness of the various insulating films is non-uniform. Therefore, if the distance between the light receiving elements on the wafer is short, the sensitivity difference may be small, and if the distance is long, the sensitivity difference may be large.

For example, in FIG. 39B, assuming that the sensitivity increases as going to the right, the IC
The output when the mounting substrate 14 on which the chips are arranged is irradiated with uniform light is as shown in FIG. FIG. 45 shows the output waveform of the image sensor head of the present invention, in which the number of IC chips is six. Since the directions of the adjacent IC chips are opposite on the wafer, the inclination of the output is alternately opposite.
Therefore, there is almost no output difference between adjacent IC chips. This is because adjacent light receiving elements between adjacent chips arranged on the mounting substrate 6 are arranged very close on the wafer. For example, in the case of an IC having a length of 8 mm and a width of 0.4 mm, adjacent light receiving elements between adjacent chips are separated from each other by a maximum of 0.8 mm on the wafer, and light receiving elements at both ends in one chip. Approximately 8m between
It is 1/10 compared to m.

On the other hand, when all the ICs are arranged in the same direction on the wafer, the output when the mounting substrate 6 on which the ICs are similarly arranged is irradiated with uniform light is as shown in FIG. Become. FIG. 44 shows an output waveform of a conventional image sensor head, and there is an output step at a connection portion of a chip. That is, the sensitivity changes suddenly, and the output must be corrected for each bit. In FIG. 45, since there is no portion where the sensitivity changes suddenly, it is sufficient to correct the output without correction or with the average value every few bits, and the memory of the external circuit is small, and the calculation of the correction is easy. Become.

In the above description of the present invention, if there is a defective chip, and if the inclination of the output in the chip adjacent to the defective chip is small, only the defective chip is treated as defective. Specifically, hitting bad marks or IC
Is recorded on a floppy disk or the like together with the coordinate data of (1). When the output gradient of the chip adjacent to the defective chip is large, one of the two chips adjacent to the defective chip is also treated as defective. In this way, there is no portion where the sensitivity changes abruptly between adjacent chips.

If there is a defective chip, there is a method of unconditionally treating one of two adjacent chips as defective. There is also a method in which only a defective chip is treated as defective, and when there is a defective chip when mounting with a robot, the next chip is skipped and mounted. In any of the above methods, an image sensor head having a small output step at the connection portion of the IC chip can be obtained.

As described above, according to the tenth embodiment, the ICs adjacent to each other in the direction perpendicular to the direction in which the light receiving elements of the ICs are arranged are arranged.
Since C is formed so as to have a point symmetrical relationship with each other, an accurate test can be performed simultaneously on two chips, so that the manufacturing cost can be reduced. In addition, an output step between adjacent chips can be reduced, and an IC mounting substrate with less variation between ICs can be manufactured.

Next, the image sensor ICs and I of the present invention will be described.
An eleventh embodiment of the C mounting board and its manufacturing method will be described with reference to the drawings. FIG. 46A is a plan view of a silicon wafer for obtaining an IC arranged on the IC mounting substrate of the present invention.

A plurality of ICs 2 having the same pattern are printed in a matrix on the surface of the silicon wafer 1 by using ordinary photolithography technology. Each IC has a scribe line 15 provided vertically in the horizontal and vertical directions.
Separated by Further, the IC used for the IC mounting board of the present invention has a narrow width of, for example, 400 μm. I
The length of C is set to 5 mm to 15 mm in order to reduce the number of chips used for mounting. Processing is performed using a stepper to reduce the width of the IC. Therefore, the length of the IC is within the maximum transfer length of the stepper of 15 mm. In addition, the length must be reduced to 15
mm or less to maintain the mechanical strength. The silicon wafer 1 is processed to a thickness of about 600 μm in the case of processing such as oxidation and etching in an IC process, and in the case of a 6-inch wafer. Efficiently prints ICs by using large-diameter wafers of 6 inches or more because they are elongated ICs.
Can be processed. As wafers become larger in diameter, ICs are printed and processed with a wafer thickness of 400 μm or more in order to maintain the mechanical strength of the wafer.

FIG. 47 is a plan view of an IC mounted on the IC mounting board of the present invention. The IC 2 usually has six or more pads 5 for a power source, a control input / output terminal, and an image signal output terminal.
Are formed. In addition, the light receiving elements 32 of the same shape, each of which is composed of a phototransistor or a photodiode, are periodically arranged in plural numbers along the length direction of the chip.
The light receiving elements 32 are provided one-dimensionally at a reading pitch cycle along the scanning direction. The charge stored in the light receiving element is sequentially scanned rightward from the leftmost light receiving element,
Conversely, the image is output from the image signal output terminal by sequentially scanning leftward from the rightmost light receiving element. That is, it has a bidirectional scanning function. The width of the chip is, for example, 400 μm and the length is, for example, 8 mm, which is considerably elongated.

FIG. 48 is an enlarged view of a part of the surface of the silicon wafer 1.

Since the width of the IC is very small, about 400 μm, it is necessary to lower the center of gravity in order to stably dispose the IC on a mounting board. Therefore, after the IC is printed on the front surface of the silicon wafer 1, the back surface of the silicon wafer 1 is thinned to about 350 μm by polishing (polishing).

Next, the wafer 1 is placed on the wafer stage of the prober, and the electric characteristics of all ICs on the wafer are measured by a tester. FIG. 49 is an enlarged view of a central portion of a probe card attached to a prober for testing the IC 2 in the wafer 1. The test of the IC 2 is performed by bringing the tip of the needle 45 attached to the probe card into contact with the pad 5 of the IC 2. The needle 45 has a function of bringing the IC tester and the IC 2 into electrical contact. I
The C tester determines the quality of IC2.

Next, based on the test results, bad marks are formed on ICs determined to be defective. Alternatively, the pass / fail judgment result is recorded on a floppy disk or the like together with the IC coordinate data. Next, an ultraviolet adhesive tape is adhered to the back surface of the silicon wafer. This tape is easily deformed elastically, and the adhesive strength can be controlled by irradiation with ultraviolet rays. When the silicon wafer is scribed, it is sufficiently adhered to the silicon wafer so as not to peel off.

Next, scribing is performed by repeating vertical and horizontal reciprocating motions along the scribe line 15 from the surface of the silicon wafer 1. The scribes spatially separate the ICs connected to each other by the silicon wafer. Next, as shown in FIG. 46B, the adhesive tape is two-dimensionally stretched along the tape surface. Then, each IC separated by the scribe further separates. Leave more than the width of the scribe line.

Next, as shown in FIG. 46 (c), the ICs 2 separated by the robot 7 are taken out and placed on the head substrate 14. The robot 7 is controlled by a computer 8. The computer 8 reads out the electrical characteristic data in the wafer of the probing test from the floppy disk 9, selects only non-defective products, and controls the robot to arrange the IC. Alternatively, a bad mark hit on a defective IC chip is image-recognized and only good products are selected.

In the present invention, for convenience, the IC chips adjacent on the wafer are diced, picked up by the robot 7 in order, and placed on the mounting board 14. If an adjacent IC chip is defective, a normal IC chip in the vicinity is arranged. At this time, by arranging the IC chips so as to be connected in order, the chips adjacent on the wafer can be also adjacent on the mounting substrate 14. For example, FIG.
(B), the lowermost good chips C in the next row are arranged in order from the uppermost good chip A in the rightmost column to the B chip IC. Then C
, And D and E in the same manner. On the way, when the mounting board 14 has been arranged, it is arranged on the next mounting board 14.

In the case of the image sensor IC, the sensitivity of the light receiving element varies within the silicon wafer. This is because
The sensitivity tends to change continuously within the wafer because it is considered that the heat distribution in the IC manufacturing process is non-uniform in the wafer surface and the thickness of the various insulating films is non-uniform. Therefore, if the distance between the light receiving elements on the wafer is short, the sensitivity difference may be small, and if the distance is long, the sensitivity difference may be large.

For example, in FIG. 46B, it is assumed that the sensitivity increases as going to the right. Here, for the sake of convenience, the order of picking up the IC chips is shown in FIG.
A case will be described in which three arrangements of 0, d1, d2, and d3 are provided on the mounting board. Output states when uniform light is applied to the mounting substrate 6 arranged so that the directions of the IC chips are in the same direction are as shown in FIGS. 51 (d1) to (d3). Indicates the order of pickup by IC. As can be seen from each of the figures, there is a sharp sensitivity difference between several adjacent IC chips. FIG.
(D1) to (d3) are output waveforms of the image sensor head of the present invention, and show the results of applying the present invention to FIGS. 51 (d1) to (d3), respectively. FIG. 52 (d1)
Is arranged by rotating the IC chip by 180 ° on the plane of the mounting substrate, and the scanning direction of the light receiving element in the IC chip is reversed. In FIG. 52 (d2), the IC chip is arranged by being rotated by 180 ° on the plane of the mounting substrate, and the scanning direction of the light receiving element in the IC chip is reversed. In FIG. 52 (d3), the IC chip is arranged by being rotated by 180 ° on the plane of the mounting substrate, and the scanning direction of the light receiving element in the IC chip is reversed. By doing so, a linear image sensor having an extremely small output difference between adjacent IC chips can be realized.
This is because adjacent light receiving elements between adjacent chips arranged on the mounting substrate 14 are arranged very close on the wafer. For example, a length of 8 mm and a width of 0.4
In the case of an IC of 1 mm, adjacent light receiving elements between adjacent chips are only 0.4 mm apart on the wafer, and are １ ／ of the distance between the light receiving elements at both ends in one chip, which is about 8 mm.
0.

As can be seen by comparing FIGS. 52 (d1) to 52 (d3), FIG. 52 (d1) in which an IC arranged in a direction perpendicular to the arrangement direction of the light receiving elements in the IC chip is picked up. Is more likely to reduce the non-uniformity of the sensitivity as a linear image sensor after being placed on the mounting board. FIG. 53 (a) shows a plan view of the linear image sensor head after the IC chip arrangement, showing the output state of FIG. 52 (d1). The scanning direction in the IC chip is also shown in the figure. The image sensor IC shown in FIG. 53A has an arrangement in which image information of a document is read via a 1: 1 lens (such as an SLA), and has a narrow gap between adjacent IC chips. In order to read image information one by one for each IC chip through a reduction lens without using the equal-magnification lens, the IC chip 2 'having a narrowed light receiving element arrangement interval is used as shown in FIG. 53 (b). Deploy. In the case of FIG. 53A, the wires 23 from the pads are on both sides of the light receiving element row, and the optical conditions differ between the IC chips. In order to obtain high image quality, as shown in FIG. 54A, the pads 5 are arranged on both sides so as to sandwich the light receiving element row, and the IC chip can be driven from either side. By using the IC chip, as shown in FIG. 54 (b), a linear image sensor can be realized only by disposing a wire on one side of the light receiving element row even when the present invention is applied.

In FIG. 52, since there is no portion where the sensitivity changes abruptly, it is sufficient to perform correction with no output correction or with an average value every few bits. Calculations are also easier. FIG.
(A) and FIG. 55 (b) show a linear image sensor of the present invention. FIG. 55A is a perspective view of a linear image sensor, and FIG. 55B is a cross-sectional view of a portion A in the figure. The light from the light source 72 passes through the transparent glass 71 to irradiate the original surface, and the reflected light showing the image information passes through the transparent glass 71, passes through the equal-magnification lens 73, enters the linear image sensor IC2, and reads the image information. . Case 75
Has a function of fixing other parts as well as shading.

As described above, according to the eleventh embodiment, an output step between adjacent chips can be reduced, an IC mounting substrate with less variation in sensitivity between adjacent light receiving elements can be manufactured, and complicated correction can be performed. The circuit was unnecessary, and an inexpensive application product was realized. Further, the present invention is more effective for a contact type linear image sensor having a wide reading width. A
To read a 4-size original, 27 IC chips having a reading length of 8 mm as described above had to be arranged, and the present invention greatly contributed to reduce non-uniformity.

Next, the color image sensor IC of the present invention
A twelfth embodiment will be described with reference to the drawings. FIG. 56 (a) is a plan view of a silicon wafer for obtaining an IC arranged on the IC mounting substrate of the present invention.

A plurality of ICs 2 and color filters having the same pattern are printed in a matrix on the surface of the silicon wafer 1 using ordinary photolithography technology. Each IC is separated by scribe lines provided vertically in the horizontal and vertical directions. The I of the present invention
The IC used for the C mounting board has a narrow width of, for example, 400 μm. The length of the IC is set to 5 mm to 15 mm in order to reduce the number of chips used for mounting. I
Processing is performed using a stepper to reduce the width of C.
Therefore, the length of the IC is 15m, the maximum transfer length of the stepper.
m. Further, in order to obtain a very thin and long chip, the length is kept within 15 mm to maintain the mechanical strength. The silicon wafer 1 is processed to a thickness of about 600 μm in the case of processing such as oxidation and etching in an IC process, and in the case of a 6-inch wafer. Since the IC is elongated, the IC can be efficiently printed and processed by using a large-diameter wafer of 6 inches or more. As wafers become larger in diameter, ICs are printed and processed with a wafer thickness of 400 μm or more in order to maintain the mechanical strength of the wafer.

FIG. 57 is a plan view of an IC arranged on the IC mounting board of the present invention. The IC 2 usually has six or more pads 5 for a power source, a control input / output terminal, and an image signal output terminal.
Are formed. In addition, the light receiving elements 32 of the same shape, each of which is composed of a phototransistor or a photodiode, are periodically arranged in plural numbers along the length direction of the chip.
The light receiving elements 32 are provided one-dimensionally at a reading pitch cycle along the scanning direction. The charge stored in the light receiving element is output from the image signal output terminal by sequentially scanning rightward from the leftmost light receiving element or sequentially scanning leftward from the rightmost light receiving element. It has become so. That is, it has a bidirectional scanning function. The width of the chip is, for example, 400 μm and the length is, for example, 8 mm, which is considerably elongated.

FIG. 58 is an enlarged view of a part of the surface of the silicon wafer 1.

Since the width of the IC is very thin, about 400 μm, it is necessary to lower the center of gravity in order to stably dispose the IC on a mounting board. Therefore, after the IC is printed on the front surface of the silicon wafer 1, the back surface of the silicon wafer 1 is thinned to about 350 μm by polishing (polishing).

Next, the wafer 1 is placed on the wafer stage of the prober, and the electrical characteristics of all ICs on the wafer are measured by a tester. FIG. 59 is an enlarged view of a central portion of a probe card attached to a prober for testing IC 2 in wafer 1. The test of the IC 2 is performed by bringing the tip of the needle 45 attached to the probe card into contact with the pad 5 of the IC 2. The needle 45 has a function of bringing the IC tester and the IC 2 into electrical contact. I
The C tester determines the quality of IC2.

Next, based on the test results, bad marks are formed on ICs determined to be defective. Alternatively, the pass / fail judgment result is recorded on a floppy disk or the like together with the IC coordinate data. Next, an ultraviolet adhesive tape is adhered to the back surface of the silicon wafer. This tape is easily deformed elastically, and the adhesive strength can be controlled by irradiation with ultraviolet rays. When the silicon wafer is scribed, it is sufficiently adhered to the silicon wafer so as not to peel off.

Next, scribing is performed by repeating vertical and horizontal reciprocating movements along the scribe line 15 from the surface of the silicon wafer 1. The scribes spatially separate the ICs connected to each other by the silicon wafer. Next, as shown in FIG. 56B, the adhesive tape is two-dimensionally stretched along the tape surface. Then, each IC separated by the scribe further separates. Leave more than the width of the scribe line.

Next, as shown in FIG. 56C, the ICs 2 separated from each other by the robot 7 are taken and placed on the head substrate 6. The robot 7 is controlled by a computer 8. The computer 8 reads out the electrical characteristic data in the wafer of the probing test from the floppy disk 9, selects only non-defective products, and controls the robot to arrange the IC. Alternatively, a bad mark hit on a defective IC chip is image-recognized and only good products are selected.

In the present invention, for convenience, the IC chips adjacent to each other on the wafer are diced and then sequentially picked up by the robot 7 and arranged on the mounting substrate 14. If an adjacent IC chip is defective, a normal IC chip in the vicinity is arranged. At this time, by arranging the IC chips so as to be connected in order, the chips adjacent on the wafer can be also adjacent on the mounting substrate 14. For example, FIG.
(B), the lowermost good chips C in the next row are arranged in order from the uppermost good chip A in the rightmost column to the B chip IC. Then C
, And D and E in the same manner. On the way, when the mounting board 14 has been arranged, it is arranged on the next mounting board 14.

In the case of the image sensor IC, the sensitivity of the light receiving element varies within the silicon wafer. This is because
The sensitivity tends to change continuously within the wafer because it is considered that the heat distribution in the IC manufacturing process is non-uniform in the wafer surface and the thickness of the various insulating films is non-uniform. Therefore, if the distance between the light receiving elements on the wafer is short, the sensitivity difference may be small, and if the distance is long, the sensitivity difference may be large.

For example, in FIG. 56B, it is assumed that the sensitivity increases as going to the right. Here, the order of picking up the IC chips is shown in FIG.
A case will be described in which three arrangements of 0, d1, d2, and d3 are provided on the mounting board. FIGS. 61 (d1) to 61 (d3) show output states when uniform light is applied to the mounting board 14 arranged so that the directions of the IC chips are the same. Indicates the order of pickup by IC. As can be seen from each of the figures, there is a sharp sensitivity difference between several adjacent IC chips. FIG. 62
(D1) to (d3) are output waveforms of the image sensor head of the present invention, and show the results of applying the present invention to FIGS. 61 (d1) to (d3), respectively. FIG. 62 (d1)
Is arranged by rotating the IC chip by 180 ° on the plane of the mounting substrate, and the scanning direction of the light receiving element in the IC chip is reversed. In FIG. 62 (d2), the IC chip is arranged by being rotated by 180 ° on the plane of the mounting substrate, and the scanning direction of the light receiving element in the IC chip is reversed. In FIG. 62 (d3), the IC chip is arranged by being rotated by 180 ° on the plane of the mounting substrate, and the scanning direction of the light receiving element in the IC chip is reversed. By doing so, a linear image sensor having an extremely small output difference between adjacent IC chips can be realized.
This is because adjacent light receiving elements between adjacent chips arranged on the mounting substrate 14 are arranged very close on the wafer. For example, a length of 8 mm and a width of 0.4
In the case of an IC of 1 mm, adjacent light receiving elements between adjacent chips are only 0.4 mm apart on the wafer, and are １ ／ of the distance between the light receiving elements at both ends in one chip, which is about 8 mm.
0.

Further, as can be seen by comparing FIGS. 62 (d1) to (d3), FIG. 62 (d1) in which an IC arranged in a direction perpendicular to the arrangement direction of the light receiving elements in the IC chip is picked up. Is more likely to reduce the non-uniformity of the sensitivity as a linear image sensor after being placed on the mounting board. FIG. 63 is a plan view of the linear image sensor after the IC chip is placed, showing the output state of FIG. 62 (d1).
(A). The scanning direction in the IC chip is also shown in the figure. The image sensor shown in FIG. 63A has an arrangement in which image information of a document is read via an equal-magnification lens (SLA or the like), and has a narrow gap between adjacent chips. In order to read image information one by one for each IC chip via a reduction lens without using the equal-magnification lens, the IC chip 2 ′ in which the arrangement interval of the light receiving elements is narrowed is used as shown in FIG.
It is arranged as shown in FIG. In the case of FIG. 63 (a), the wires 23 from the pads are on both sides of the light receiving element row, and the optical conditions differ between the IC chips. To obtain high image quality, FIG.
As shown in (a), pads are arranged on both sides so as to sandwich the light receiving element row, and the IC chip can be driven from either side. By using the IC chip, as shown in FIG. 64 (b), a linear image sensor can be realized only by disposing a wire on one side of the light receiving element row even when the present invention is applied.

In FIG. 62, there is no portion where the sensitivity changes suddenly. Therefore, it is sufficient to correct the output without correction or with the average value every several bits. Calculations are also easier. The case where the color filter which is one of the color separating means is formed on the light receiving element of the image sensor which is the reading means has been described above. 65 (a) and 65 (b) show the color linear image sensor unit at this time.
FIG. 65A is a perspective view of the color linear image sensor unit, and FIG.
(B). The light from the light source 72 passes through the transparent glass 71 and irradiates the original surface, and the reflected light passes through the transparent glass 71, passes through the equal-magnification lens 73, passes through the color filter 74, and is color-separated and enters the image sensor IC2. And read the color image information.

In addition to this, there is also a means for separating the color of the original to be read by blinking while switching three or more types of light sources having different wavelengths without using a color filter as one means of color separation means. Also, a linear image sensor as the reading means of the present invention is suitable, and a color linear image sensor unit at that time is shown in FIG. FIG. 66A is a perspective view of the color linear image sensor unit, and FIG. 66B is a sectional view of a portion B in the figure. Light from the light sources 72a, 72b, and 72c of different colors that blink while being switched is irradiated on the original surface through the transparent glass 71, and the reflected light there passes through the transparent glass 71 and the equal-magnification lens 73,
The light enters the image sensor IC2 and reads color image information.

As described above, according to the twelfth embodiment, an output step between adjacent chips can be reduced, an IC mounting substrate with less variation in sensitivity between adjacent light receiving elements can be manufactured, and complicated correction can be performed. No circuit was required, and inexpensive applied products such as color scanners were realized.

The present invention is more effective for a contact type linear image sensor having a wide reading width. A
To read a 4-size original, 27 IC chips having a reading length of 8 mm as described above had to be arranged, and the present invention greatly contributed to reduce non-uniformity.

Next, a method of manufacturing a semi-finished silicon wafer according to the present invention will be described as a thirteenth embodiment with reference to the drawings. FIG. 67 is a schematic cross-sectional view of a bad marking step showing the method for manufacturing a semi-finished silicon wafer of the present invention.

As shown in FIG. 67, a plurality of ICs are repeatedly formed in a matrix on a silicon wafer surface via scrub lines by a usual process before bad marks are formed on defective IC chips. On the surface of each IC, one-dimensionally the same transistors are arranged in the chip length direction.

For example, if the IC is a one-dimensional image sensor I
In the case of C, the phototransistor is provided in the multiple chip length direction of a multiple of 4 bits. I for thermal head
In the case of C, high breakdown voltage trouble transistors for resistance heating are provided one-dimensionally in a multiple of 4 bits in the chip length direction. The width of the chip is thinned to 400 μm or less for cost reduction. The width of the tip is the length from the scribe center to the scribe center. To reduce the chip width, the scribe line width was reduced to 60 μm or less. Also, I
The minimum processing width was set to 1.2 μm or less by using a stepper in the photolithography of C. It is difficult to provide alignment marks necessary for using a stepper on scribe lines of 60 μm or less. Therefore, the scribe line in the chip length direction was reduced to 60 μm or less, and the scribe line in the chip width direction was increased to 100 μm, which is the conventional value, to provide a mark for the thick scribe line.

With the above arrangement, the chip width becomes 28
It can be as thin as about 0 μm. The length varies depending on the required number of bits, but is generally 4 to 12 m longer than the chip width by one digit or more.
Lengths between m are common. After an IC is printed on the surface of the silicon wafer by a stepper, the back surface of the silicon wafer is polished to reduce the thickness of the silicon wafer. 6
In the case of an inch wafer, a silicon wafer of about 600 μm is thinned to about 300 to 400 μm.

Next, the electrical characteristics of all ICs on the surface of the silicon wafer are measured by an IC tester. A bad mark is provided on the surface of the defective IC chip by a marking process so that the defective product can be identified as a defective product. As shown in FIG. 67, the laser beam emitted by the YAG laser 10 is guided to the vicinity of the silicon wafer 1 by a thin optical fiber 17 having a diameter of 100 μm or less. Optical fiber 1
At the exit 7, a condenser lens 18 is provided at a distance of 1 to 2 cm from the surface of the silicon wafer 1. The laser beam emitted from the optical fiber 17 is irradiated on the defective chip of the silicon wafer 1 by the condenser lens 18. When a defective IC chip is irradiated with a laser beam, the temperature becomes locally high, and a heat-damaged region is formed on the surface of the defective chip to form a bad mark.

FIG. 68 is a plan view of a defective IC chip to which the bad mark 19 has been attached. According to the present invention, the size of the bad mark 19 is very small as compared with the conventional ink method, and can be formed with a diameter of 100 to 200 μm. Accordingly, a semi-finished silicon wafer having a chip width smaller than 400 μm can be formed. A bad mark can be reduced by a method of condensing a laser beam into a condensing lens close to an optical fiber and a silicon wafer.
When a bad mark is formed by a laser beam, there is a problem that fragments due to damage scatter to an adjacent chip.
However, by squeezing the laser beam into a very small area, it was possible to prevent the fragments from being scattered to the adjacent chip. In the embodiment, the wavelength of the YAG laser is 1.06 μm, and the pulse is driven at 10 pulses per second. The oscillation time width is 100 μsec and the output energy is 50 mJ.

Bad marks formed by laser irradiation are more difficult to distinguish than bad marks formed by ink. Therefore, FIG.
8, it is necessary to provide a bad mark near the bad mark with a pattern for bad mark identification. Generally, a pad or a thick aluminum wiring is used. By checking whether or not a bad mark exists near the bad mark identification pattern, the presence of the bad mark can be accurately checked.

As described above, the present invention has made it possible to form a silicon wafer composed of extremely fine chips by forming a bad mark small by laser irradiation. Further, the laser irradiation was transmitted to the silicon wafer through a thin optical fiber, and a condensing lens was provided in the vicinity of the silicon wafer, so that the laser beam was formed in a small spot and the bad mark could be reduced.

As described above, according to the thirteenth embodiment, since the bad mark was formed by thermal damage due to laser irradiation focused on a small area, 400 μm was obtained.
It is now possible to manufacture very thin ICs of less than m. Because of the extremely small size, the cost and size of the IC can be reduced.

Next, an electronic device according to the present invention will be described as a fourteenth embodiment with reference to the drawings. FIG. 69 is a plan view (FIG. 69 (a)) and a cross-sectional view (FIG. 6) of an electronic device in which a plurality of extremely elongated ICs 2 are linearly arranged on the surface of the substrate 1.
9 (b)). The substrate 14 has all the wiring printed on its surface, and receives power and signals from the outside. The wiring on the substrate 14 and each IC 2 are bonded via each pad terminal to form a bonding lead 23
Is electrically connected. The length of the IC is longer than 7 mm and the width is thinner than 0.35 mm. The thickness of the IC is formed as thin as 0.35 mm by back surface polishing. In particular, the width of the IC can be reduced to at least about 100 μm, which is the width of the pad, by performing various measures. That is, in the present invention, the width of the IC is formed smaller than the thickness.
Its width is very narrow, from 100 μm to 350 μm. In addition, the length is formed to be at least ten times as large as the width in application, and generally longer than twenty times seven mm. In addition, IC2
Are provided on the surface of the substrate 1 in a straight line at least 3 or more, generally 10 or more.

In the electronic device of the present invention, in order to mechanically leave such an IC having an unconventional structure in a stable state,
A support 30 is provided which is in mechanical contact with the length direction of each IC. The width of the support 30 is 1 mm or more, and the length is at least the length of each IC.
It is desirable that the length of the support 30 be equal to or longer than the sum of the plurality of ICs so that the plurality of ICs can be supported simultaneously.
The support 30 is mechanically supported at the bottom by the substrate 14. Each IC 2 is supported on its side by a support 30. The substrate 14 is also supported by the contact between the bottom of the IC 2 and the substrate 14. However, in the present invention, since the width of the IC is smaller than the thickness, the mechanical support is provided by the support 30 rather than the substrate 14. The contact area between the IC 2 and the support 30 is equal to the IC 2 and the substrate 1
4 because it is formed larger than the contact area.

As described above, according to the fourteenth embodiment, a very thin and long IC can be stably supported by the support. Very thin and long ICs are stably placed with a mechanical connection at the bottom to the substrate and a mechanical connection at the sides to the support. In an electronic device in which the width of the IC is smaller than the thickness, the IC is stably arranged on the support base rather than the substrate. Therefore, it has become possible to mount a micro IC that has been difficult in the past. As a result, the size and cost of the device can be reduced.

As the electronic device of the present invention, an image sensor or a thermal head for forming a facsimile is suitable.

Next, a fifteenth embodiment will be described. FIG. 71 is a plan view (FIG. 71 (a)) and a cross-sectional view (FIG. 71 (b)) of an electronic device in which a plurality of extremely elongated ICs 2 are linearly arranged on the surface of the substrate 1. The substrate 14 has all the wiring printed on its surface, and receives power and signals from the outside. The wiring on the substrate 14 and each IC 2 are bonded via respective pad terminals and are electrically connected by bonding leads 23. The length of the IC is longer than 7 mm and the width is thinner than 0.35 mm. The thickness of the IC is formed as thin as 0.35 mm by back surface polishing. In particular, the width of the IC can be reduced to at least about 100 μm, which is the width of the pad, by performing various measures. That is, in the present invention, the width of the IC is formed smaller than the thickness.
Its width is very narrow, from 100 μm to 350 μm. In addition, the length is formed to be at least ten times as large as the width in application, and generally longer than twenty times seven mm. In addition, IC2
Are provided on the surface of the substrate 1 in a straight line at least 3 or more, generally 10 or more.

In the electronic device of the present invention, in order to leave such an IC having an unconventional structure mechanically and stably,
A support groove 40 is provided along the length direction of the substrate 14. The width of the support groove 40 is formed larger than the width of the IC 2. Also, the length of the support groove 40 is longer than the length of the IC,
Generally, the length is substantially the same as that of the substrate 14 so that a plurality of ICs can be continuously arranged. The depth of the support groove 40 is larger than the width of the IC 2 in order to mechanically stabilize the IC 2 by bonding the IC 2 to the bottom of the support groove 40 by making it larger than the bonding area between the IC 2 and the bottom of the support groove 40. Have been. That is, the IC 2 is almost supported by bonding to the side of the support groove 40. Also, since the surface of the IC 2 and the surface of the substrate 14 are arranged on substantially the same plane,
Electrical connection between C2 and the wiring of the substrate 14 can be facilitated.

As the electronic device of the present invention, an image sensor and a thermal head used for FAX described in the related art are suitable. In particular, in an image sensor,
When the IC becomes very thin, there is a problem that not only light detection from the surface but also light detection noise from the side is added.

When the thickness of the IC2 is reduced, the distance between the side of the IC2 and the photosensor provided on the surface of the IC2 becomes short, and light detection noise from the side is generated. However, in the case of the electronic device of the present invention, the side portion of the IC 2 comes into contact with the support groove 40 to prevent light from entering. Therefore, noise due to the incidence of light from the side of the IC 2 can be prevented. The other side of IC2 cannot contact the groove. However, by disposing the photosensor in a direction in which it contacts the support groove 40 with respect to the width of the IC 2, it is possible to prevent the occurrence of light detection noise from the non-contact side. Although not shown, the support groove on the non-contact side may be chapped with an opaque liquid resin and solidified by heat treatment to support both sides of the IC 2 and prevent light from entering.

As described above, according to the fifteenth embodiment, a very thin and long IC can be stably supported by the groove provided in the substrate. The grooves not only position the IC, but also
The mechanical strength is improved by bonding C with the side of the groove. Further, in the case of a one-dimensional image sensor, there is an effect of preventing noise from being generated due to light irradiation on the side of the IC. Therefore, it has become possible to mount a micro IC that has been difficult in the past. As a result, the size and cost of the device can be reduced.

Next, a sixteenth embodiment will be described. Figure 72
FIG. 72A is a plan view (FIG. 72A) and a cross-sectional view (FIG. 72B) in which a plurality of extremely elongated ICs 2 are linearly arranged on the surface of the substrate 14. An electric connection plate 50 is provided, which is electrically connected via pads on the surface of the IC 2. IC
2 is mechanically stabilized by being arranged in contact between the substrate 14 and the electrical connection plate 50. Each IC2 has a length of more than 7 mm and a width of less than 0.35 mm. The thickness of the IC 2 is formed as thin as about 350 μm by backside polishing. The width of the IC 2 can be reduced to a pad size of about 100 μm. That is, the width of the IC of the electronic device of the present invention is smaller than the thickness, and is 100 to 350 μm.
Range. The length of the IC is generally 1
It is longer than 0 times, usually longer than 20 times 7 mm. Also,
Generally, five or more ICs are provided side by side, and most commonly, ten or more ICs are provided side by side to correspond to the width of A4 size paper.

In the electronic device of the present invention, in order to stably install a plurality of very elongated ICs as described above, an electric connection plate 50 is provided on the surface of the IC opposite to the substrate 14 to stabilize the IC. . Even if the width of the IC 2 is smaller than 0.35 mm, not only the bonding strength between the bottom of the IC 2 and the substrate 14 but also the bonding strength between the IC 2 and the electric connecting plate 50 and the distance between the electric connecting plate 50 and the substrate 14 Stabilized by pressure.
Therefore, the electric connection plate 50 functions not only as an electric connection but also as a support plate. It may be used only as a support plate having no electrical connection function. When used as a support plate,
It is necessary to stabilize the support plate itself.

FIG. 72 shows an embodiment in which the electric connection plate 50 as a support plate is fixed to the substrate 14 via the support base 39 and stabilized. That is, the support table 39 is stably set on the surface of the substrate 14 along the length direction beside the IC 2. The width of the support 39 is sufficiently larger than the width of the IC 2 in order to strongly fix the support to the substrate 14. According to the conventional results, the support itself can be stably installed if the width is 1 mm or more. Further, an electric connection plate 50 as a support plate is provided so as to bridge the support table 39 and the IC 2. Therefore, the height of the support table 39 is formed to be substantially the same as the thickness of the IC 2. As shown in FIG. 72, by providing the support base 39 by bonding to the IC 2, the IC 2
Extremely stable because it is supported by the three surfaces of the front and side. The electrical connection between the IC 2 and the electrical connection plate 50 can be made by providing a conductive film on one of the surfaces so as to protrude from the surface. Preferably, a conductive film made of an elastic material is good.
The electrical connection between the electrical connection plate 50 and the support or the substrate 14 is also made via a conductive film. By using an elastic material as the conductive film, the pressure on the IC 2 can be increased, so that the IC 2 can be mechanically stabilized.

FIG. 73 is a cross-sectional view in the width direction of the electronic device when the substrate 14 and the electric connection plate 50 are connected linearly.
A groove having the same thickness as that of the IC 2 is formed on the substrate 14, and the IC 2 is provided in contact with a side portion of the groove. Since the respective surfaces of the IC 2 and the substrate 14 are at the same height, connection by the electric connection plate 50 is possible. Also in FIG. 73, the electric connection plate 50 may be used not only for electric connection but also only as a support plate for stabilizing mechanical strength. In FIG. 73, the bottom and sides of the IC 2 are not only supported by the substrate 14 but also
The mechanical stability is improved by supporting the surface of the IC.

FIG. 74 is a cross-sectional view in the width direction of the electronic device when the electric connection plate 50 is supported with the same step as the thickness of the IC 2 provided. The electric connection plate 50 is stably installed in contact with the substrate 14 over a large area. The above-mentioned electric connection plate has a plate-like shape and enables electric connection to a plurality of pads simultaneously. As a material, a mechanically strong silicon single crystal is preferable. In an electronic device in which a photosensor is provided on the surface of the IC 2, it is necessary to transmit light.
Therefore, the electrical connection plate is preferably a glass plate of a transparent substrate.
In addition, since the IC and the electrical connection plate are in a planar contact structure, the size of the pad of the IC 2 can be reduced. If the pad is made smaller, the width of the IC 2 itself can be made smaller, and the present invention can be more effectively implemented.

As described above, in the electronic device according to the sixteenth embodiment, in order to obtain the mechanical strength of each of the very thin and long ICs, the IC can be made to have a sandwich structure of the substrate and the support table, and the strength can be twice or more. I made it. Further, since the support has a function as an electric connection plate, there is an effect of reducing mounting cost.

The first embodiment to the sixteenth embodiment shown in the above description
The embodiments can be implemented in various combinations.

[0225]

The image sensor IC of the present invention is arranged so that the circuit can be formed into a pattern elongated in the scanning direction, so that the width of the chip is larger than the chip thickness which could not be predicted by the conventional technology. A narrow chip was realized. Further, by using this very thin IC, a compact IC mounting board with less variation among ICs can be manufactured at low cost. Further, mounting of an IC on a cylindrical substrate, which has been difficult until now, can be easily performed.

As a result, a compact and low-cost electronic device such as a multi-chip image sensor or a multi-chip thermal head has become possible. Therefore, it has become possible to reduce the cost, which has been difficult in the past, and to realize an inexpensive FAX.

[Brief description of the drawings]

FIG. 1 is a plan view of a circuit block of an image sensor IC according to the present invention.

FIG. 2 is a plan view of a circuit block of a conventional image sensor IC.

FIG. 3 is an electric circuit diagram of the image sensor IC of the present invention.

FIG. 4 is an electric circuit diagram of the image sensor IC of the present invention.

FIG. 5 is an electric circuit diagram of the image sensor IC of the present invention.

FIG. 6 is a timing chart of the image sensor IC of the present invention.

FIG. 7 is a cross-sectional view of the image sensor IC of the present invention.

FIG. 8 is a cross-sectional view of the image sensor IC of the present invention.

FIG. 9 is a plan view of one read cycle circuit block of the image sensor IC of the present invention.

FIG. 10 shows a facsimile using the image sensor IC of the present invention.
FIG. 3 is a perspective view of a sensor head for use.

FIG. 11 is a plan view showing an arrangement of a read cycle circuit block of the image sensor IC of the present invention.

FIG. 12 is a plan view of a photo sensor at an end in a scanning direction of the image sensor IC of the present invention.

FIG. 13 is a plan view of a circuit block of the image sensor IC of the present invention.

FIG. 14 is a plan view of one read cycle circuit block of the image sensor IC of the present invention.

FIG. 15 is a plan view showing an arrangement of a read cycle circuit block of the image sensor IC of the present invention.

FIG. 16 is a plan view of a photo sensor at an end in the scanning direction of the image sensor IC of the present invention.

FIG. 17 is a plan view of a circuit block of the image sensor IC of the present invention.

FIG. 18 is a plan view of one read cycle circuit block of the image sensor IC of the present invention.

FIG. 19 is a plan view showing an arrangement of a read cycle circuit block of the image sensor IC of the present invention.

FIG. 20 is a plan view of a photo sensor at an end in a scanning direction of the image sensor IC of the present invention.

FIG. 21 is a plan view of one read cycle circuit block of the image sensor IC of the present invention.

FIG. 22 is a plan view of a photosensor at the scanning direction end of the image sensor IC according to the present invention.

FIG. 23 is a plan view of one read cycle circuit block of the image sensor IC of the present invention.

FIG. 24 is a plan view showing an arrangement of a read cycle circuit block of the image sensor IC of the present invention.

FIG. 25 is a plan view showing a pad shape of the image sensor IC of the present invention.

FIG. 26 is a plan view showing a pad shape of the image sensor IC of the present invention.

FIG. 27 is a plan view showing a pad shape of the image sensor IC of the present invention.

FIG. 28 is a plan view showing the image sensor IC of the present invention at the time of inspection.

FIG. 29 is a cross-sectional view showing the image sensor IC of the present invention at the time of inspection.

FIG. 30 is a plan view showing a probe trace of a pad at the time of inspection of the image sensor IC of the present invention.

FIG. 31 is a schematic diagram of a circuit of the image sensor of the present invention.

FIG. 32 is a schematic diagram of a circuit of the image sensor of the present invention.

FIG. 33 is a time chart of the circuit of the image sensor of the present invention.

FIG. 34 is a schematic diagram of a circuit of the image sensor of the present invention.

FIG. 35 is a schematic diagram of a circuit of the image sensor of the present invention.

FIG. 36 is a schematic diagram of a circuit of the image sensor of the present invention.

FIG. 37 is a time chart of a circuit of the image sensor of the present invention.

FIGS. 38A and 38B are views showing a process of a conventional method for manufacturing an IC mounting substrate, in which FIG. 38A is a plan view of a silicon wafer;
(B) is a plan view in which chips are put in a tray, and (c)
FIG. 2 is a perspective view of the completed IC mounting board.

FIG. 39 is a view showing the order of steps of the method for manufacturing an IC mounting board according to the present invention, wherein (a) is a plan view of a silicon wafer,
(B) is a plan view after scribing, and (c) is an explanatory view in which an IC is installed on a mounting board.

FIG. 40 is a plan view of an IC used for the IC mounting board of the present invention.

FIG. 41 is a perspective view of an IC mounting board according to the present invention.

FIG. 42 is an enlarged view of a part of the surface of the silicon wafer of the present invention.

FIG. 43 is an enlarged view of a central portion of the probe card of the present invention.

FIG. 44 is an output waveform of a conventional image sensor head.

FIG. 45 is an output waveform of the image sensor head of the present invention.

FIGS. 46A and 46B are diagrams showing the order of steps of the method for manufacturing an IC mounting substrate according to the present invention, wherein FIG.
(B) is a plan view after scribing, and (c) is an explanatory view in which an IC is installed on a mounting board.

FIG. 47 is a plan view of an IC used for the IC mounting board of the present invention.

FIG. 48 is an enlarged view of a part of the surface of the silicon wafer of the present invention.

FIG. 49 is an enlarged view of a central portion of the probe card of the present invention.

FIG. 50 is a plan view showing the order of picking up ICs from a silicon wafer.

FIG. 51 is an output waveform of a conventional image sensor head.

FIG. 52 is an output waveform of the image sensor head of the present invention.

FIG. 53 is a plan view of the image sensor head of the present invention.

FIG. 54 (a) is a plan view of another image sensor IC of the present invention. (B) is a plan view of an image sensor head using the image sensor IC of (a).

FIG. 55 (a) is a perspective view of a linear image sensor of the present invention. (B) is a sectional view of a portion A of the linear image sensor of (a).

FIG. 56 is a view showing the order of the steps of the method for manufacturing an IC mounting substrate according to the present invention, wherein (a) is a plan view of a silicon wafer,
(B) is a plan view after scribing, and (c) is an explanatory view in which an IC is installed on a mounting board.

FIG. 57 is a plan view of an IC used for the IC mounting board of the present invention.

FIG. 58 is an enlarged view of a portion of the surface of the silicon wafer of the present invention.

FIG. 59 is an enlarged view of a central portion of the probe card of the present invention.

FIG. 60 is a plan view showing the order of picking up ICs from a silicon wafer.

FIG. 61 is an output waveform of a conventional image sensor head.

FIG. 62 is an output waveform of the image sensor head of the present invention.

FIG. 63 is a plan view of a conventional image sensor head.

FIG. 64A is a plan view of another image sensor IC of the present invention. (B) is a plan view of an image sensor head using the image sensor IC of (a).

FIG. 65 (a) is a perspective view of a color linear image sensor unit of the present invention. FIG. 2B is a cross-sectional view of a portion A of the color linear image sensor of FIG.

FIG. 66 (a) is a perspective view of another color linear image sensor unit of the present invention. (B) is a sectional view of a portion B of the color linear image sensor of (a).

FIG. 67 is a schematic sectional view showing the method for manufacturing a semi-finished silicon wafer of the present invention.

FIG. 68 is a plan view of a semi-finished silicon wafer of the present invention.

FIGS. 69 (a) and (b) are a plan view and a cross-sectional view, respectively, of an electronic device of the present invention.

FIGS. 70A and 70B are a plan view and a cross-sectional view of a conventional electronic device, respectively.

FIGS. 71 (a) and (b) are a plan view and a cross-sectional view of an electronic device of the present invention, respectively.

FIGS. 72A and 72B are a plan view and a cross-sectional view of an electronic device of the present invention, respectively.

FIG. 73 is a cross-sectional view of the electronic device of the present invention.

FIG. 74 is a cross-sectional view of the electronic device of the present invention.

[Explanation of symbols]

 2 Image Sensor IC 20 Phototransistor and Switch Transistor Row 3 Scanning Circuit Row 4 Drive Circuit 5 Pad 21 Phototransistor Row 22 Switch Transistor Row 111 N-Silicon Substrate 112 P-Base Diffusion Layer 113 P + Diffusion Layer 114 N + Diffusion Layer 115 LOCOS Oxidation Film 115 116 N ± Separation layer 117 AL 118 Intermediate insulating layer 119 Passivation film 120 Chip edge S Photoelectric conversion element PCLK Clock pulse SW Switching element PSI Start pulse SL Common line PSW Switching element control pulse G Read gate PG Read gate control pulse RG reset gate PRG reset gate control pulse SC scanning circuit VSIG signal output FF flip-flop CC control circuit SIG signal output Child

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/66 H01L 21/66 A X 27/146 H05K 1/18 S 27/14 H01L 27/14 A H05K 1/18 D ( 72) Inventor Yoshikazu Kojima 1-8-8 Nakase, Mihama-ku, Chiba City, Chiba Pref. (72) Inventor Norito Ando 1-8-8 Nakase, Mihama-ku, Chiba-shi Chiba Pref.

Claims (42)

[Claims] An image sensor circuit comprising a plurality of switch circuits connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit is formed on a chip surface. A linear image sensor IC, wherein the relationship among the thickness Z, the length X in the scanning direction, and the width Y of the linear image sensor IC is Y ≦ Z <X. 2. The linear image sensor IC according to claim 1, wherein Y ≦ 350 μm. 3. A linear image sensor circuit comprising a plurality of switch circuits respectively connected in series with a plurality of light receiving elements, a scanning circuit for sequentially switching the switch circuits, and a driving circuit for operating the scanning circuit is formed on a chip surface. In the linear image sensor IC, the tip of the probe that comes into contact with the pad electrode for inspection is made to enter almost parallel to the main scanning direction of the linear image sensor IC, and the pad electrode attached by the tip of the probe is An image sensor I, wherein the length of the scar in the main scanning direction is longer than the length of the scar in the sub-scanning direction.
C. 4. A plurality of photoelectric conversion elements arranged linearly on a semiconductor substrate for reading image information, and an input terminal connected to the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. In a linear image sensor composed of a plurality of switching elements connected to each other and a scanning circuit that drives a control terminal of the switching element, an output terminal of the switching element is connected to a common line, and the common line is reset. A linear image sensor connected to an input terminal of a gate, and an output terminal of the reset gate is connected to a reset power supply terminal. 5. A plurality of photoelectric conversion elements for reading image information arranged linearly on a semiconductor substrate, and an input terminal connected to the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. In a linear image sensor comprising a plurality of switching elements connected to each other and a scanning circuit for driving a control terminal of the switching element, an output terminal of the switching element is connected to an input terminal of a reset gate, and the reset gate Is connected to a reset power supply terminal, and the scanning circuit is connected to 1 / fCK
Driving with a clock pulse of a second cycle, synchronizing with the control of the switching element, controlling the reset gate to read a signal from the photoelectric conversion element, and setting the output terminal of the photoelectric conversion element to a reset potential for 1 / fCK seconds or more. A linear image sensor fixed to a linear image sensor. 6. A plurality of photoelectric conversion elements arranged linearly on a semiconductor substrate for reading image information, and an input terminal connected to the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. And a scanning circuit for driving a control terminal of the switching element, wherein the scanning circuit is driven by a clock pulse having a period of 1 / fCK seconds. Inputting data of 2 / fCK seconds or more to the controller, synchronizing with the control of the switching element, controlling the reset gate to read a signal from the photoelectric conversion element, and keeping the conduction state of the switching element longer than the reading period. A linear image sensor characterized by the following. 7. A plurality of photoelectric conversion elements for reading image information arranged linearly on a semiconductor substrate, and an input terminal connected to the photoelectric conversion element for reading out a signal obtained by the photoelectric conversion element to the outside. In a linear image sensor including a plurality of switching elements connected to each other and a scanning circuit that drives a control terminal of the switching element, an output terminal of the switching element is connected to a common line, and the common line is connected to a plurality of common lines. This arrangement connects each of the common lines to an input terminal of a reset gate, connects an output terminal of the reset gate to a reset power supply terminal, and switches the switching element from a non-conductive state to a conductive state to perform reading. A common line other than the common line in a conductive state with the output terminal of the photoelectric conversion element has a fixed potential. Linear image sensor. 8. An IC mounting method comprising the steps of repeatedly forming a plurality of ICs in a matrix on the surface of a silicon wafer, cutting the silicon wafer, and arranging the ICs one-dimensionally on a mounting substrate. Substrate manufacturing method. 9. A step of repeatedly forming a plurality of ICs in a matrix on a surface of a silicon wafer, a step of bonding a tape to a back surface of the silicon wafer, a step of cutting the silicon wafer, and a step of mounting the IC on a mounting substrate. And a step of one-dimensionally disposing them on a substrate. 10. The method according to claim 9, wherein the tape controls the adhesive strength with the silicon wafer by irradiating ultraviolet rays.
A method for manufacturing a C mounting board. 11. A step of repeatedly forming a plurality of ICs in a matrix on the surface of a silicon wafer, and measuring electrical characteristics of the ICs and electrically converting data of the electrical characteristics in accordance with the matrix coordinates. An IC comprising: a probe test step of writing in a readable storage means; a step of cutting the silicon wafer; and a step of one-dimensionally arranging the ICs sequentially selected in accordance with data in the storage means on a mounting substrate. Manufacturing method of mounting board. 12. A step of repeatedly forming a plurality of linear image sensor ICs in a matrix on the surface of a silicon wafer, a probe test step of measuring electric characteristics of the IC, and cutting the silicon wafer to form a space between the ICs. A method for manufacturing a linear image sensor IC, comprising the steps of:
Forming a linear image sensor IC, wherein the ICs adjacent to each other in the direction in which the light receiving elements of the ICs are arranged and in the vertical direction have a point-symmetric relationship with each other. 13. The linear image according to claim 12, wherein, in the probe test step, the ICs adjacent to each other in a direction perpendicular to the direction in which the light receiving elements of the ICs are arranged are simultaneously probed by two chips for testing. Manufacturing method of sensor IC. 14. The method of claim 12, wherein the I is produced by the method of claim 12.
C. A method of manufacturing an IC mounting substrate, comprising a step of one-dimensionally arranging C on a mounting substrate, wherein the ICs vertically adjacent to a direction in which pixels of the IC are arranged on the surface of the silicon wafer are adjacent to each other. A method for manufacturing an IC mounting board, comprising: disposing. 15. In a silicon wafer on which a plurality of linear image sensor ICs are repeatedly formed in a matrix, the ICs adjacent to each other in the direction in which the light receiving elements of the ICs are arranged and in the vertical direction have a point-symmetric relationship with each other. A silicon wafer characterized by being formed. 16. A multi-chip in which a linear image sensor IC in which a plurality of light receiving elements are arranged one-dimensionally and a plurality of chips are arranged on a mounting substrate at substantially equal intervals in the arrangement direction of the light receiving elements. A linear image sensor, wherein the linear image sensor IC has a bidirectional scanning function. 17. A multi-chip in which a plurality of light-receiving elements are arranged one-dimensionally and a plurality of chips are arranged on a mounting board at substantially equal intervals in the arrangement direction of the light-receiving elements. Linear image sensor, wherein the linear image sensor IC has a bidirectional scanning function, and the linear image sensors I
The linear image sensor IC of one chip of at least one pair of C is arranged to be rotated by 180 degrees on the plane of the mounting substrate with respect to the other linear image sensor IC of the pair. Linear image sensor. 18. A multi-chip linear image sensor according to claim 42, wherein said linear image sensor IC is cut out from a silicon wafer having a plurality of linear image sensor ICs arranged in a matrix.
In a manufacturing method for manufacturing a chip-type linear image sensor, at least one pair of the linear image sensor ICs that are adjacent in the vertical direction with respect to the arrangement direction in which light receiving elements are arranged or that are close in the vertical direction are cut out from the silicon wafer. The linear image sensor ICs of one chip of at least one of the pairs are arranged so as to be adjacent to each other, and are rotated by 180 degrees on the plane of the mounting substrate with respect to the other linear image sensor ICs of the pair. 17. The method for manufacturing a linear image sensor according to claim 16, wherein: 19. A manufacturing method for manufacturing the multi-chip type linear image sensor by cutting out from a silicon wafer having a plurality of the linear image sensor ICs according to claim 16 arranged in a matrix.
The linear image sensor IC rotated by 80 degrees is the linear image sensor IC that is adjacent to the silicon wafer in the direction perpendicular to the arrangement direction in which the light receiving elements are arranged, or that is adjacent in the vertical direction. 43
A manufacturing method of the linear image sensor described in the above. 20. In the linear image sensor IC, an input / output terminal including a power supply of the linear image sensor IC is arranged along a line of the light receiving elements and with the light receiving elements interposed therebetween. The linear image sensor according to claim 17, wherein: 21. The multi-chip linear image sensor according to claim 42, wherein said linear image sensor IC is cut out from a silicon wafer having a plurality of linear image sensor ICs arranged in a matrix. Or at least one pair of the linear image sensor ICs that are adjacent in the vertical direction with respect to the arrangement direction in which the linear image sensors are arranged are cut out and arranged so that they are adjacent to each other, and at least one of the pairs The one-chip linear image sensor IC is arranged so as to be rotated by 180 degrees on the mounting substrate plane with respect to the other linear image sensor IC to be paired, and the scanning direction in the linear image sensor IC is also reversed. Claim 1.
8. The linear image sensor according to 8. 22. A method for manufacturing a multi-chip type linear image sensor by cutting out a plurality of linear image sensor ICs from a silicon wafer having a plurality of linear image sensor ICs arranged in a matrix, From the silicon wafer,
The linear image sensor I which is adjacent in the vertical direction to the arrangement direction in which the light receiving elements are arranged or in the vertical direction.
17. The linear image sensor according to claim 16, wherein C and the scanning direction in the linear image sensor IC are opposite. 23. A reading means comprising a linear image sensor IC in which a plurality of light receiving elements are arranged one-dimensionally and a plurality of chips arranged on a mounting substrate at substantially equal intervals in the arrangement direction of the light receiving elements. A color linear image sensor unit comprising a multi-chip type linear image sensor and color separation means including a light source and a lens, wherein the linear image sensor IC has a bidirectional scanning function. unit. 24. A reading means comprising a linear image sensor IC in which a plurality of light receiving elements are arranged one-dimensionally and a plurality of chips arranged on a mounting board at substantially equal intervals in the arrangement direction of the light receiving elements. In a color linear image sensor unit comprising a multi-chip linear image sensor and color separation means including a light source and a lens, the linear image sensor IC has a bidirectional scanning function,
In addition, one chip linear image sensor IC of at least one pair of linear image sensor ICs adjacent to each other is arranged by being rotated by 180 degrees on the mounting substrate plane with respect to another pair of linear image sensor ICs. A color linear image sensor unit characterized by being performed. 25. A method for manufacturing a multi-chip linear image sensor according to claim 49, wherein the linear image sensor IC is cut out from a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix. At least one or more pairs of the linear image sensor ICs which are vertically adjacent to the arrangement direction in which the light receiving elements are arranged or which are adjacent in the vertical direction are cut out and arranged so as to be adjacent to each other. 24. The color linear image sensor according to claim 23, wherein the one-chip linear image sensor IC is arranged to be rotated by 180 degrees on the plane of the mounting substrate with respect to another pair of linear image sensor ICs. Unit manufacturing method. 26. The method of manufacturing a multi-chip linear image sensor according to claim 50, wherein the linear image sensor IC is cut out from a silicon wafer having a plurality of linear image sensor ICs arranged in a matrix.
The linear image sensor IC to be rotated by an angle is the linear image sensor IC that is vertically adjacent to the arrangement direction in which the light receiving elements are arranged from the silicon wafer or that is vertically adjacent to the silicon wafer. 24
A method for manufacturing the color linear image sensor unit described in the above. 27. In a linear image sensor IC,
3. An input / output terminal including a power supply of the linear image sensor IC is arranged along a line of the light receiving elements and with the light receiving elements interposed therebetween.
4. A color linear image sensor unit according to item 4. 28. A method of manufacturing a multi-chip type linear image sensor by cutting out a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix form, wherein the silicon wafer is arranged in a direction in which light receiving elements are arranged. At least one pair of the linear image sensor ICs which are vertically adjacent to or adjacent to each other in the vertical direction are cut out and arranged so that they are adjacent to each other,
The linear image sensor IC of one chip of at least one of the pairs is arranged by being rotated by 180 degrees on the plane of the mounting substrate with respect to the other linear image sensor IC of the pair, and The method of manufacturing a color linear image sensor unit according to claim 23, wherein the scanning direction in the sensor IC is also reversed. 29. A method of manufacturing a multi-chip type linear image sensor by cutting out a silicon wafer in which a plurality of linear image sensor ICs are arranged in a matrix, wherein the linear image sensor IC rotated by 180 degrees is: The linear image sensor IC which is vertically adjacent to the arrangement direction in which the light receiving elements are arranged from the silicon wafer or which is adjacent in the vertical direction.
25. The method for manufacturing a color linear image sensor unit according to claim 24, wherein the scanning direction in the linear image sensor IC is also reversed. 30. In a semi-finished silicon wafer in which ICs are repeatedly provided in a matrix form on the surface of a silicon wafer, the ICs are composed of a plurality of light receiving elements or transistors arranged one-dimensionally and repeatedly. With a diameter of 1 on the surface of at least one of the ICs.
A semi-finished silicon wafer having a bad mark of 00 to 200 μm. 31. A step of repeatedly forming a plurality of ICs in a matrix form on a surface of a silicon wafer, a probe test step of measuring electric characteristics of the IC, and forming a bad mark on a defective IC. A semi-finished product of a silicon wafer, wherein the marking step controls the bad mark to have a diameter of 100 to 200 μm by laser irradiation. Production method. 32. The marking step includes: emitting a laser beam from a YAG laser; transmitting the laser beam to the vicinity of the silicon wafer through an optical fiber having a diameter smaller than 100 μm; and engineering the laser beam from the optical fiber by using an engineering lens. 32. The method of manufacturing a semi-finished silicon wafer according to claim 31, comprising the step of forming a heat-damaged region by condensing light on the surface of the IC. 33. An electronic device, comprising: a support base and an IC provided on a substrate so as to be in contact with each other along a length direction, wherein the width of the IC is smaller than the thickness. 34. The electronic device according to claim 33, wherein the length of the IC is at least 20 times the width. 35. The electronic device according to claim 34, wherein three or more of the ICs are linearly arranged along a length direction of the substrate. 36. A semiconductor device comprising: a substrate provided with a groove linearly in a length direction; and an IC disposed so as to contact a side portion of the groove, wherein the width of the IC is smaller than the thickness. Electronic devices. 37. The electronic device according to claim 36, wherein the IC has a larger contact area with a side portion of the groove than a contact area with a bottom portion of the groove. 38. The electronic device according to claim 37, wherein the width of the IC is smaller than 0.35 mm. 39. An elongated IC on a flat and elongated substrate surface.
Are linearly arranged in the electronic device.
An electronic device, wherein an electronic circuit is formed on a surface of C, and an adhesion area between a side portion of the IC and the substrate is larger than an adhesion area between a bottom portion of the IC and the substrate. . 40. An electronic device comprising a substrate on which electric wiring is printed and an IC provided on a surface of the substrate, wherein the width of the IC is longer and thinner than the thickness, and the IC and the substrate An electronic device, wherein electrical connection with the electronic device is made via an electrical connection plate. 41. The electronic device according to claim 40, further comprising a support provided on a surface of the substrate in contact with the IC. 42. The electronic device according to claim 41, wherein the electric connection plate is provided so as to bridge a surface of the IC and the support base.