JPH11284032A - Flip-chip connection method and structure - Google Patents
Flip-chip connection method and structureInfo
- Publication number
- JPH11284032A JPH11284032A JP9857698A JP9857698A JPH11284032A JP H11284032 A JPH11284032 A JP H11284032A JP 9857698 A JP9857698 A JP 9857698A JP 9857698 A JP9857698 A JP 9857698A JP H11284032 A JPH11284032 A JP H11284032A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- connection
- chip
- flip
- solder resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はフリップチップ接続
方法とフリップチップ接続構造に関する。The present invention relates to a flip-chip connection method and a flip-chip connection structure.
【０００２】[0002]
【従来の技術】従来のフリップチップ接続構造では、図
６に示すように、プリント回路の電極パターン３の端部
に設けられ、搭載接続される半導体チップとの接続部分
の外側より、半導体チップの搭載領域以外の基板１の全
面には、一様な厚みのソルダーレジスト７が被覆配設さ
れ形成されている。そして、この基板１に対して、図５
に示すように、基板１のプリント回路の電極パターン３
の端部が、金や半田などの導電材で形成されるバンプ５
を介して、半導体チップ２と加熱や加圧など、バンプ５
の材質に応じた方法で接続され、接続部のフラックスな
どの接続劣化異物を洗浄した後に、半導体チップ２と基
板１との間隙に封止樹脂が注入され硬化処理されてい
る。2. Description of the Related Art In a conventional flip-chip connection structure, as shown in FIG. 6, a semiconductor chip provided at an end of an electrode pattern 3 of a printed circuit and connected to a semiconductor chip to be mounted and connected is provided. A solder resist 7 having a uniform thickness is coated and formed on the entire surface of the substrate 1 other than the mounting area. Then, with respect to this substrate 1, FIG.
As shown in FIG.
5 is formed of a conductive material such as gold or solder.
Through the bumps 5 such as heating and pressing with the semiconductor chip 2
After the connection deteriorating foreign matter such as the flux at the connection portion is cleaned, a sealing resin is injected into the gap between the semiconductor chip 2 and the substrate 1 and hardened.
【０００３】この従来のフリップチップ接続構造では、
接続ピッチが小さくなると、バンプ５の直径が小さくな
り、図７に示すように、バンプ５の高さが例えば４０〜
５０μｍと小さくなると、半導体チップ２とソルダーレ
ジスト７間の間隔ｄがかなり小さくなり、電極パターン
３とバンプ５の接続部分の洗浄が充分に行なえなくな
り、封止樹脂６の流入時にも、基板１と半導体チップ２
間に封止樹脂６が完全に流入せず、硬化後に気泡が残存
する状態となる。In this conventional flip chip connection structure,
As the connection pitch decreases, the diameter of the bump 5 decreases, and as shown in FIG.
When the thickness is reduced to 50 μm, the distance d between the semiconductor chip 2 and the solder resist 7 becomes considerably small, so that the connection between the electrode pattern 3 and the bump 5 cannot be sufficiently cleaned. Semiconductor chip 2
The sealing resin 6 does not completely flow in between, and bubbles remain after curing.
【０００４】このようにフリップチップ接続構造内に、
フラックスなどの接続劣化異物や気泡が残存している
と、残存する接続劣化異物により、腐食が発生して動作
寿命が短縮したり、残存する気泡により接続が不安定に
なることがある。As described above, in the flip chip connection structure,
If connection deterioration foreign matter such as flux or bubbles remain, the remaining connection deterioration foreign matter may cause corrosion and shorten the operation life, or the connection may become unstable due to the remaining bubbles.
【０００５】[0005]
【発明が解決しようとする課題】前述した従来のフリッ
プチップ接続構造での問題を解決するために、特開平５
−１４４８１６号公報において、電極パターンの端部の
半導体チップの接続部を、ソルダーレジストより高く形
成したフェイスダウンボンディング方法が開示されてい
る。In order to solve the above-mentioned problems in the conventional flip-chip connection structure, Japanese Patent Laid-Open Publication No.
JP-A-144816 discloses a face-down bonding method in which a connection portion of a semiconductor chip at an end of an electrode pattern is formed higher than a solder resist.
【０００６】しかし、この開示の方法では、基板の作成
時に、通常の基板形状を形成した後に、さらに、メッキ
工程などにより、電極パターンの端部を形成する必要が
あり、追加工程を施すために製造工程が延長され、さら
に、メッキ廃液の処理などの設備が必要になり製造コス
トも増大することになる。However, according to the method of this disclosure, it is necessary to form an ordinary substrate shape at the time of forming the substrate, and then form an end portion of the electrode pattern by a plating process or the like. The manufacturing process is extended, and furthermore, equipment such as treatment of plating waste liquid is required, which increases the manufacturing cost.
【０００７】本発明は、前述したようなフリップチップ
接続構造の現状に鑑みてなされたものであり、その第１
の目的は、半導体チップとの接続ピッチが小さくなり、
バンプの直径が小さくなつても、電極パターンの接続部
の洗浄と、基板と半導体チップ間の樹脂による封止と
を、簡単且つ完全に行なうことが可能なフリップチップ
接続方法を提供することにある。The present invention has been made in view of the present situation of the flip chip connection structure as described above,
The purpose is to reduce the connection pitch with the semiconductor chip,
It is an object of the present invention to provide a flip chip connection method capable of easily and completely cleaning a connection portion of an electrode pattern and sealing with a resin between a substrate and a semiconductor chip even when the diameter of a bump is small. .
【０００８】また、本発明の第２の目的は、半導体チッ
プとの接続ピッチが小さくなり、バンプの直径が小さく
なつても、内部に接続劣化異物や気泡が残存せずに簡単
に構成されるフリップチップ接続構造を提供することに
ある。A second object of the present invention is to provide a simple configuration without connection deteriorating foreign matter or bubbles remaining inside even if the connection pitch with the semiconductor chip is reduced and the diameter of the bump is reduced. It is to provide a flip chip connection structure.
【０００９】[0009]
【課題を解決するための手段】前記第１の目的を達成す
るために、請求項１記載の発明は、プリント回路の電極
パターンの半導体チップとの接続部以外の前記半導体チ
ップの外側領域が、ソルダーレジスト膜で覆われる基板
に対して、前記半導体チップを前記接続部に導電性のバ
ンブを介して接続し、該接続に伴って生じる接続劣化異
物を洗浄後に、前記基板と前記半導体チップ間の間隙領
域及びその周辺部を樹脂により封止するフリップチップ
接続方法において、前記半導体チップの隅部に対向し、
前記電極パターンが形成されていない基板位置に対し
て、形成されるソルダーレジスト膜の膜厚が他部分より
も薄いか、またはソルダーレジスト膜が形成されない膜
調整部を設けるソルダーレジスト膜調整ステップと該ソ
ルダーレジスト膜調整ステップで設けられた膜調整部よ
り前記樹脂による封止を行なう樹脂封止ステップとを有
することを特徴とするものである。In order to achieve the first object, according to the present invention, an outer region of the semiconductor chip other than a connection portion of an electrode pattern of a printed circuit with the semiconductor chip is provided. The semiconductor chip is connected to the connection portion via a conductive bump with respect to the substrate covered with the solder resist film, and after the connection deteriorating foreign matter caused by the connection is washed, the semiconductor chip is connected between the substrate and the semiconductor chip. In the flip chip connection method of sealing a gap region and a peripheral portion thereof with a resin, the flip region is opposed to a corner of the semiconductor chip,
For a substrate position where the electrode pattern is not formed, the thickness of the formed solder resist film is smaller than other portions, or a solder resist film adjusting step of providing a film adjusting portion where the solder resist film is not formed, And a resin sealing step of sealing with the resin from a film adjusting section provided in the solder resist film adjusting step.
【００１０】同様に前記第１の目的を達成するために、
請求項２記載の発明は、請求項１記載の発明に対して、
前記半導体チップに対向する前記基板の領域に、貫通孔
を形成する貫通孔形成ステップと、前記貫通孔を介し
て、前記接続劣化異物の洗浄を行なう洗浄ステップとが
設けられている特徴とするものである。[0010] Similarly, in order to achieve the first object,
The invention of claim 2 is different from the invention of claim 1 in that
A through hole forming step of forming a through hole in a region of the substrate facing the semiconductor chip; and a cleaning step of cleaning the connection degraded foreign matter via the through hole. It is.
【００１１】前記第２の目的を達成するために、請求項
３記載の発明は、プリント回路の半導体チップとの接続
部以外の前記半導体チップの外側領域が、ソルダーレジ
スト膜で覆われる基板と、前記半導体チップが前記接続
部に導電性のバンブを介して接続され、該接続に伴って
生じる接続劣化異物の洗浄後に、前記基板と前記半導体
チップ間の間隙領域及びその周辺部が樹脂により封止さ
れてなるフリップチップ接続構造において、前記半導体
チップの隅部に対向し、前記電極パターンが形成されて
いない基板位置に対して、形成されるソルダーレジスト
膜が他部分よりも薄いか、または、ソルダーレジスト膜
が形成されておらず、樹脂が流入され前記封止が行なわ
れる膜調整部が設けられていることを特徴とするもので
ある。According to a third aspect of the present invention, there is provided a semiconductor device comprising: a substrate in which an outer region of the semiconductor chip other than a connection portion of the printed circuit with the semiconductor chip is covered with a solder resist film; The semiconductor chip is connected to the connection portion through a conductive bump, and after cleaning of connection-related foreign matter generated by the connection, a gap region between the substrate and the semiconductor chip and a peripheral portion thereof are sealed with resin. In the flip-chip connection structure, a solder resist film to be formed is thinner than other portions at a substrate position facing the corner of the semiconductor chip and where the electrode pattern is not formed, or A resist film is not formed, and a film adjusting section is provided in which a resin flows in and the sealing is performed.
【００１２】同様に前記第２の目的を達成するために、
請求項４記載の発明は、請求項３記載の発明に対して、
前記半導体チップに対向する前記基板の領域に、前記接
続劣化異物の洗浄を行なう貫通孔が形成されていること
を特徴とするものである。Similarly, in order to achieve the second object,
The invention described in claim 4 is different from the invention described in claim 3 in that
A through-hole for cleaning the connection-deteriorating foreign matter is formed in a region of the substrate facing the semiconductor chip.
【００１３】[0013]
【発明の実施の形態】［第１の実施の形態］本発明をフ
リップチップ接続構造に係る第１の実施の形態に基づい
て、図１及び図２を参照して説明する。図１は本実施の
形態の構成を示す平面説明図、図２は本実施の形態の封
止工程を示す断面説明図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] The present invention will be described based on a first embodiment of a flip-chip connection structure with reference to FIGS. FIG. 1 is an explanatory plan view showing the configuration of the present embodiment, and FIG. 2 is an explanatory cross-sectional view showing a sealing step of the present embodiment.
【００１４】本実施の形態では、図１及び図２に示すよ
うに、基板１には、搭載接続される半導体チップ２の隅
部に対向して、電極パターン３が形成されていない基板
位置に対して、形成されるソルダーレジストの膜厚が他
部分よりも薄いか、またはソルダーレジストが形成され
ない膜調整部８が、ソルダーレジスト膜の現像パターン
の変更により設けられている。In this embodiment, as shown in FIGS. 1 and 2, the substrate 1 is located at a substrate position where the electrode pattern 3 is not formed, facing the corner of the semiconductor chip 2 to be mounted and connected. On the other hand, a film adjusting section 8 in which the thickness of the solder resist to be formed is smaller than the other portions or in which the solder resist is not formed is provided by changing the development pattern of the solder resist film.
【００１５】そして、本実施の形態では、この基板１と
半導体チップ２の間隔が広い膜調整部８より、洗浄液に
よる接続部のフラックスなどの接続劣化異物の洗浄が行
なわれ、この洗浄後に、膜調整部８より封止樹脂６が基
板１と半導体チップ２間に流入され、基板１と半導体チ
ップ２の間隙とその周辺部の封止樹脂６による封止が行
なわれている。In this embodiment, the film adjusting section 8 having a large distance between the substrate 1 and the semiconductor chip 2 cleans the connection deteriorating foreign matter such as the flux of the connection section with a cleaning liquid. The sealing resin 6 flows between the substrate 1 and the semiconductor chip 2 from the adjustment unit 8, and the gap between the substrate 1 and the semiconductor chip 2 and the peripheral portion thereof are sealed by the sealing resin 6.
【００１６】本実施の形態のその他の部分の構成は、す
でに図５及び図６を参照して説明した従来のフリップチ
ップ接続構造と同一なので、重複する説明は行なわな
い。The structure of the other parts of the present embodiment is the same as the conventional flip-chip connection structure already described with reference to FIGS. 5 and 6, and will not be described again.
【００１７】このように本実施の形態では、ソルダーレ
ジスト膜の現像パターンの変更により、簡単に形成され
る膜調整部８では、基板１と半導体チップ２の間隔が広
いので、封止樹脂６は、基板１と半導体チップ２間に容
易に且つ気泡を残存させることなく隅々まで流入され充
填されていて、対角位置に存在する膜調整部８間で、充
填時の内部空気の排出効果が高まり、内部に残存気泡が
存在せず、経年的に残存気泡による接続不良が発生する
ことが完全に防止され、接続不良の発生がない安定した
動作を行なう動作寿命を大幅に延長することが可能にな
る。As described above, in the present embodiment, in the film adjustment section 8 which is easily formed by changing the development pattern of the solder resist film, the distance between the substrate 1 and the semiconductor chip 2 is wide, so that the sealing resin 6 The space between the substrate 1 and the semiconductor chip 2 is easily and completely filled without air bubbles, and the space between the film adjusting portions 8 located at diagonal positions has the effect of discharging the internal air at the time of filling. With no residual air bubbles inside, connection failure due to residual air bubbles over time is completely prevented, and the operating life of stable operation without occurrence of connection failure can be greatly extended become.
【００１８】［第２の実施の形態］本発明の第２の実施
の形態を、図３及び図４を参照して説明する。図３は本
実施の形態の構成を示す平面説明図、図４は本実施の形
態の洗浄工程を示す断面説明図である。[Second Embodiment] A second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is an explanatory plan view showing the configuration of the present embodiment, and FIG. 4 is an explanatory cross-sectional view showing a cleaning step of the present embodiment.
【００１９】本実施の形態では、図３及び図４に示すよ
うに、半導体チップ２に対向する基板１に接続部のフラ
ックスなどの接続劣化異物の洗浄時に洗浄液が流入され
る貫通孔１０が形成されている。この貫通孔１０は、図
３及び図４では一個形成されているが、必要に応じて複
数個形成することが可能である。In this embodiment, as shown in FIGS. 3 and 4, a through-hole 10 through which a cleaning liquid flows when cleaning foreign matter such as flux at a connection portion is formed in a substrate 1 facing a semiconductor chip 2. Have been. Although one through hole 10 is formed in FIGS. 3 and 4, a plurality of through holes can be formed as necessary.
【００２０】本実施の形態のその他の部分の構成は、す
でに図１及び図２を参照して説明した従来のフリップチ
ップと同一なので、重複する説明は行なわない。The structure of the other parts of the present embodiment is the same as that of the conventional flip chip described with reference to FIGS. 1 and 2, and therefore, will not be described again.
【００２１】このような構成の本実施の形態では、接続
部のフラックスなどの接続劣化異物の洗浄時には、図４
に示すように、貫通孔１０から洗浄液１１ｉを注入さ
せ、バンプ５と電極パターン３との接続部のフラックス
などの接続劣化異物を含んだ洗浄液１１ｏが、半導体チ
ップ２の下側から、基板１と半導体チップ２の間隔が広
い膜調整部８を通って、完全に外部に排出されている。
このために、本実施の形態によると、すでに説明した第
１の実施の形態で得られる効果に加えて、フリップチッ
プ構造内部には、接続劣化異物が残存しておらず、接続
劣化異物による経年的な腐食の発生がなく、安定した動
作を行なう動作寿命を大幅に延長することが可能にな
る。In the present embodiment having such a structure, when cleaning foreign matter such as connection flux which is deteriorated at the time of connection, FIG.
As shown in FIG. 3, a cleaning liquid 11i is injected from the through-hole 10 and a cleaning liquid 11o containing connection deteriorating foreign matter such as a flux at a connection portion between the bump 5 and the electrode pattern 3 is transferred from the lower side of the semiconductor chip 2 to the substrate 1. The semiconductor chips 2 are completely discharged to the outside through the film adjusting unit 8 having a large interval.
For this reason, according to the present embodiment, in addition to the effects obtained in the first embodiment already described, no connection-deteriorating foreign matter remains inside the flip chip structure, It is possible to significantly extend the operating life of performing stable operation without causing any substantial corrosion.
【００２２】[0022]
【発明の効果】請求項１記載の発明に係るフリップチッ
プ接続方法によると、プリント回路の電極パターンの半
導体チップとの接続部以外の半導体チップの外側領域
が、ソルダーレジスト膜で覆われる基板に対して、半導
体チップを導電性のバンブを介して接続部に接続し、該
接続に伴って生じる接続劣化異物を洗浄した後に、基板
と半導体チップ間の間隙領域及びその周辺部が樹脂によ
り封止されるが、半導体チップの隅部に対向して、電極
パターンが形成されていない基板位置に対して、形成さ
れるソルダーレジスト膜の膜厚が他部分よりも薄いか、
またはソルダーレジスト膜が形成されない膜調整部が、
ソルダーレジスト膜の現像パターンの変更により簡単に
設けられ、この基板と半導体チップの間隔が広い膜調整
部より樹脂による封止が行なわれるので、樹脂は気泡を
生じることなく、基板と半導体チップ間に容易に流入
し、短時間で完全な封止を行なうことが可能になる。According to the flip-chip connection method according to the first aspect of the present invention, the outside region of the semiconductor chip other than the connection portion of the electrode pattern of the printed circuit with the semiconductor chip is covered with the solder resist film. Then, after connecting the semiconductor chip to the connection portion via the conductive bump, and cleaning the connection deterioration foreign matter caused by the connection, the gap region between the substrate and the semiconductor chip and its peripheral portion are sealed with resin. However, the thickness of the solder resist film to be formed is smaller than that of the other portion at the substrate position where the electrode pattern is not formed, facing the corner of the semiconductor chip.
Or the film adjustment part where the solder resist film is not formed,
It is easily provided by changing the development pattern of the solder resist film, and the gap between the substrate and the semiconductor chip is wide. It easily flows in, and complete sealing can be performed in a short time.
【００２３】請求項２記載の発明に係るフリップチップ
接続方法によると、請求項１記載の発明で得られる効果
に加えて、半導体チップに対向する基板の領域に形成さ
れる貫通孔を介して、内部に残存する接続劣化異物を完
全に洗浄することが可能になる。According to the flip chip connection method according to the second aspect of the present invention, in addition to the effect obtained by the first aspect of the present invention, in addition to the effect obtained by the first aspect of the present invention, This makes it possible to completely clean the connection deteriorating foreign matter remaining inside.
【００２４】請求項３記載の発明に係るフリップチップ
接続構造によると、プリント回路の電極パターンの半導
体チップとの接続部以外の半導体チップの外側領域が、
ソルダーレジスト膜で覆われる基板に、半導体チップが
導電性のバンブを介して接続部に接続され、該接続に伴
って生じる接続劣化異物の洗浄後に、基板と半導体チッ
プ間の間隙領域及びその周辺部が樹脂により封止されて
いるが、半導体チップの隅部に対向し、電極パターンが
形成されていない基板位置に対して、ソルダーレジスト
膜の膜厚が他部分よりも薄く形成されるか、またはソル
ダーレジスト膜が形成されない膜調整部が設けられ、こ
の基板と半導体チップの間隔が広い膜調整部から、樹脂
が基板と半導体チップ間に完全に流入され、樹脂による
封止が気泡を生じることなく行なわれているので、内部
に気泡が残存することがなく、接続不良の発生がなく、
安定した動作を行なう動作寿命を延長することが可能に
なる。According to the flip-chip connection structure according to the third aspect of the present invention, the outer region of the semiconductor chip other than the connection portion of the electrode pattern of the printed circuit with the semiconductor chip is:
A semiconductor chip is connected to a connection portion via a conductive bump on a substrate covered with a solder resist film, and after cleaning of connection-deteriorating foreign matter caused by the connection, a gap region between the substrate and the semiconductor chip and a peripheral portion thereof Is sealed with a resin, but the thickness of the solder resist film is formed to be smaller than that of the other portion, with respect to the substrate position facing the corner of the semiconductor chip and where the electrode pattern is not formed, or A film adjusting portion where a solder resist film is not formed is provided. From the film adjusting portion having a large distance between the substrate and the semiconductor chip, the resin flows completely between the substrate and the semiconductor chip, and the sealing with the resin does not generate bubbles. Because it is performed, there is no air bubble remaining inside, there is no occurrence of poor connection,
It is possible to extend the operating life of performing stable operation.
【００２５】請求項４記載の発明に係るフリップチップ
接続構造によると、請求項３記載の発明で得られる効果
に加えて、半導体チップに対向する基板の領域に形成さ
れた貫通孔を介して、内部に残存する接続劣化異物が完
全に洗浄されていて、腐食の発生がなく、安定した動作
を行なう動作寿命を延長することが可能になる。According to the flip-chip connection structure according to the fourth aspect of the present invention, in addition to the effect obtained by the third aspect of the present invention, in addition to the effect obtained through the through-hole formed in the region of the substrate facing the semiconductor chip, Since the connection deteriorating foreign matter remaining inside is completely cleaned, there is no occurrence of corrosion, and it is possible to extend the operation life of performing stable operation.
【図１】本発明の第１の実施の形態の構成を示す平面説
明図である。FIG. 1 is an explanatory plan view showing a configuration of a first exemplary embodiment of the present invention.
【図２】同実施の形態の封止工程を示す断面説明図であ
る。FIG. 2 is an explanatory sectional view showing a sealing step of the embodiment.
【図３】本発明の第２の実施の形態の構成を示す平面説
明図である。FIG. 3 is an explanatory plan view showing a configuration of a second exemplary embodiment of the present invention.
【図４】同実施の形態の洗浄工程を示す断面説明図であ
る。FIG. 4 is an explanatory sectional view showing a cleaning step of the embodiment.
【図５】従来のフリップチップ接続構造を示す断面説明
図である。FIG. 5 is an explanatory sectional view showing a conventional flip chip connection structure.
【図６】従来のフリップチップ接続構造を示す平面説明
図である。FIG. 6 is an explanatory plan view showing a conventional flip chip connection structure.
【図７】従来のフリップチップ接続構造での封止工程の
説明図である。FIG. 7 is an explanatory view of a sealing step in a conventional flip chip connection structure.
１ 基板 ２ 半導体チップ ３ 電極パターン ５ バンプ ６ 封止樹脂 ７ ソルダーレジスト ８ 膜調整部 １０ 貫通孔 １１o ，１１i 洗浄液 DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor chip 3 Electrode pattern 5 Bump 6 Sealing resin 7 Solder resist 8 Film adjustment part 10 Through-hole 11o, 11i Cleaning liquid
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岩渕 寿章 東京都大田区中馬込１丁目３番６号 株式 会社リコー内 (72)発明者 桑崎 聡 東京都大田区中馬込１丁目３番６号 株式 会社リコー内 (72)発明者 大倉 秀章 東京都大田区中馬込１丁目３番６号 株式 会社リコー内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toshiaki Iwabuchi 1-3-6 Nakamagome, Ota-ku, Tokyo Stock inside Ricoh Company (72) Inventor Satoshi Kuwasaki 1-3-6 Nakamagome, Ota-ku, Tokyo Stock Inside Ricoh Company (72) Inventor Hideaki Okura 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company
Claims (4)
ップとの接続部以外の前記半導体チップの外側領域が、
ソルダーレジスト膜で覆われる基板に対して、前記半導
体チップを前記接続部に導電性のバンブを介して接続
し、該接続に伴って生じる接続劣化異物を洗浄後に、前
記基板と前記半導体チップ間の間隙領域及びその周辺部
を樹脂により封止するフリップチップ接続方法におい
て、 前記半導体チップの隅部に対向し、前記電極パターンが
形成されていない基板位置に対して、形成されるソルダ
ーレジスト膜の膜厚が他部分よりも薄いか、またはソル
ダーレジスト膜が形成されない膜調整部を設けるソルダ
ーレジスト膜調整ステップと該ソルダーレジスト膜調整
ステップで設けられた膜調整部より前記樹脂による封止
を行なう樹脂封止ステップとを有することを特徴とする
フリップチップ接続方法。An outer region of the semiconductor chip other than a connection portion of the electrode pattern of the printed circuit with the semiconductor chip,
The semiconductor chip is connected to the connection portion via a conductive bump with respect to the substrate covered with the solder resist film, and after the connection deteriorating foreign matter caused by the connection is washed, the semiconductor chip is connected between the substrate and the semiconductor chip. In a flip-chip connection method for sealing a gap region and a peripheral portion thereof with a resin, a film of a solder resist film formed on a substrate position facing the corner of the semiconductor chip and not having the electrode pattern formed thereon A solder resist film adjusting step of providing a film adjusting section having a thickness smaller than that of the other portion or in which a solder resist film is not formed, and a resin sealing for sealing with the resin from the film adjusting section provided in the solder resist film adjusting step. A flip-chip connecting method.
に対して、 前記半導体チップに対向する前記基板の領域に、貫通孔
を形成する貫通孔形成ステップと、 前記貫通孔を介して、前記接続劣化異物の洗浄を行なう
洗浄ステップとが設けられている特徴とするフリップチ
ップ接続方法。2. The flip-chip connection method according to claim 1, wherein a through-hole forming step of forming a through-hole in a region of the substrate facing the semiconductor chip; and the connection via the through-hole. A flip-chip connection method, comprising: a cleaning step of cleaning deteriorating foreign matter.
以外の前記半導体チップの外側領域が、ソルダーレジス
ト膜で覆われる基板と、前記半導体チップが前記接続部
に導電性のバンブを介して接続され、該接続に伴って生
じる接続劣化異物の洗浄後に、前記基板と前記半導体チ
ップ間の間隙領域及びその周辺部が樹脂により封止され
てなるフリップチップ接続構造において、 前記半導体チップの隅部に対向し、前記電極パターンが
形成されていない基板位置に対して、形成されるソルダ
ーレジスト膜が他部分よりも薄いか、または、ソルダー
レジスト膜が形成されておらず、樹脂が流入され前記封
止が行なわれる膜調整部が設けられていることを特徴と
するフリップチップ接続構造。3. An outer region of the semiconductor chip other than a connection portion of the printed circuit with the semiconductor chip is connected to a substrate covered with a solder resist film, and the semiconductor chip is connected to the connection portion via a conductive bump. In a flip-chip connection structure in which a gap region between the substrate and the semiconductor chip and a peripheral portion thereof are sealed with a resin after cleaning of connection deterioration foreign matter caused by the connection, the semiconductor device faces a corner of the semiconductor chip. However, for the substrate position where the electrode pattern is not formed, the solder resist film to be formed is thinner than other portions, or the solder resist film is not formed, and the resin flows in and the sealing is performed. A flip-chip connection structure, wherein a film adjustment unit is provided.
に対して、 前記半導体チップに対向する前記基板の領域に、前記接
続劣化異物の洗浄を行なう貫通孔が形成されていること
を特徴とするフリップチップ接続構造。4. A flip chip connection structure according to claim 3, wherein a through hole for cleaning said connection deteriorating foreign matter is formed in a region of said substrate facing said semiconductor chip. Flip chip connection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9857698A JPH11284032A (en) | 1998-03-26 | 1998-03-26 | Flip-chip connection method and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9857698A JPH11284032A (en) | 1998-03-26 | 1998-03-26 | Flip-chip connection method and structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11284032A true JPH11284032A (en) | 1999-10-15 |
Family
ID=14223505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9857698A Pending JPH11284032A (en) | 1998-03-26 | 1998-03-26 | Flip-chip connection method and structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11284032A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6956290B2 (en) | 2002-09-12 | 2005-10-18 | Nec Electronics Corporation | Flip-chip BGA semiconductor device for achieving a superior cleaning effect |
| JP2006269541A (en) * | 2005-03-22 | 2006-10-05 | Nec Electronics Corp | Semiconductor device |
| EP1732117A2 (en) | 2005-06-09 | 2006-12-13 | Shinko Electric Industries Co., Ltd. | Semiconductor device packaging substrate and semiconductor device packaging structure |
| JP2008159702A (en) * | 2006-12-21 | 2008-07-10 | Nec Electronics Corp | Substrate for semiconductor device and its manufacturing method, and semiconductor device and its manufacturing method |
| CN100444373C (en) * | 2005-10-10 | 2008-12-17 | 三星电机株式会社 | Void-free circuit board and semiconductor package having the same |
-
1998
- 1998-03-26 JP JP9857698A patent/JPH11284032A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6956290B2 (en) | 2002-09-12 | 2005-10-18 | Nec Electronics Corporation | Flip-chip BGA semiconductor device for achieving a superior cleaning effect |
| JP2006269541A (en) * | 2005-03-22 | 2006-10-05 | Nec Electronics Corp | Semiconductor device |
| JP4502204B2 (en) * | 2005-03-22 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| EP1732117A2 (en) | 2005-06-09 | 2006-12-13 | Shinko Electric Industries Co., Ltd. | Semiconductor device packaging substrate and semiconductor device packaging structure |
| EP1732117A3 (en) * | 2005-06-09 | 2010-03-31 | Shinko Electric Industries Co., Ltd. | Semiconductor device packaging substrate and semiconductor device packaging structure |
| CN100444373C (en) * | 2005-10-10 | 2008-12-17 | 三星电机株式会社 | Void-free circuit board and semiconductor package having the same |
| JP2008159702A (en) * | 2006-12-21 | 2008-07-10 | Nec Electronics Corp | Substrate for semiconductor device and its manufacturing method, and semiconductor device and its manufacturing method |
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