JPH11283335A - Data slice circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower an error rate at the time of reproducing a draw type optical disk, etc., in an optical disk reproducing device. SOLUTION: A reference range setting circuit 43 with simple circuit constitution is added to the data slice circuit 4A, and only a binary signal with the signal length near the side of the signal length 11T is extracted among the binary signals SBN binarized by a comparator 41, and an offset potential is applied to a high frequency signal SRF. Thus, the possitive and negative coincident point of the binarized signal SBN is shifted to the side of the signal length 11T, then the error rate is lowered since the synchronizing detection is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD player, C
D-ROM drive, DVD player, DVD-ROM
The present invention relates to a data slice circuit which is built in an optical disk reproducing device such as a drive and binarizes a high-frequency signal read from an optical disk.

[0002]

2. Description of the Related Art FIG. 8 shows a block diagram of a reproduction signal processing section of an optical disk including a conventional data slice circuit. FIG.
, CD (compact disk), CD-ROM
Digital information is recorded on the reproducing surface of the optical disk 1 and the like, and is rotated at a predetermined rotation speed during reproduction.
Then, the pickup 2 reads information recorded on the optical disc 1 as a difference in reflectance, converts the value into a voltage value, and outputs the voltage value.

[0003] Then, the head amplifier 3, and outputs a high frequency signal S _RF and amplifies and equalizing the output from the pickup 2. This high-frequency signal _SRF is an analog value, and the data slice circuit 4E outputs the high-frequency signal SRF.
_RF is converted into a high-level (hereinafter, referred to as "H") or low-level (hereinafter, referred to as "L") digital signal, that is, a binary signal _SBN .

The data slicing circuit 4E outputs a high-frequency signal S
_RFAnd a predetermined slice potential E_SL1Compare with high frequency signal
S_RFA comparator 41 for binarizing the signal and a high-frequency signal
No. S _RFTo a binarized signal S by adding a predetermined offset potential to_BN
Potential control circuit 42 for controlling the signal length of
B and its operation is as follows.

The binarized signal S _BN binarized by the comparator 41 is used as it is as a drive signal for the constant current circuit 421. When the binarized signal S _BN is “H”, the capacitor 4
22 by driving the constant current circuit 421 so as to discharge to lower the offset voltage for the high frequency signal S _RF. On the other hand, when the binarized signal S _BN is “L”, the constant current circuit 421 is driven so as to charge the capacitor 422, and the offset potential with respect to the high frequency signal S _RF is increased. The capacitor 47 forms a low-pass filter together with the resistor 423.

Since the digital information recorded on the optical disk 1 is originally processed so that the appearance ratio of the "H" period and the "L" period becomes equal within a certain period, the charging and discharging of the capacitor 422 is suspended. optimal value of the offset potential to the high frequency signal S _RF is obtained at that suits. Therefore, the comparator 41 compares the high-frequency signal S _RF and the slice voltage E _SL1 the offset potential is applied, is binarized at an optimum slice positions are carried out.

After that, the binary signal S _BN is sent to the PLL circuit 5. The PLL circuit 5 generates an extraction clock synchronized with the binarized signal S _BN , and the decoder 6 restores digital information recorded on the optical disc 1 from the binarized signal S _BN by the extracted clock. That is, the decoder 6, by incorporating binarized signal S _BN in the data slice circuit 4E in the timing of the extracted clock generated by the PLL circuit 5, to recover the digital information as recorded on the optical disc 1. After that, error correction is performed, and the data is rearranged into music information, computer data, and the like.

[0008]

However, when a conventional data slice circuit is used, when a write-once optical disc such as a CD-R is reproduced, the digital information restored by the decoder 6 using the PLL circuit 5 is used. The result that the error rate (error rate) was bad was obtained. Hereinafter, this point will be described in detail.

[0009] The EFM (Eight)
Digital information processed by a modulation method called “To Fourteen Modulation” is recorded. When the reference signal length is T, the signal length is 3T to 11T.
There is a signal having a signal length that is an integral multiple of T. When reproducing the fabricated ordinary CD in the stamper, "H" (positive) width "L" (negative) width of the binary signal S _BN binarized by the data slice circuit, the signal length 3T ~
Almost matched values are obtained up to 11T.

However, in a write-once optical disk such as a CD-R, information is written on a reproducing surface by irradiation of a laser beam, and the writing state is not uniform, so that a difference occurs in reflectance. Therefore, as shown in FIG. 9, positive width and negative width of the binary signal S _BN is but substantially mates around the signal length 4T～5T, phenomenon confirmed that would significantly shift the signal length 11T side Was. Incidentally, in FIG. 9 shows a "H" (positive) width "L" (negative) width S _BN of the binary signal to the signal length 3T to 11T.

In the case of a CD, restoration data processing is performed using a signal length of 11T as a synchronization pattern. However, it is considered that the detection of the synchronization pattern becomes unstable due to the above-described shift between the positive width and the negative width, and the error rate deteriorates. FIG. 9 shows the relationship between the binarized signal length and the frequency of its appearance, divided into a positive width and a negative width. To improve the error rate to solve the above problem, in the data slice circuit, positive width of the binary signal S _BN and the negative width, as shown in FIG. 10, to conform with 11T side It is considered that a circuit configuration should be adopted.

An object of the present invention is to provide a data slice circuit capable of improving an error rate.

[0013]

According to a first aspect of the present invention, there is provided a data slice circuit comprising: a comparator for binarizing a high-frequency signal read as information recorded on an optical disk; , Comparator 2
Setting of a reference range for extracting a binarized signal within a range from a first signal length larger than the minimum signal length to a second signal length larger than the first signal length, out of the binarized binarized signals. Controlling the offset potential added to the high-frequency signal in accordance with the signal length of the binarized signal within the range from the first signal length to the second signal length extracted by the circuit and the reference range setting circuit; The appearance ratios of the “H” period and the “L” period of the binarized signal in the range from the first signal length to the second signal length of the binarized signal binarized by the comparator are substantially equal. And an offset potential control circuit.

According to this configuration, the second signal is converted from the first signal length to the second signal length.
By controlling the offset potential added to the high-frequency signal in accordance with the signal length of the binarized signal in the range up to the signal length, the minimum signal length of the binarized signal binarized by the comparator is calculated. The "H" period and "L" period of the binarized signal in the range from the large first signal length to the second signal length
Since the appearance ratios of the periods are made substantially equal, it is possible to shift the position where the “H” width and “L” width of the binarized signal match to the longer signal length. As a result, the binarized signal having a long signal length for which the synchronization pattern is to be detected can be brought closer to a state where the “H” width and the “L” width of the binarized signal match. Therefore, it is possible to stably detect the synchronization pattern, and it is possible to improve the error rate.

According to a second aspect of the present invention, there is provided a data slice circuit comprising: a comparator for binarizing a high-frequency signal read as information recorded on an optical disc; and a binary signal binarized by the comparator. Potential control to adjust the appearance ratio of the "H" period and the "L" period of the binary signal binarized by the comparator by controlling the offset potential added to the high-frequency signal in accordance with the signal length of A circuit and a binarized signal in a range from a first signal length larger than the minimum signal length to a second signal length larger than the first signal length among the binarized signals binarized by the comparator A reference range setting circuit for extracting the first signal length from the first signal length extracted by the reference range setting circuit.
By correcting the offset potential according to the signal length of the binarized signal in the range up to the signal length, the first signal length to the second signal of the binarized signal binarized by the comparator An offset potential correction circuit is provided for making the appearance ratios of the “H” period and the “L” period of the binary signal within the range up to the length substantially equal.

According to this configuration, the second signal is converted from the first signal length to the second signal length.
By correcting the offset potential according to the signal length of the binarized signal in the range up to the signal length, the first signal larger than the minimum signal length among the binarized signals binarized by the comparator Since the appearance ratios of the “H” period and the “L” period of the binary signal in the range from the long signal length to the second signal length are made substantially equal, the “H” width and the “L” width of the binary signal Can be shifted to the longer signal length. As a result, regarding the binarized signal having a long signal length for which the synchronization pattern is to be detected, “H”
The width can be made closer to the state where the width and the “L” width match. Therefore, it is possible to stably detect the synchronization pattern, and it is possible to improve the error rate.

According to a third aspect of the present invention, there is provided a data slice circuit comprising: a comparator for binarizing a high-frequency signal by comparing a high-frequency signal read as information recorded on an optical disk with a slice potential; Of the binarized signal binarized from the first signal length greater than the minimum signal length to the second signal length greater than the first signal length
A reference range setting circuit for extracting a binary signal in a range up to the signal length of the first range, and a first range extracted by the reference range setting circuit.
By controlling the slice potential according to the signal length of the binarized signal in the range from the signal length to the second signal length,
The appearance ratios of the “H” period and the “L” period of the binarized signal in the range from the first signal length to the second signal length of the binarized signal binarized by the comparator are substantially equal. And a slice potential control circuit.

According to this configuration, the second signal is converted from the first signal length to the second signal length.
By controlling the slice potential in accordance with the signal length of the binarized signal within the range of the signal length of the first signal, the first signal larger than the minimum signal length among the binarized signals binarized by the comparator 2 in the range from the first signal length to the second signal length
Since the appearance ratios of the “H” period and the “L” period of the binarized signal are made substantially equal, the position where the “H” width and “L” width of the binarized signal match is shifted to the longer signal length. It becomes possible. As a result, the binarized signal having a long signal length for which the synchronization pattern is to be detected can be brought closer to a state where the “H” width and the “L” width of the binarized signal match. Therefore, it is possible to stably detect the synchronization pattern, and it is possible to improve the error rate.

According to a fourth aspect of the present invention, there is provided a data slice circuit comprising: a comparator for binarizing a high-frequency signal by comparing a high-frequency signal read as information recorded on an optical disc with a slice potential; By controlling the slice potential according to the signal length of the binarized signal binarized by the above, the appearance ratio of the “H” period and the “L” period of the binarized signal binarized by the comparator is substantially reduced. A slice potential control circuit for equalizing, and a binarized signal binarized by the comparator in a range from a first signal length larger than the minimum signal length to a second signal length larger than the first signal length. A reference range setting circuit for extracting a certain binarized signal, and according to the signal length of the binarized signal in the range from the first signal length to the second signal length extracted by the reference range setting circuit By correcting the slice potential, the “H” period and “L” of the binarized signal within the range from the first signal length to the second signal length of the binarized signal binarized by the comparator And a slice potential correction circuit for making the appearance ratios of the periods substantially equal.

According to this configuration, the second signal is converted from the first signal length to the second signal length.
Of the binarized signal binarized by the comparator by correcting the slice potential according to the signal length of the binarized signal in the range up to the signal length of the first signal larger than the minimum signal length 2 in the range from the first signal length to the second signal length
Since the appearance ratios of the “H” period and the “L” period of the binarized signal are made substantially equal, the position where the “H” width and “L” width of the binarized signal match is shifted to the longer signal length. It becomes possible. As a result, the binarized signal having a long signal length for which the synchronization pattern is to be detected can be brought closer to a state where the “H” width and the “L” width of the binarized signal match. Therefore, it is possible to stably detect the synchronization pattern, and it is possible to improve the error rate.

According to a fifth aspect of the present invention, there is provided a data slice circuit according to the first, second, third or fourth aspect, wherein the reference range setting circuit is binarized by a comparator. Is masked with a fixed-length mask signal shorter than the first signal length, thereby extracting a binary signal longer than the first signal length.

According to this configuration, the method of extracting the binary signal is facilitated, and the configuration of the reference range setting circuit can be simplified. According to a sixth aspect of the present invention, in the data slice circuit according to the first, second, third, fourth, or fifth aspect, the extracted clock synchronized with the binary signal binarized by the comparator is used. A PLL circuit for extracting information recorded on the optical disc from a binarized signal generated and binarized by the comparator, wherein the reference range setting circuit binarizes the binary signal by the comparator based on the extracted clock; Characterized in that the signal length of the coded signal is measured.

According to this configuration, the binarized signal can be easily extracted in units of the reference signal length of the EFM signal. The data slice circuit according to claim 7 of the present invention is the data slice circuit according to claim 6,
When the extraction clock generated by the L circuit is abnormal, the reference range setting circuit stops the operation of extracting the binarized signal in the range from the first signal length to the second signal length, and outputs a signal in the entire range. A long binary signal is output.

According to this configuration, when the PLL circuit is not locked and the extracted clock is not synchronized with the binarized signal, the binarized signal in an erroneous range due to erroneous measurement of the binarized signal length is output. It is possible to prevent the occurrence ratio of the extracted and binarized signal between the high level period and the low level period from being largely shifted.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a block diagram of a reproduction signal processing section of an optical disk including a data slice circuit according to a first embodiment of the present invention. In FIG. 1, CD, CD-R
Digital information is recorded on a reproduction surface of the optical disc 1 such as an OM, and is rotated at a predetermined rotation speed during reproduction. Then, the pickup 2 reads information recorded on the optical disc 1 as a difference in reflectance, converts the value into a voltage value, and outputs the voltage value.

Next, the head amplifier 3, and outputs a high frequency signal S _RF and amplifies and equalizing the output from the pickup 2. This high-frequency signal _SRF is an analog value, and the data slice circuit 4A outputs the high-frequency signal SRF.
_RF is converted into a digital signal of "H" or "L", that is, a binary signal _SBN . Then, the binarized signal S _BN is sent to the PLL circuit 5. Generates the extracted clock CLK synchronized with the PLL circuit 5 in the binarized signal S _BN, digital information recorded by the extracted clock CLK from the binary signal S _BN on the optical disc 1 is restored. The procedure for restoring the digital information is the same as in the conventional example.

Here, the data slice circuit 4A will be described in detail. The data slice circuit 4A includes a comparator 41, an offset potential control circuit 42A, and a reference range setting circuit 43. Comparator 41
Outputs a binary signal S _BN by binarizing the RF signal S _RF is compared with the high frequency signal S _RF with a predetermined slice potential E _SL1 read as information recorded on the optical disc 1.

Further, reference range setting circuit 43 has a function of extracting a binary signal of the signal length of the predetermined range from the binary signal S _BN. Specifically, the minimum signal length of the binary signal S _BN binarized by the comparator 41 (in this example, 3T) greater than the first signal length (in this example, 7T) from the first , And a binary signal within a range up to a second signal length (11T in this example) which is equal to or smaller than the maximum signal length (11T in this example).

Further, the offset potential control circuit 42A
By controlling the offset potential added to the high-frequency signal _SRF according to the signal length of the binarized signal in the range from the first signal length to the second signal length extracted by the reference range setting circuit 43, The appearance ratio of the “H” period and the “L” period of the binarized signal in the range from the first signal length to the second signal length of the binarized signal S _BN binarized by the comparator 41 _Are controlled so that the signal lengths of the binary signal _SBN are substantially equal to each other.

The binarized signal S _BN binarized by the comparator 41 is input to the reference range setting circuit 43 as described above. The internal configuration of the reference range setting circuit 43 is, for example, as shown in FIG. The operation timing is as shown in FIG. In Figure 3, stop the binarized signal S _BN and the extracted clock CLK in the case where the reference range setting value 6 as an example (signal length exceeding 6T (extract only the binarized signal S _BN of 7T~11T)) The operation timings of the signal S _ST , the up signal S _U, and the down signal S _D are shown.

The width of the "L" period and the "H" period of the input binary signal S _BN is counted respectively by the counter 431 and 433 using the extracted clock CLK output from the PLL circuit 5. Specifically, "H" period of the binarized signal S _BN is counter 431 to reset the inverting circuit 435, "L" period of the binarized signal S _BN is counter 433 to reset, 2 the "L" period of the binarized signal S _BN counter 431 counts the extracted clock CLK, the counter 433 to "H" period of the binarized signal S _BN counts the extracted clock CLK.

The count values of the counters 431 and 433 and the reference range setting value (6 in this example) are compared by comparators 432 and 434, respectively.
If the count value of 434 is larger, the comparators 432 and 43
4 outputs "H". In this case, the counter 431
And a comparator 432 constitute a mask signal generation circuit for forming a mask signal on the “L” side for masking a binarized signal having a short signal length. A mask signal generation circuit for forming a mask signal on the “H” side for masking the value signal is configured.

Further, the outputs of the comparators 432 and 434
Are AND gates through OR gates 436 and 437, respectively.
Ports 438 and 439 are input as mask signals. So
As a result, the signal length 6T (exactly, the rising of the extracted clock CLK)
The falling edge is a binary signal S _BNIs synchronized with the edge of
Therefore, the binary signal S is equal to or less than 6.5T._BNIs trout
Binarized signal exceeding 6T in signal length and ignored
Signal, that is, a binary signal S having a signal length of 7T to 11T._BNOnly
It is extracted by the reference range setting circuit 43. Concrete
Specifically, a binary signal S having a signal length of 7T to 11T is used._BNOf which
Each of the portions exceeding 6T is an up signal S_UOr down
Signal S_DIs output as

[0034] Incidentally, OR gate 436, 437 is for disabling the mask signal when the input of the stop signal S _ST. Hereinafter, this point will be described. As described above, the reference range setting circuit 43 counts the binarized signal S _BN with the extraction clock CLK. Therefore, the optical disk 1 has a flaw or the like, and the PLL circuit 5 synchronizes with the binarized signal S _BN correctly. When the extracted clock CLK is not obtained (PLL
In a state where the circuit 5 is not locked), the normal counting is not performed, and the appropriate control operation cannot be performed. Therefore, in that case, the stop signal S
_ST is output, and the up signal S _U or the down signal S according to all the binarized signals S _BN regardless of the reference range setting value.
_D is output.

The up signal S _U and down signal S _D of the reference range setting circuit 43 thus generated are used as drive signals for the constant current circuit 421, and the down signal S _D
There "H" is lowered to offset potential to the high frequency signal S _RF to drive the constant current circuit 421 so as to discharge the capacitor 422 when the, so as to increase the negative width, up signal S _U is "H" when increases the offset potential to the high frequency signal S _RF to drive the constant current circuit 421 to charge the capacitor 422, so as to increase the positive width.

With such an operation, the capacitor 422
When the charging and discharging of the_RFTo
The optimum value of the offset potential to be obtained is obtained.
The range setting value is 6, and the reference range is a signal length of 7T to 11T.
(Binary signal S exceeding 6T _BNOnly extract) as a range
And cut the whole range from 3T to 6T compared to the conventional example.
The binary signal S_BNPoi width and negative width match
Event is shifted to the 11T side instead of the 3T side.
The offset potential is determined.

FIG. 4 shows the reference point and the coincidence point between the positive width and the negative width of the binary signal _SBN . FIG. 4 shows the relationship between the reference range and the negative width / positive width matching point. This can be obtained from the appearance frequency of the binarized signal having a signal length of 3T to 11T (see FIGS. 9 and 10). As can be seen from FIG. 4, the signal length of the positive and negative of the binary signal S _BN at 11T side as the reference range is narrower in 11T side becomes to match the reference range 7T~11
If it is T, it will match around 8T.

Therefore, the offset potential control circuit 42
When a high-frequency signal S _RF and the slice voltage E _SL1 which is offset potential applied by A are compared in the comparator 41, the binary signal S _BN as positive and negative matches are obtained in a shorter 11T side, the 11T detection As a result, the synchronization can be reliably detected, and as a result, the error rate is improved.

As described above, the data slice circuit 4A
By adding a reference range setting circuit 43 is a simple circuit structure, by extracting only the binarized signal S _BN of signal length close to 11T side of the binary signal S _BN binarized by the comparator 41 , by controlling the offset potential applied to the high frequency signal S _RF in accordance with the binarized signal S _BN of signal length close to the 11T side, shifting the binary positive and consistent point of the negative signal S _BN to 11T side It is possible to increase the error rate by improving the synchronization detection.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. FIG.
Shows a block diagram of a reproduction signal processing unit of an optical disk including a data slice circuit according to a second embodiment of the present invention. In FIG. 5, 1 is an optical disk, 2 is a pickup, 3 is a head amplifier, and 5 is a PLL circuit, and the above configuration is the same as that of the first embodiment. The difference from the first embodiment is the configuration of the data slice circuit 4B, and the binary signal S _BN extracted by the reference range setting circuit 43.
, An offset potential correction circuit 44 for correcting the offset potential obtained by the offset potential control circuit 42B
Is newly provided. The offset potential control circuit 42B is directly driven by the binary signal S _BN binarized by the comparator 41 has the same structure as the conventional example.

Hereinafter, the operation of the data slice circuit 4B will be described in detail. Offset potential control circuit 42
In B, and determines the offset potential is added by driving the constant current circuit 421 for charging and discharging the capacitor 422 in response to the binary signal S _BN to the high frequency signal S _RF, charging at a constant current circuit 421 The amount of current at the time and the amount of current at the time of discharge are analog amounts, and are not necessarily the same value, and may have a slight difference (unbalance). Then this case, since the offset potential applied to the high frequency signal S _RF shifted binarization by the comparator 41 is no longer performed in an optimum state. Therefore, an offset potential correction circuit 44 is added to digitally correct the offset potential.

The binarized signal S _BN binarized by the comparator 41 is input to the reference range setting circuit 43 and, like the first embodiment, the up signal S _BN corresponding to the reference range set value.
_U or down signal _SD is output. Then, by the output of the up signal _SU or the down signal _SD ,
The up / down counter 441 in the offset potential correction circuit 44 counts up when the up signal _SU is "H" and counts down when the down signal _SD is "H". Is counted. Therefore, the count value of the up / down counter 441, which is the difference between the count up / down, is output as a correction value. This count value is converted into a PWM signal by a PWM (pulse width modulation) control circuit 442,
The offset potential is corrected by charging / discharging the capacitor 422 via the resistor 443.
Since the binary signals of the signal length 3T~6T by 3 are excluded, so that the matching point of the positive width and negative widths of the first embodiment as well as the binary signal S _BN is shifted to 11T side Act on.

The PWM control circuit 442 takes out the upper 6 bits of the count value of the up / down counter 441 and converts it into a PWM signal which can be changed in 64 steps corresponding to the value. Charging is performed when the PWM signal is “H”, and discharging is performed when the PWM signal is “L”. Therefore, the offset potential is applied by the offset potential control circuit 42B, and when the high frequency signal S _RF and the slice voltage E _SL1 the correction offset potential were performed at the offset potential correcting circuit 44 for comparing with a comparator 41, and more 1
Binary signal S _BN as positive and negative matches at 1T side is obtained, synchronization detection for the 11T detection is improved should be able to reliably, the error rate is improved as a result.

[0044] As described above, by adding a reference range setting circuit 43 and the offset potential correcting circuit 44 to the data slice circuit 4B, signal close to 11T side of the binary signal S _BN binarized by the comparator 42 Only the long binary signal _SBN is extracted by the reference range setting circuit 43, and the reference range setting circuit 4
By correcting the offset potential applied to the high-frequency signal _SRF based on the output signal of No. 3, the imbalance in the constant current circuit 421 can be corrected and accurate binarization can be realized, and the binarized signal S _BN positive / negative match point is 1
The error rate can be improved by shifting to the 1T side and improving the synchronization detection.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. FIG.
Shows a block diagram of a reproduction signal processing unit of an optical disk including a data slice circuit according to the third embodiment of the present invention. In FIG. 6, 1 is an optical disk, 2 is a pickup, 3 is a head amplifier, and 5 is a PLL circuit, and the above configuration is the same as that of the first embodiment. The first is different from the embodiment has a configuration of a data slice circuit 4C, provided instead slice potential control circuit 45A of the offset potential control circuit 42A, the high frequency signal S _RF slices potential E of the comparator 41 instead of the offset potential _SL2
Is controlled.

The circuit configuration of the slice potential control circuit 45A is such that the polarity of the signal for driving the constant current circuit 451 is opposite to that of the constant current circuit 421, that is, the capacitor 422 when the down signal _SD is "H". To increase the slice potential and discharge the capacitor 422 when the up signal S _U is “H” to lower the slice potential. The capacitor 452 corresponding to the capacitor 422 is
This is the same as the offset potential control circuit 42A, except that the resistor corresponding to 23 is omitted. The reason why the resistance is omitted is that there is no point in forming a low-pass filter on the slice potential side. In FIG. 6, the low pass filter is configured with a high-frequency signal S _RF on the input side of the capacitor 47 high-frequency signals S _RF on the input side to the resistance 48 of the comparator 41 is inserted.

The comparator 41 compares the high-frequency signal S _RF with the slice potential E _SL2 and outputs the binary signal S _BN , so that the offset potential applied to the high-frequency signal S _RF is controlled and the slice potential E _SL2 is controlled. When to control,
There is no difference in the comparison operation, and an effect completely equivalent to that of the data slice circuit according to the first embodiment can be obtained.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG.
Shows a block diagram of a reproduction signal processing unit of an optical disk including a data slice circuit according to a fourth embodiment of the present invention. In FIG. 7, 1 is an optical disk, 2 is a pickup, 3 is a head amplifier, and 5 is a PLL circuit, and the above configuration is the same as that of the second embodiment. Second embodiment differs from of a configuration of a data slice circuit 4D, provided instead slice potential control circuit 45B of the offset potential control circuit 42B, the high frequency signal S _RF slices potential E of the comparator 41 instead of the offset potential _SL2
And the offset potential correction circuit 4
4 is provided a slice potential correcting circuit 46 in place of, is also a point which is adapted to correct the slice potential E _SL2 of the comparator 41 instead of the offset potential of the high-frequency signal S _RF.

The circuit configuration of the slice potential control circuit 45 B and the slice potential correction circuit 46 is the same as that of the constant current circuit 4.
51 is the same as the offset potential control circuit 43B and the offset potential correction circuit 44, except that the polarity of the signal for driving the counter 51 is reversed and the signal applied from the reference range setting circuit 43 to the U / D counter 461 is replaced. is there. Incidentally, because switching the signal applied to the U / D counter 461, which had been allowed to up-count the up / down counter 461 by the up signal S _U in the case of FIG. 5, the up / down 7 up signal S _U the counter 461 is counting down, also had to down-count the up / down counter 461 in the down signal S _D in case of FIG. 5, up-down signal S _U 7 /
That is, the down counter 461 is counted up.

[0050] Since the comparator 41 compares the high-frequency signal S _RF and the slice voltage E _SL2 outputs the binarized signal S _BN, controls the slice potential E _SL2 when controlling the offset potential applied to the high frequency signal S _RF There is no difference in the comparison operation between the two cases, and an effect completely equivalent to that of the data slice circuit according to the second embodiment can be obtained. In addition,
In each of the first to fourth embodiments, the optical disk 1 is a CD, a CD-ROM, or the like.
Other CD media such as RW, DVD, DVD-
DVD media such as ROM and DVD-RAM, MO (magneto-optical disk), and PD (phase change optical disk) may be used.

In each of the first to fourth embodiments, the reference range setting value of the reference range setting circuit 43 is set to 6, and binary data in the range of 7T to 11T is extracted. By setting the lower limit to 7T, 8T, 9T,... And narrowing the reference range to the 11T side, 11T
, The positive width and the negative width of the binarized signal _SBN match. If the reference range setting value is set to 3 smaller than 6, the reference range becomes 4T to 11T. If it is set to 4, 5T to 11T. If it is set to 5, 6T to 11T.
And the reference range is 3T more than in the case of the above embodiment.
Will be closer to the side. However, in any case, as compared with the conventional example, at least the binarized signal having the signal length of 3T is not referred to, so that the point where the positive width and the negative width match is shifted to the 11T side. In any case, the error rate can be improved.

[0052] That is, if the reference range setting circuit 43, and the first signal length, to be able to extract the binary signal S _BN ranging first signal a second signal length greater than the length, The positive and negative widths of the specific binary signal _SBN can be matched to each other, and the error rate can be improved by setting the first signal length larger than the minimum signal length. You can do it.

When the reference range setting circuit 43 can extract the binarized signal S _BN in the range from the first signal length to the second signal length, the signal of the specific binarized signal S _BN can be extracted. It is also possible to match the long positive width with the negative width.

[0054]

As described above, according to the data slice circuit of the present invention, a reference range setting circuit having a simple circuit configuration is added to the data slice circuit, and the binary signal generated by the comparator is output. At least, the binarized signal having the minimum signal length is excluded, and a binarized signal having a signal length close to the maximum signal length is extracted. By controlling, the coincidence point between the positive and negative of the binarized signal is shifted to the longer signal length, and the error detection can be improved by improving the synchronization detection.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a reproduction signal processing unit of an optical disc including a data slice circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a reference range setting circuit according to the first embodiment of the present invention.

FIG. 3 is an operation timing chart of the reference range setting circuit when the reference range setting value is set to 6;

FIG. 4 is a graph showing a relationship between a reference range and a positive width / negative width matching point of a binary signal.

FIG. 5 is a block diagram illustrating a configuration of a reproduction signal processing unit of an optical disc including a data slice circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a reproduction signal processing unit of an optical disc including a data slice circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a reproduction signal processing unit of an optical disc including a data slice circuit according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a reproduction signal processing unit of an optical disc including a conventional data slice circuit.

FIG. 9 is a graph showing a relationship between a binary signal length and a positive width / negative matching point when an error rate is low.

FIG. 10 is a graph showing a relationship between a binary signal length and a positive width / negative matching point when an error rate is good.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 optical disk 2 pickup 3 head amplifier 4A data slice circuit 4B data slice circuit 4C data slice circuit 4D data slice circuit 41 comparator 42A offset potential control circuit 42B offset potential control circuit 421 constant current circuit 422 capacitor 423 resistance 43 reference range setting circuit 431 counter 432 Comparator 433 Counter 434 Comparator 435 Inverting circuit 436 OR gate 437 OR gate 438 AND gate 439 AND gate 44 Offset potential correction circuit 441 Up / down counter 442 PWM control circuit 443 Resistance 45A Slice potential control circuit 45B Slice potential control circuit 451 Constant current circuit 452 Capacitor 46 Slice potential correction circuit 461 Up / down counter 462 PWM control circuit 463 resistor 47 capacitor 48 resistor 5 PLL circuit S _RF frequency signal S _BN 2 binary signal E _SL1 slice potential E _SL2 slice potential S _U up signal S _D down signal S _ST stop signal CLK extracted clock

Claims (7)

[Claims] A comparator for binarizing a high-frequency signal read as information recorded on an optical disc; and a first signal larger than a minimum signal length among binary signals binarized by the comparator. A reference range setting circuit for extracting a binarized signal in a range from a signal length to a second signal length larger than the first signal length; and a reference range setting circuit extracting the binary signal from the first signal length extracted by the reference range setting circuit. By controlling an offset potential to be added to the high-frequency signal according to the signal length of the binarized signal in the range up to the second signal length, of the binarized signal binarized by the comparator A data slave comprising an offset potential control circuit for making the appearance ratio of a high level period and a low level period of a binary signal in the range from the first signal length to the second signal length substantially equal. Scan circuit. 2. A comparator for binarizing a high-frequency signal read as information recorded on an optical disk, and adding to the high-frequency signal according to a signal length of the binarized signal binarized by the comparator. An offset potential control circuit for controlling the offset potential to make the appearance ratios of the high level period and the low level period of the binarized signal binarized by the comparator substantially equal to each other; A reference range setting circuit for extracting a binarized signal of a binarized signal in a range from a first signal length larger than the minimum signal length to a second signal length larger than the first signal length; The offset potential is corrected according to the signal length of the binarized signal within the range from the first signal length to the second signal length extracted by the reference range setting circuit. Thereby, the high-level period and the low-level period of the binarized signal in the range from the first signal length to the second signal length of the binarized signal binarized by the comparator are A data slice circuit comprising: an offset potential correction circuit that makes appearance ratios substantially equal. 3. A comparator for binarizing the high-frequency signal by comparing a high-frequency signal read as information recorded on an optical disk with a slice potential, and a binarized signal binarized by the comparator. A reference range setting circuit for extracting a binarized signal in a range from a first signal length larger than the minimum signal length to a second signal length larger than the first signal length; and the reference range setting circuit. By controlling the slice potential according to the signal length of the binarized signal in the range from the first signal length to the second signal length extracted by Slice potential control for making the appearance ratios of the high level period and the low level period of the binarized signal in the range from the first signal length to the second signal length of the binarized signal substantially equal Data slice circuit and a road. 4. A comparator for binarizing the high-frequency signal by comparing a high-frequency signal read as information recorded on an optical disk with a slice potential, and a binarized signal binarized by the comparator. A slice potential control circuit that controls the slice potential in accordance with a signal length to make the appearance ratios of a high-level period and a low-level period of the binarized signal binarized by the comparator substantially equal to each other; Reference for extracting a binarized signal in a range from a first signal length larger than the minimum signal length to a second signal length larger than the first signal length among the binarized binary signals. A range setting circuit, and a previous range according to the signal length of the binary signal in the range from the first signal length to the second signal length extracted by the reference range setting circuit. The high-level period of the binarized signal within the range from the first signal length to the second signal length of the binarized signal binarized by the comparator by correcting the slice potential. And a slice potential correction circuit for making the appearance ratio of the low level period substantially equal. 5. A binary signal longer than the first signal length by the reference range setting circuit masking the binary signal binarized by the comparator with a fixed-length mask signal shorter than the first signal length. 5. The data slice circuit according to claim 1, wherein a signal is extracted. 6. A PLL circuit for generating an extraction clock synchronized with a binarized signal binarized by a comparator and extracting information recorded on an optical disc from the binarized signal binarized by the comparator. 5. The apparatus according to claim 1, wherein the reference range setting circuit measures a signal length of the binarized signal binarized by the comparator with reference to the extracted clock. Or 5
A data slice circuit as described. 7. When the extracted clock generated by the PLL circuit is abnormal, the reference range setting circuit stops the operation of extracting the binarized signal in the range from the first signal length to the second signal length. 7. The data slice circuit according to claim 6, wherein a binarized signal having a signal length in the entire range is output.