JPH11282821A - 同時トランザクションを依存性で管理するための低占有度プロトコル - Google Patents

同時トランザクションを依存性で管理するための低占有度プロトコル

Info

Publication number
JPH11282821A
JPH11282821A JP10340925A JP34092598A JPH11282821A JP H11282821 A JPH11282821 A JP H11282821A JP 10340925 A JP10340925 A JP 10340925A JP 34092598 A JP34092598 A JP 34092598A JP H11282821 A JPH11282821 A JP H11282821A
Authority
JP
Japan
Prior art keywords
node
processor
data
packet
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10340925A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11282821A5 (https=
Inventor
Simon C Steely
シー ステイーリイ シモン
Madhumitra Sharma
シャルマ マドハミトラ
Stephen R Vandoren
アール ヴァンドーレン スティーヴン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of JPH11282821A publication Critical patent/JPH11282821A/ja
Publication of JPH11282821A5 publication Critical patent/JPH11282821A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP10340925A 1997-10-24 1998-10-26 同時トランザクションを依存性で管理するための低占有度プロトコル Pending JPH11282821A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/957565 1997-10-24
US08/957,565 US6154816A (en) 1997-10-24 1997-10-24 Low occupancy protocol for managing concurrent transactions with dependencies

Publications (2)

Publication Number Publication Date
JPH11282821A true JPH11282821A (ja) 1999-10-15
JPH11282821A5 JPH11282821A5 (https=) 2005-12-02

Family

ID=25499771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10340925A Pending JPH11282821A (ja) 1997-10-24 1998-10-26 同時トランザクションを依存性で管理するための低占有度プロトコル

Country Status (3)

Country Link
US (1) US6154816A (https=)
EP (1) EP0911736A1 (https=)
JP (1) JPH11282821A (https=)

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WO2007039933A1 (ja) * 2005-10-04 2007-04-12 Fujitsu Limited 演算処理装置
JP2010198490A (ja) * 2009-02-26 2010-09-09 Fujitsu Ltd キャッシュ制御装置

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US6973545B2 (en) * 2002-06-28 2005-12-06 Sun Microsystems, Inc. System with a directory based coherency protocol and split ownership and access right coherence mechanism
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WO2007039933A1 (ja) * 2005-10-04 2007-04-12 Fujitsu Limited 演算処理装置
JP2007102447A (ja) * 2005-10-04 2007-04-19 Fujitsu Ltd 演算処理装置
JP2010198490A (ja) * 2009-02-26 2010-09-09 Fujitsu Ltd キャッシュ制御装置

Also Published As

Publication number Publication date
US6154816A (en) 2000-11-28
EP0911736A1 (en) 1999-04-28

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