JPH112799A - Drive circuit for liquid crystal display device, liquid crystal display device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a pattern layout of a drive circuit of a liquid crystal display device generating a voltage according to a voltage - transmissivity characteristic of a pixel based on a digital image data input. SOLUTION: A voltage generation unit 11 constituting the drive circuit contains a first voltage generation means 13 generating a voltage based on upper N1 bits of the image data and a second voltage generation means 14 generating the voltage based on low-order N2 bits of the image data. The first voltage generation means 13 is arranged on a position far from a pixel area than the second voltage generation means 14, and a data bus 121 of upper N1 bits and a hold means holding the data are formed on the position far from the pixel area than the first voltage generation means 13, and the data bus 122 of lower-order N2 bits and the hold means holding the data are formed between the first voltage generation means 13 and the second voltage generation means 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal display device for supplying a voltage to a pixel of the liquid crystal display device via a data signal line, a liquid crystal display device including the driving circuit, and the liquid crystal display device. More particularly, the present invention relates to the drive circuit, the device, and the electronic device with improved circuit pattern layout.

[0002]

2. Description of the Related Art A liquid crystal display device is constructed by sealing liquid crystal between a pair of substrates. TFT (thin film transistor)
In one type of liquid crystal display device, a plurality of scanning lines and data signal lines are arranged on one substrate (insulating substrate, for example, glass) so as to intersect each other, and a pixel region formed by the matrix arrangement has A TFT having an amorphous silicon thin film or a polysilicon thin film as a channel and a pixel electrode are formed. The TFT has a gate controlled by a scanning signal supplied to the scanning line, a source connected to the data signal line, and a drain connected to the pixel electrode. TFT
Supplies the voltage supplied to the data signal line to the pixel electrode when the conduction is controlled (selected) by the scanning signal. A charge storage capacitor is formed in each pixel, and the charge of the voltage supplied at this time is held during the subsequent non-conduction time (non-selection period) of the TFT. On the other hand, a common electrode is formed on a counter substrate facing the substrate, and the voltage difference between the voltage applied to and held on each pixel electrode and the common electrode voltage is applied to the liquid crystal layer of each pixel sandwiched between the electrodes. By changing the applied and applied voltage, the arrangement of the liquid crystal molecules is changed to modulate the incident light.

When a transmissive liquid crystal panel is used, the transmittance of each pixel is obtained by modulating the light transmitted through the incident-side polarizing means with liquid crystal and then the amount of light transmitted through the output-side polarizing means. In the case of a reflection-type liquid crystal panel, the polarizing means disposed on the front surface of the liquid crystal panel serves as both the incident-side polarizing means and the outgoing-side polarizing means, and is determined by the amount of light obtained through the polarizing means. The rate of change in the amount of light that varies according to the voltage is determined as a non-linear voltage-transmittance characteristic of the pixel. In general, the voltage supplied from the driving circuit to each pixel corrects the non-linearity of the voltage-transmittance characteristic, and the change in the gradation obtained by the change in the transmittance according to the change in the applied voltage becomes uniform. Thus, the voltage change width according to the gradation change is made non-uniform. Such correction is generally called γ correction.

FIG. 17 shows a conventional driving circuit used in this type of liquid crystal display device. In FIG. 17, a first latch circuit 91A is provided on one substrate 90 of the liquid crystal panel.
Voltage generation unit 93 including second latch circuit 91B and digital / analog (D / A) conversion circuit 92
Are formed. This voltage generation unit 93 corresponds to each data signal line 971 arranged in the pixel region S,
The pixel regions S are provided side by side in the horizontal direction. Further, the voltage generation unit 93 has a scanning signal line 972 of the pixel region S.
Are connected to data buses 951 to 953 formed in parallel. These data buses 951 to 953 have R
Digital image data is output from the gamma correction circuits 941 to 943 and transmitted for each of the colors (red), G (green), and B (blue). γ correction circuit 9
In steps 41 to 943, γ correction is performed in the process of receiving 6-bit digital image data for each of RGB and converting this into 8-bit digital image data. That is, 8
From 2 ⁸ = 256 voltage levels that can be defined by the bit data, a 6-bit data input can be specified so that the gradation (transmittance) change in the voltage-transmittance characteristic of the pixel becomes linear. ⁶ = 64 voltage levels are selected, and the input 6-bit data is converted to 8-bit data specifying the selected 64 voltage levels, thereby performing γ correction.

In addition, three consecutive voltage generating units 9
A shift register 96 for taking in image data, which is commonly used for the three, is formed along data buses 951 to 953. The output of the shift register 96 is connected to the first latch circuit 91A so that the RGB digital image data transmitted to the data buses 951 to 953 is simultaneously taken into the first latch circuit 91A.
Each output of the shift register 96 is divided into three first latch circuits 91A with three voltage generation units 93 as one unit.
The latch control of the image data is performed.

In the circuit shown in FIG. 17, 6-bit digital image data D _AR ,
D _AG and D _AB are taken into γ correction circuits 941 to 943, respectively. Next, the gamma correction circuits 941 to 943 convert the image data D _AR , D _AG , and D _AB into 8-bit image data D _BR ,
D _BG and D _BB are converted to data buses 951-9, respectively.
Output to 53. Image data D _BR , D on each data bus
_BG, D _BB is a timing pulse from the shift register 96, respectively taken in the first latch circuit 91A. After the data is latched in the first latch circuits 91A of all the voltage generation units 93, 1 is generated by a latch pulse commonly supplied to all the second latch circuits 91B.
Image data corresponding to the number of horizontal pixels is sent to the second latch circuit 91B in a lump. The second latch circuit 91B is the captured image data D _B, and sends collectively to the D / A conversion circuit 92. Each D / A conversion circuit 92, the image data D _BR, based on D _BG, D _BB, analog voltage V _DRVR the reference voltage V _01, V ₀₂ as a reference voltage, V _DrvG, converted to V _DRVB. V _drvR , V _drvG , and V _drvB are output to each data signal line 971 of the liquid crystal display device.

As another configuration, as shown in FIG. 18, the D / A conversion circuit 92 can be provided with a gamma correction function without providing the gamma correction circuits 941 to 943. FIG.
FIG. 17 is a configuration diagram showing another conventional technique, and each symbol indicates the same as in FIG.

In this configuration, data buses 951-951
The 6-bit image data output on the N.953 corresponds to FIG.
In the same manner as described above, the data is sent to the D / A conversion circuit 92 via the first and second latch circuits 91A and 91B. The D / A conversion circuit 92 selects two adjacent voltages from among the nine reference voltages V _{01 to} V ₀₉ using the upper three bits of the digital image data, and selects the lower three bits of the digital image data. , The output voltages V _drvR , V _drvG , and V _drvB γ-corrected by _dividing the selected two voltages.
Can be generated.

As shown in FIG. 19, the drive circuit described in FIGS. 17 and 18 is replaced with a substrate 99 on which pixels of a liquid crystal panel are formed (corresponding to the substrate 90 in FIGS. 17 and 18).
The output of the drive circuit is formed by using a separate substrate from the data signal line 97 drawn out to the end of the liquid crystal panel substrate 99 via the mounting terminal member (flexible tape) 98.
It can also be output to one terminal.

Further, it is also possible to form a reflection type liquid crystal display device in which the liquid crystal panel substrate having the above-described drive circuit built therein is formed of a silicon substrate and the pixel electrodes are formed of metal.
In this case, a transistor formed on a silicon substrate is used as a switching element of the pixel, and a drive circuit including a transistor or the like can be formed outside the pixel region on the same silicon substrate. The voltage generation units of this drive circuit are arranged at a pitch that matches the arrangement pitch of the data signal lines in the pixel area.

[0011]

FIG. 17 (and FIG. 18)
In the drive circuit of FIG. 8, 8-bit (6 bits in FIG. 18) image data is input to the voltage generation unit 93, and therefore, the data bus having an 8-bit or 6-bit width is connected to the first voltage generation unit 93 by the first bus. Latch circuit 91A,
It must be arranged over the second latch circuit 91B and the D / A conversion circuit 92. Therefore, the width of each voltage generation unit (the width in the horizontal pixel direction, that is, the width of the pixel region in the data signal line arrangement direction) is increased. In particular, when a driving circuit is formed using TFT elements on an insulating substrate such as glass and the circuit elements are separated from the wiring region in a planar manner, the circuit arrangement width is increased. Further, if a multilayer wiring is formed on the upper layer of the TFT element in an attempt to reduce the circuit arrangement width, the number of manufacturing steps is increased, and the manufacturing yield of the device is significantly reduced.

Since it is necessary to match the arrangement pitch of the data signal lines with that of the voltage generating unit, as shown in FIGS. 17 and 18, in order to secure the width of the data bus of 8 bits or 6 bits, When the width of the voltage generation unit is increased, the horizontal arrangement pitch of the data signal lines 971 cannot be reduced. Therefore, the pixels of the liquid crystal panel are arranged in the horizontal direction at substantially the same pitch as the arrangement pitch of the data signal lines to which they are connected. The size cannot be reduced, and a high-definition liquid crystal panel cannot be formed.

Further, in the drive circuit of FIG. 18, the number of reference voltages selected in the D / A conversion circuit 92 increases, and the circuit configuration of the voltage generation unit becomes large. The width becomes wide, and the arrangement pitch of each of the voltage generation unit 93, the data signal line 971, and the pixel cannot be reduced.

Further, in the case of FIG. 19, the image data is transmitted to the liquid crystal panel substrate 99 via the mounting terminal member 98, so that the balance of the electrical characteristics (impedance of the lines) of each signal line is lost. The data signal may be attenuated due to noise. Further, as compared with the case where a driving circuit is formed on a liquid crystal panel substrate, the number of components is increased, and the liquid crystal panel, the mounting terminal member, and the driving circuit are separate members, so that the overall size of the liquid crystal display device cannot be reduced.

Further, even when a substrate on which a pixel electrode of a liquid crystal panel is formed is a silicon substrate, and a driving circuit is formed on the substrate, the TFT formed on the insulating substrate is replaced by the transistor formed on the silicon substrate. There is a problem similar to that described with reference to FIGS. 17 and 18 only by changing.

An object of the present invention is to improve the pattern layout of a drive circuit so that the drive circuit is adjusted to the pixel pitch of the liquid crystal display device, thereby not only reducing the mounting area of the drive circuit. Another object of the present invention is to promote downsizing of a liquid crystal display device including the driving circuit and an electronic device having the liquid crystal display device, and to guarantee improvement in image quality of a display image of the display device.

[0017]

A driving circuit of a liquid crystal display device according to the present invention inputs digital image data (N bits: N is plural) and supplies the data to pixels via a data signal line based on the input data. To generate a voltage
The drive circuit includes a predetermined number of voltage generation units arranged outside the pixel region of the liquid crystal display device on the substrate in a manner corresponding to the data signal lines.

In the present invention, the voltage generation unit converts the input digital image data into a voltage in which the voltage-transmittance characteristic of the pixel is corrected as much as possible (so-called γ).
Correction function), and includes a first voltage generation unit and a second voltage generation unit. It is located at a far position.

The first voltage generating means generates a voltage obtained by correcting the voltage-transmittance characteristic of the pixel with coarse accuracy from a predetermined number N1 bits of the digital image data. Also, the second
The voltage generating means generates a voltage level corrected with finer accuracy according to the voltage-transmittance characteristic of the pixel based on the voltage corrected with coarse accuracy. Note that the accuracy of correction means the accuracy of correction for approximating ideal voltage-transmittance characteristics. In other words, correction with coarse accuracy means correcting the transmittance characteristic change curve at a rough level with a large voltage change width, and correction with fine accuracy means at a finer level with a small voltage change width. This means that the change curve of the transmittance characteristic is corrected.

In a more specific embodiment, the first voltage generating unit is configured to output the first voltage of the digital image data.
Selects two voltages from a plurality of voltages different from each other on the basis of a predetermined number of bit data of the digital image data. The two voltages selected by the means are divided, and one divided voltage is selected.

In addition, N is used for the first voltage generating means.
A data bus for transmitting 1-bit data or a first holding means for holding the data is arranged at a position farther from the pixel area than the first voltage generating means, and is provided for the second voltage generating means. A data bus for transmitting N2 bit data or a second holding means for holding the data is arranged between the first voltage generating means and the second voltage generating means.

The voltage generation of each of the voltage generation units according to the present invention is, specifically, performed by the first voltage generation unit.
Two voltages are selected from a plurality of voltages different from each other based on the N1 bit data of the digital image data. Operates to divide the two voltages selected by (1) and to select one divided voltage.

First, the N1 bit data bus or the first holding means and the N2 bit data bus or the second holding means are formed between the first voltage generating means and the second voltage generating means. However, the N1 bit data input / output to / from the N1 bit data bus and the holding means is easily affected by an electric influence (increase in line impedance, occurrence of crosstalk, etc.) from a power supply line or the like. Also, an N2 bit data bus or a second holding means could be formed between the second voltage generating means and the pixel area of the liquid crystal display device.
The N2 bit data input / output to / from the bit data bus and the second holding unit is affected by the electrical influence (increase in line capacitance) from the sealing material (see FIG. 3) formed around the pixel area of the liquid crystal display device. Etc.).

In consideration of the above circumstances, in the driving circuit of the present invention, the first holding means for holding the N1 bit data for the data bus of the N1 bit data or the first voltage generating means is the first bus. The second voltage generator is disposed at a position farther from the pixel area than the voltage generator, and the second voltage storage means for holding the N2 bit data for the data bus of the N2 bit data or the second voltage generation means includes the first voltage generation means and the first voltage generation means. It is arranged between the second voltage generating means. This gives N
Input to the 1-bit data bus or the first holding means /
The electrical characteristics of the output data and the data input / output to the N2-bit data bus or the second holding means are also improved.

The arrangement pitch of the N1 bit data buses and circuit elements for voltage generation may be ensured as the arrangement pitch of the first voltage generation means. Since the arrangement pitch of the data buses and the circuit elements for voltage generation corresponding to the number of N2 bits may be secured as the arrangement pitch, the circuit arrangement width in the horizontal pixel direction of the voltage generation unit can be reduced. it can.

Further, in the present invention, the first voltage generating means holds the value of the N1 bit of the digital image data and the N1 bit data output from the first holding means. In addition, a voltage level selection circuit that selects and outputs two adjacent reference level voltages from the plurality of reference level voltages can be included. Further, the second voltage generating means holds a second holding means for holding N2 bit data of the digital image data, and the N2 output from the second holding means.
It is also possible to include a voltage dividing circuit for dividing the voltage between the two voltages selected by the voltage level selecting circuit in accordance with the value of the bit to generate an output voltage.

Here, the voltage level selection circuit, 2 ^N1 +1
, Two voltages can be selected. Such a voltage level selection circuit can be composed of a plurality of switches and a plurality of decoder elements, as described later.

The number of voltages that can be divided and selected by the voltage dividing circuit can be 2 ^N2 . For example, when the number of bits of N2 bits is 3, a voltage obtained by dividing the voltage between the two voltages selected by the voltage level selection circuit into 2 ^N2 can be generated and selected. Such a voltage dividing circuit can be composed of a plurality of resistors, a plurality of switches, and a plurality of decoder elements, as described later.

In the case of an active matrix type liquid crystal display device, particularly, the resistance of the second voltage generating means is changed by changing the drain electrode and the source electrode of the transistor of the pixel and the transistors constituting the first and second voltage generating means. The manufacturing process can be simplified by forming the same process.

In the present invention, when the number of voltages to be selected in the first voltage generating means is 2 ^N1 + 1,
The first to second ^N1 +1 voltage supply lines can be formed at intervals from one another across a plurality of voltage generation units in a direction parallel to the scanning signal lines of the pixel region S. In addition, the voltage value applied to the voltage supply line is sequentially increased or
It is set so that it becomes lower sequentially.

Further, the first memory for holding N1 bit data
Signal line connecting the holding means and the voltage level selection circuit,
The first output line from which the voltage selected by the voltage level selection circuit is output is also arranged in the circuit arrangement direction of the voltage generation unit (the direction parallel to the data signal line).

Each of the voltage level selection circuits comprises a first to a second ^N1 comprising two switches arranged side by side and a decoder element arranged between the two switches.
Consisting of a selection unit. J-th (j = 1, 2,..., 2 ^N1 )
Is provided between the j-th and j + 1-th voltage supply lines. One terminal (voltage input terminal) of a switch located far from the pixel region of the liquid crystal display device among the two switches of the j-th selection unit is connected to the j-th voltage supply line and the switch is connected to the j-th voltage supply line. Is connected to one of the first output lines. One terminal (voltage input terminal) of the switch arranged near the pixel area of the liquid crystal display device is connected to the (j + 1) th voltage supply line, and the other terminal (voltage output terminal) of the switch is connected to the second terminal. Output line. Then, the decoder element of the j-th selecting unit is configured to send an ON operation signal to two switches of the selecting unit when the value of the N1 bit is j−1.

In the present invention, when the number of voltages that can be divided by the voltage dividing circuit is 2 ^N2 , a signal line connecting the second holding means for holding N2-bit data and the voltage dividing circuit is provided. , And a second output line output from the voltage divider circuit,
It is formed in the circuit arrangement direction of the voltage generation unit (direction parallel to the data signal line). Further, the voltage dividing circuit includes a first to a second ^N2 selection unit, which includes a resistor, a switch, and a decoder element, and is sequentially arranged from a side far from a display area of the liquid crystal display device to a side close to the display area. Become.

The resistance of each selector is connected in series in the circuit arrangement direction of the voltage generation unit (the direction parallel to the data signal line). One end of a switch of each selection unit is connected to a voltage output terminal of the resistor, or is connected to a terminal closer to a pixel region of a liquid crystal display device among two terminals of the resistor, The other ends of the switches are respectively connected to the second output lines. When a reset signal is supplied from a reset signal line formed in a horizontal pixel direction (a direction parallel to the scanning signal line), a switch of each of the selection units switches between two voltages selected by the voltage level selection circuit. One is forcibly supplied to the data signal line.

In the driving circuit for a liquid crystal display device according to the present invention, when each voltage generating unit is disposed at one end or both ends of the data signal line, the voltage generation unit is connected to the data signal line (or pixel). They are arranged at a pitch substantially equal to the arrangement pitch.

On the other hand, a plurality of voltage generating units are arranged at one end of the data signal line and connected to one end of the data signal line; In the case where the second voltage generation means is arranged on the other end side and connected to the other end of the data signal line, the arrangement pitch is twice the arrangement pitch of the data signal lines (or pixels). The width of the minute can be used as the circuit width of each voltage generation unit, and the wiring and the pattern of the circuit element can have a margin. Usually, the arrangement at a pitch twice the arrangement pitch of the data signal lines (or pixels) is preferable.

That is, the voltage generation units may be arranged at substantially the same pitch as an integer multiple (1 or 2 times) of the pixel arrangement pitch or the data signal line arrangement pitch of the liquid crystal display device. preferable. Here, “substantially (substantially)” means that the arrangement interval of the voltage generation units does not have to be completely the same as the pixel arrangement pitch or an integral multiple of the data signal line arrangement pitch. ing. For example, by adding a special additional circuit to one of the adjacent voltage generation units or by modifying a part of the circuit, one of the voltage generation units expands more than the arrangement pitch of the pixels or the data signal lines, and the adjacent voltage generation unit expands. The array width may be widened on the unit side. However, if more than half of the plurality of voltage generation units are arranged at the same pitch as an integral multiple of the arrangement pitch of the pixels and the data signal lines, this also applies. In a manufacturing process, a specific group of voltage generating units and a group of other voltage generating units may be formed by different manufacturing processes. In such a case, in order to secure a margin at the boundary between the groups of the voltage generation units, the voltage generation unit is provided with a circuit arrangement width smaller than the arrangement pitch of the pixels of the liquid crystal display device or the arrangement pitch of the data signal lines. And a gap may be provided between the units. As described above, even if an interval is provided between the voltage generation units, if the arrangement pitch of a predetermined portion of the unit is an integral multiple of the arrangement pitch of the pixels and the data signal lines (as described above, the arrangement pitch of more than half of the unit is larger). If the pitch is an integral multiple thereof), it is also included.

If a plurality of voltage generating units are all arranged at one end of the data signal line, the arrangement pitch of the units and the arrangement pitch of pixels or data signal lines become substantially the same. However, if the arrangement of the voltage generation units connected to each data signal line is on the opposite side, one voltage generation unit is provided for two data signal lines at one end of the data signal lines. Therefore, the arrangement pitch of the voltage generation units is substantially equal to twice the arrangement pitch of the pixels or the data signal lines.

That is, when the voltage generation units are provided on both sides of the data signal line so as to sandwich the pixel region, for example, the voltage generation units are alternately provided for each data signal line at the opposite end of the data signal line. When the voltage generation units are provided, one voltage generation unit may be disposed on each of one side and the other side of the pixel region for two data signal lines. "Upper" is twice as long as the arrangement pitch of the data signal lines. Note that, instead of changing the location of the voltage generation unit for each data signal line, the three data signal lines of RGB are used as a unit. A voltage generation unit may be provided.

A liquid crystal display device according to the present invention includes the above driving circuit. In particular, when the pixel electrode circuit is formed by a TFT using a polysilicon layer formed on an insulating substrate such as a glass substrate as a channel, the driving circuit can be easily formed as described above.

Further, an electronic apparatus having a liquid crystal display device according to the present invention is characterized by using the above liquid crystal display device.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a diagram schematically showing a first embodiment of a drive circuit of a color liquid crystal display device. In the first embodiment, a case is shown in which a data line side driving circuit is arranged only on one end side of a data signal line. Each of the voltage generation units 11 constituting the drive circuit is composed of one substrate (glass substrate) 10 of a pair of substrates constituting a liquid crystal panel.
It is formed in a peripheral region outside the pixel region S of the upper liquid crystal display device.

In the pixel region S, a plurality of scanning signal lines L _S and a plurality of data signal lines L _D are arranged in a matrix on the glass substrate 10. A TFT (thin film transistor), a pixel electrode, and a charge storage capacitor are formed. The TFT of each pixel has a gate connected to the scanning signal line L _S , a source connected to the data signal line L _D , and a drain connected to the pixel electrode and the storage capacitor. On the other hand, the counter substrate sandwiching a liquid crystal layer opposite the substrate 10 is a common electrode are formed, the liquid crystal layer sandwiched between the pixel electrode and the common electrode, a data signal line L _D, via the TFT supply The potential difference between the applied potential and the common electrode potential is applied. As will be described later in detail, the voltage applied to the pixel electrode is changed at a predetermined period (usually one vertical scanning period or a shorter period) with respect to the common electrode potential in order to drive the liquid crystal by AC. Must be inverted.

[0044] Each voltage generating unit 11 includes a first voltage generating block 13 and the second voltage generating blocks arranged in a direction (vertical pixel direction) which is arranged in the data signal line L _D 1
Consists of four. As shown in FIG. 1, each voltage generation unit 11 includes a plurality of data signal lines L _D at substantially the same interval as the pixel arrangement pitch (or data signal line arrangement pitch) W in the horizontal pixel direction of the liquid crystal display device. Are arranged side by side in the arrangement direction. Voltage generating unit 11 is provided minutes equals the number of data signal lines L _D in the pixel region S. The pixel area S of the substrate 10 of each voltage generation unit 11
R (red), G (green), B (blue)
Out of the N bits of the N-bit digital image data D _AR , D _AG , and D _AB , the data bus 121 for transmitting the upper N1 bits has the scanning signal line of the pixel area S for each of R, G, and B colors. It is formed over a plurality of voltage generation units 11 in a direction parallel to L _S.

Further, between the first voltage generation block 13 and the second voltage generation block 14 constituting each voltage generation unit 11, a data bus 122 of lower N2 bits of the digital image data is provided. But R, G, B
Each of the colors is arranged over a plurality of voltage generating units.

Since the processing for each of the R, G, and B colors is the same, the operation of the voltage generation unit that generates an output voltage for the R pixel based on the digital image data of the R pixel will be described below.

The first voltage generation block 13 includes first holding means (latch means 131) and a voltage generation section 132. The data bus 121 of the upper N1 bits (3 bits in FIG. 1) is connected to the latch unit 131, and the N1 bit output of the latch unit 131 is input to the voltage generation unit 132. The latch unit 131 has a configuration in which two CMOS inverters are connected in a feedback manner, and the input or output of the inverter whose input is connected to the data bus 121 is controlled by a clock signal. Each inverter is a P-channel T
FT and N-channel TFT. Data input from the data bus 121 to the latch means 131 is performed according to the shift register 9 shown in FIGS.
As in the case of 6, control is performed by an output from a shift register (not shown). That is, the latch control of the latch means 131 is performed in the same manner as in the conventional technique as shown in FIG. 17 and FIG. A latch control clock is sequentially output from the shift register according to the shift. In accordance with the output timing of the latch control clock, the data bus 12 is provided to the latch means 131 of the plurality of voltage generation units 11 arranged in the horizontal pixel direction.
Digital image data of one horizontal pixel (N1 bits per pixel) transmitted in time series to 1 are sequentially captured.

The voltage generator 132 is connected to the reference voltage supply line L _V1
The reference voltages V ₁ applied to the (located across the voltage generating means in a direction parallel to the scanning signal line L _S in the pixel region S), generates a voltage V ₂ corresponding to the N1-bit input.

The voltage V ₂ generated by the voltage generator 132 is
For N-bit digital image data, the voltage is a voltage obtained by correcting the voltage-transmittance characteristic of the pixel with coarse accuracy (accuracy based on the data amount of N1 bits). Note that various configurations can be considered as the configuration of the voltage generation unit 132.
And the reference voltages V ₁ and the potential difference between the ground potential charged in the capacitor, by boosting at the magnification corresponding voltage difference N1-bit data, it is possible to generate a voltage V _2. Another configuration, the reference voltages V ₁ the resistance value to be inserted between the ground potential, the voltage V ₂ from the resistor terminals is varied based on the data in the N1 bits can be voltage generation. Further, if V ₁ is composed of a number of reference voltages may be the voltage generated by selecting a voltage V ₂ in accordance with the N1-bit data. This voltage generator 1
The voltage generation in 32 is performed simultaneously and in parallel by each latch unit 131 during the next horizontal scanning period in which the plurality of latch units 131 capture image data for one horizontal pixel within one horizontal scanning period.

The second voltage generation block 14 comprises a second holding means (latch means) 141 and a voltage generation section 142. The lower N2 bit data bus 122 is connected to the latch unit 141, and the N2 bit output of the latch unit 141 is input to the voltage generation unit 142. Since data is transmitted to the data bus 122 synchronously with the same cycle as the data bus 121, the latch in the latch means 141 is synchronized with the latch means 131 and the same voltage is applied to each voltage generating unit. Latch control is performed by the shift register output. Here, the digital image data for determining the gradation of one pixel of R is N-bit data obtained by adding N1 bits of the data bus 121 and N2 bits of the data bus 122.

The voltage generation section 142 is provided with the above-described voltage generation section 1.
32 apply voltage V ₂ from, for generating a voltage V _DRVR based on N2-bit data. If the boosting circuit voltage generator 142, a potential difference between the voltage V ₂ ground potential, boosted by step-up factor corresponding to N2-bit digital image data, to generate one of the boosted voltage. However, it is necessary to make the step-up factor smaller than that of the voltage generator 132 and to improve the accuracy of correcting the voltage-transmittance characteristic. Further, the voltage generating unit 142 when a voltage divider circuit, the potential difference between the reference voltage V ₂ and the ground potential, divided according to N2-bit digital image data to generate one voltage. However, it is necessary to make the divided voltage width smaller than that in the case of the voltage generation unit 132, and to increase the accuracy of the correction of the voltage-transmittance characteristic.

FIG. 1 also shows a voltage generator for generating the output voltages V _drvG and V _drvB for the G pixel and the B pixel, but operates in the same manner as the voltage generation unit for the R pixel. Eggplant

In each of the voltage generating units, the voltage generated by the voltage generating section 142 is a voltage that corrects the voltage-transmittance characteristic of the liquid crystal pixel as finely as possible for N-bit digital image data. Has become. That is, in the voltage generator 142, the voltage generator 132 corrects the characteristic curve of the voltage-transmittance characteristic with a smaller voltage change width. In other words, the correction of the voltage-transmittance with a large change width is performed in the first voltage generation block 13, and the correction with a smaller fine accuracy with a small change width is performed in the second voltage generation block 14. Therefore, for example, if the voltage generating unit 142 is a circuit that boosts the voltage, the boosting factor when boosting V ₂ with reference to some reference voltage (for example, ground potential) based on the N2 bit data is determined by the voltage generating unit 132. V _drvR is generated by setting the voltage to be smaller than the case and boosting. Further, the voltage generator 142
But if the circuit pressure voltage of, based on the N2-bit data, the partial pressure ratio when dividing the voltage V _2, pressure is set smaller than the variation in the production possible voltage by the voltage generator 132 min, Generate V _drvR .

As described above, the upper N1 bit data bus 121 and the first holding unit 1 for holding this data
Numerals 31 are formed on the side farther from the pixel area S of the liquid crystal display device than the voltage generation unit of each voltage generation unit 11, and the lower N
The two-bit data bus 122 and the second holding means for holding this data are formed between the first voltage generation block 13 and the second voltage generation block 14. Therefore, the first voltage generation block 13 only needs to form the wirings for the number of upper N1 bits in the direction in which the data signal lines are arranged. The circuit arrangement width in the horizontal pixel direction of the generation unit can be reduced. Further, since the second voltage generation block 14 only needs to form the wirings for the number of lower N2 bits in the direction in which the data signal lines are arranged, the number of wirings arranged and formed in parallel is reduced as compared with the prior art, and the voltage is reduced. The circuit arrangement width in the horizontal pixel direction of the generation unit can be reduced.

Therefore, the circuit width of the voltage generating unit 11 in the horizontal pixel direction can be reduced as compared with the conventional driving circuit, and the pixel width W (or the arrangement pitch of the data signal lines) of the liquid crystal display device can be reduced. This makes it easier to narrow the layout. Accordingly, on the liquid crystal panel side, the arrangement pitch of the data signal lines can be narrowed accordingly, and the arrangement pitch of the pixels can also be narrowed, so that a high definition panel can be formed.

In the first embodiment shown in FIG.
In one-to-one correspondence with the data signal lines and the array pitch of the pixels, but the arrangement pitch of the voltage generating unit is set to be substantially equal, it is arranged a voltage generating unit on the opposite side of the data signal line L _D, a predetermined Number of units (for example, one, three, six
If the voltage generation units are alternately arranged on the opposite side for each of the data signal lines (the...,...), The arrangement pitch of the voltage generation units can be made approximately twice as wide as a margin. For example, odd-numbered voltage supplies drive circuit to the data signal line (in the drawing, the voltage generating unit for generating a voltage generating unit and a V _DRVB to generate a V _DRVR) in FIG. 1, the end that is shown in the data signal line And a drive circuit (a voltage generation unit for generating V _drvG in the figure) that supplies a voltage to the even-numbered data signal lines is disposed at an end on the opposite side (not shown) of the data signal lines. The voltage generation unit is 2
Since one voltage generation unit is arranged for one data signal line, there is room for arrangement. Therefore, the arrangement pitch of the data signal lines and the pixels can be narrowed, so that the pixels of the liquid crystal panel can be further refined.

Although the N1 bit data bus 121 is arranged outside the latch 131 in FIG.
Since 31 bits are arranged by N1 bits, a latch 131 for latching the data may be arranged adjacent to the data bus 121 of each bit. That is, each data bus 121
May be arranged at intervals, and a 1-bit latch circuit 131 for latching the bit data of the data bus may be arranged within the interval. In the case of FIG. 1, the arrangement of the three data buses 121 and the arrangement of the three latches 131 are alternately arranged when viewed from the data signal line side. This configuration can be implemented similarly for each of the RGB voltage generation units, and the data bus 122 and the latch 14 on the second voltage generation block 14 side.
The same configuration can be adopted for the device No. 1.

[Second Embodiment] FIG. 2 is a diagram schematically showing a second embodiment of a driving circuit of a color liquid crystal display device. In the second embodiment, a voltage level selection circuit 232 is used instead of the voltage generation section 132 of FIG.
The second embodiment is different from the first embodiment in that a voltage dividing circuit 242 is used instead of the second embodiment, and the other configuration is basically the same as the first embodiment. In FIG. 2, the first voltage generating block is 23, the second voltage generating block is 24, the voltage generating unit is 21, the upper N1 bit data bus of the N-bit digital image data is 221 and the lower bus is 221. N2
222 bit data bus, holding means (latch circuit)
Are indicated by 231 and 241.

In the second embodiment, image data is taken into the latch circuits 231 from the data bus 221 through which N1 bits (3 bits in the embodiment) of digital image data is transmitted for each of the RGB colors. ,
The operation of taking image data into the latch circuits 232 from the data bus 222 through which N2 bits (3 bits in the example) of digital image data is transmitted for each color of RGB is the same as in the first embodiment. Also, the first
Similarly to the embodiment, the digital image data is composed of N bits (N = N1 + N2), and is data indicating a gradation level by N bits.

[0060] In the second embodiment, the voltage level selection circuit 232 of the first voltage generating block 23, 2 ^N1 +1 amino reference level voltage _{V 11 ~V 1i (i = 2} N1 +1) is supplied I have. Each of the voltage level selection circuits 232 is connected to the adjacent two
Voltage levels V _1m , V _1n (m = 1, 2,..., 8,
n = m + 1). These two voltage levels correspond to voltages obtained by correcting the voltage-transmittance characteristics of the liquid crystal pixels with coarse accuracy (accuracy based on the data amount of N1 bits) for digital image data of N bits.

The operation of the voltage generation unit that generates an output voltage for the R pixel based on the digital image data of the R pixel will be described below.

In the voltage level selection circuit 232, when the number of upper N1 bits is 3, nine reference level voltages V _{11 to} V ₁₉ are supplied by nine reference voltage supply lines. The reference voltage supply lines are arranged in parallel with each other over a plurality of voltage generation units in the horizontal pixel direction. Reference level voltage _{V 11, V 12, V 13} , V 14, V 15, V 16, V
_{17, V 18, V 19 (} V 11> V 12> V 13> V 14> V 15> V
_{16> V 17> V 18>} V 19) is, N (= higher N1 + lower N
2) Each bit of digital image data is (000)
000), (001000), (010000), (0
11000), (100000), (101000),
(110000), (111000), (11111)
When (1) is satisfied (the first three bits in the parentheses are N1 and the last three bits are N2), the voltage is to be supplied to the pixel electrode of the pixel corresponding to the image data. Of these nine reference voltages, the decimal values of the N-bit image data are “0” and “6”.
V ₁₁ and V ₁₉ is selected when the 3 ", the voltage of the liquid crystal pixel - corresponding to the upper limit and the lower limit of the applied voltage range set on the basis of the transmittance characteristic. For example, using a TN type liquid crystal panel,
If the polarization axis of the set positive in a pair of polarizers sandwiching the panel (normally white), the applied voltage is V ₁₁ when the voltage of the pixel - white level display in the transmittance characteristics, V
_{When it is 19} , black level is displayed. Conversely, setting the polarization axis of one polarizer if negative (normally black), V ₁₁ when the voltage - black display in transmittance characteristics and white display when the V _19.

For V _{12 to} V ₁₈ , the decimal value of the digital image data is “7”, “14”, “21”
These voltages are selected when “28”, “35”, “42”, “49”, and “56”, respectively, and their voltage change widths indicate the nonlinearity of the voltage-transmittance characteristics of the negative or positive liquid crystal. The voltage difference is set such that the voltage difference between them is made non-uniform at intervals (even if there are some equally-spaced portions as long as the nonlinearity of the transmittance characteristic can be corrected thereby). . That is, when the reference voltage of V ₁₁ ~V ₁₉ is sequentially applied to the pixel, the ratio of the display gradation level (transmittance) changes accordingly to equal respectively, the reference voltage level is set Will be.

Now, in the voltage generation block 23,
When the upper N1 bits of the image data latched by the latch means 231 are (001), the voltage level selection circuit 232 outputs the voltage V _{12 to} be applied to the pixel electrode of the pixel when the digital image data is (001000). when the digital image data to select the voltage V ₁₃ to be applied when a (010000). When the upper N1 bit is (010), the voltage level selection circuit 23
2, the voltage V ₁₃ to be applied to the pixel electrode of the pixel when the digital image data is (010000), the digital image data to select the voltage V ₁₄ to be applied when a (011000). In this manner, two reference voltages are selected according to the value of the upper N1 bit: the voltage to be originally applied to the liquid crystal when the value is N1, and the voltage of the next level adjacent to the voltage level. Become like

[0065] Note that, in practice, V ₁₁ and V ₁₉ Tonouchi one actually not be applied to the pixel is used only as a reference voltage of the voltage partial pressure in the voltage divider circuit 242 as described below 8 levels (typically 2 ^N1 levels)
Voltage is used.

Next, the two voltage levels V _1m and V _1n (n = m + 1) selected by the first voltage generation block 23 are applied to the two voltage division circuits 242 of the second voltage generation block 24. It is input by the output line, and the latch circuit 2
41, the voltage level V
A partial pressure of _{1 m} and V _1n is applied. For example, when the number of bits of the lower N2 bits is 3, the voltage dividing circuit 242 connects the two reference level voltage levels V _1m and V _1n selected by the voltage level selecting circuit 232 with 2 ^N2 (= 8) And a voltage V _drvR corresponding to the value of the lower N2 bits is generated. For example the upper N1 bits and lower N2 bits are both 3 bits in the case where V ₁₂ and V ₁₃ by a first voltage generation block 23 has been selected (i.e., if it is higher N1-bit (001)), Lower N
When the two bits are (010), the voltage dividing circuit 242
Selects and outputs the third lowest voltage among the divided voltages. The output voltage V _drvR corresponds to a voltage obtained by correcting a characteristic curve of a voltage-transmittance characteristic of a pixel with a fine precision (accuracy based on an N-bit data amount) for N-bit digital image data.

That is, in the second embodiment, the first
In the correction of the non-linearity of the voltage-transmittance in the voltage generation block 23 of FIG.
The data is divided so as to have a uniform change in transmittance with a data amount of 1 bit, and a divided range (transmittance level) is selected from the divided data according to the value of the N1 bit data. The number obtained by dividing this transmittance level (vertical axis) of the voltage-transmittance characteristic is N
Since it is determined only by the amount of data of one bit, the level of coarse correction is obtained. That is, if the number of N1 bits is 3 bits, the number of divisions is 2 ³ = 8. In the transmittance division range selected in accordance with the value of N1, the applied voltage range corresponding to the transmittance range is determined based on the characteristic curve of the voltage-transmittance characteristic. The voltages at both ends of this voltage range are two reference voltage levels selected and output from the first voltage generation block 23. Further, the second voltage generation block 24
Then, the two supplied voltages are divided at an equal ratio according to the data amount of N2 bits. If the number of N2 bits is 3, the number of divisions is 2 ³ = 8. Then, one voltage value is selected from the eight divisions according to the value of the N2 bit data. By this voltage selection, the transmittance (gray level) is determined based on the voltage-transmittance characteristics. That is, the voltage division number according to the N2 bit data amount is 8, but from the overall characteristic curve of the voltage-transmittance characteristic, after selecting from the voltage range division number 8 according to the N1 bit data amount,
Since there is a voltage selection based on the N2 bit data amount, the voltage generation in the second voltage generation block 24 is substantially a voltage value selection based on the data amount of N1 + N2 = N bits of image data. Therefore, the second voltage generation block 24 is more effective than the voltage generation in the first voltage generation block 23.
Is a correction of the voltage-transmittance characteristic with substantially fine precision.

Also in the second embodiment, the data bus 221 for the upper N1 bits and the holding means (latch circuit) 231 for latching the data are provided in the display area S of the liquid crystal display device.
From the data bus 2 of the lower N2 bits.
22 and holding means (latch circuit) 241 for latching the data are formed between the first voltage generating means 23 and the second voltage generating means 24, so that a large number of the voltage generating units are arranged in the circuit arrangement direction. This eliminates the need to route the data bus and makes it easier to make the circuit width of the voltage generation unit narrower in accordance with the pixel width W of the liquid crystal display device (or the arrangement pitch of the data signal lines) as compared with the conventional drive circuit. Becomes Accordingly, on the liquid crystal panel side, the arrangement pitch of the data signal lines can be narrowed accordingly, and the arrangement pitch of the pixels can also be narrowed, so that a high definition panel can be formed.

In the first embodiment shown in FIG. 2,
In one-to-one correspondence with the data signal lines and the array pitch of the pixels, but the arrangement pitch of the voltage generating unit is set to be substantially equal, it is arranged a voltage generating unit on the opposite side of the data signal line L _D, a predetermined Number of units (for example, one, three, six
If the voltage generation units are alternately arranged on the opposite side for each of the data signal lines (the...,...), The arrangement pitch of the voltage generation units can be made approximately twice as wide as a margin. For example, odd-numbered voltage supplies drive circuit to the data signal line (in the drawing, the voltage generating unit for generating a voltage generating unit and a V _DRVB to generate a V _DRVR) in FIG. 2, the end that is shown in the data signal line And a drive circuit (a voltage generation unit for generating V _drvG in the figure) that supplies a voltage to the even-numbered data signal lines is disposed at an end on the opposite side (not shown) of the data signal lines. The voltage generation unit is 2
Since one voltage generation unit is arranged for one data signal line, there is room for arrangement. Therefore, the arrangement pitch of the data signal lines and the pixels can be narrowed, so that the pixels of the liquid crystal panel can be further refined.

Although the N1 bit data bus 221 is arranged outside the latch 231 in FIG.
Since 31 bits are arranged by N1 bits, a latch 231 for latching the data may be arranged adjacent to the data bus 221 of each bit. That is, each data bus 221
May be arranged at intervals, and a 1-bit latch circuit 231 for latching bit data of the data bus may be arranged within the interval. In the case of FIG. 2, the arrangement of the three data buses 221 and the arrangement of the three latches 231 are alternately arranged when viewed from the data signal line side. This configuration can be implemented similarly for each of the RGB voltage generation units, and the data bus 222 and the latch 24 on the second voltage generation block 24 side.
The same configuration can be adopted for the device No. 1.

[Third Embodiment] An embodiment in which the second embodiment is more specific will be described with reference to FIGS.

The driving circuit of the present invention is used to drive a liquid crystal display device 301 as shown in the plan view of FIG. 3A, the cross-sectional view of FIG. 3B, and the vertical cross-sectional view of FIG. . In FIG. 3, a glass substrate (active matrix substrate) 303 and a counter substrate (substrate on which color filters are arranged as necessary) 302 are adhered and fixed by a sealing material 304 around each substrate, and a liquid crystal is provided in the gap. 305 is injected and pinched. A light-shielding pattern 306 is formed around the glass substrate 302 except for a peripheral side portion. A TFT, a pixel electrode, an output signal line (data An active matrix portion 307 including signal lines, scanning lines, and the like is formed. Further, in the peripheral portion of the active matrix section 307, the drive circuits 30 in which the above-described voltage generation units are formed in the same number as the number of pixel columns of the pixel array are provided.
8 and the scanning line driving circuit 309 are constituted by TFTs or the like. In addition, outside the scanning line driving circuit 309,
A mounting terminal member (flexible substrate) 310 is provided,
The liquid crystal display device 30 is provided via the flexible substrate 310.
1 and various clock signals are input.

FIG. 4 is a diagram showing the first voltage generation block 41 of each voltage generation unit 4 constituting the drive circuit 308 shown in FIG. In FIG. 4, a plurality of first voltage generation blocks 41 have an arrangement substantially the same as the pixel arrangement pitch W (see FIG. 5) (or the arrangement pitch of data signal lines) of the liquid crystal display device shown in FIG. They are arranged at a pitch along the data signal line arrangement direction of the pixel region S. In each of the voltage generation blocks 41, a circuit element and a wiring layer are arranged in the direction in which the data signal lines are arranged. In FIG. 4, the pixel region S is located in the direction in which the output voltages V _1m , V _1n , and SP are output. Than the first voltage generation block 41, and the point distant from the pixel area S of the liquid crystal display device, among the data bus 6-bit digital image data D _A (N bits), the upper 3 bits (N
A (1 bit) data bus is arranged for each of R, G, and B colors. In FIG. 4, each data bus is connected to R
Shown in 1, G1, B1, it is shown in BUS _H collectively these. These bus lines are made of metal lines such as aluminum formed on a glass substrate.

[0074] In the pixel region side of the S BUS _H liquid crystal display device, the first voltage generation block 41 consisting of latch circuits 411 and the voltage level selection circuit 412 are formed.
Latch circuit 411, a first latch circuit LTC ₁₁ second
It consists of the latch circuit LTC ₁₂ Prefecture. Each latch circuit LTC
₁₁ and LTC ₁₂ each have three latch elements Le1
To Le3, and each latch element latches and holds 1-bit data. Each of such latch elements has a configuration in which two clocked inverters composed of CMOS TFTs are cascaded, and one CMOS TFT inverter is connected in a feedback manner between the input and output of the clocked inverter at the subsequent stage. The SP controls the clocked inverter at the input / output stage and the clocked inverter at the subsequent stage.
The inverted clock of the SP controls the inverter. Hereinafter, each latch element has the same configuration. Note that three latching elements in the first latch circuit LTC ₁₁ Le1~Le3
Are sequentially arranged in the arrangement direction of the pixel region S so that the circuit arrangement width can be reduced. Figure 1 th first latch circuit LTC ₁₁ of the first voltage generation block 41 of 4 is held 3 bits of image data of the data bus R1 is inputted, likewise, the second first 3-bit data of the first latch circuit LTC ₁₁ of the voltage generating block 41 G1, 3
Th to the first latch circuit LTC ₁₁ of the first voltage generation block 41 3-bit data B1, respectively, are simultaneously latched. Three latching element in the first latch circuit LTC _11, as can narrow the circuit arrangement width are sequentially arranged in the arrangement direction of the pixel area S.

[0075] Note that the further outside the pixel region S of the liquid crystal display device of the BUS _H, the shift register 44 is provided. Shift register 44, the first latch circuit LTC ₁₁ each of three voltage generation block 41 successive sampling pulses at the timing of the shift clock CLK S
P is sent out and the latch circuit LTC ₁₁ (Le1 to Le3)
Has captures data of the upper three bits (N1 bits) on BUS _H by the pulse SP. Sampling pulse SP is because it is supplied to the first latch circuit LCT ₁₁ three of three voltage generation block 41, the upper three bits of the image data for three pixels in the horizontal pixel direction (3 pixels in RGB) , Are simultaneously latched by one sampling pulse SP. Although the shift register 44 is shown in FIG. 4 as outputting the sampling pulse SP only to the three voltage generating units, actually, the shift register 44 inputs the shift data at the beginning of the horizontal scanning period. The shift data is sequentially shifted by a shift clock CLK, and a sampling pulse SP is sequentially generated in accordance with the shift to sequentially sample a plurality of voltage generation units arranged in a horizontal pixel direction in a horizontal scanning period. supplying pulses SP, the image data for one line to be displayed in the pixel region S in this period, operates to capture the latch circuit LCT _11.

[0076] Each latch element of the latch circuit LTC ₁₁ Le1
~Le3 is the upper three bits of data captured and transmitted to the latch element of the latch circuit LTC ₁₂ Le1~Le3. Latch circuit LTC _12, each latch element Le1~Le
3 is output to a second voltage level selection circuit (corresponding to a first voltage generator) 412 at the next stage at the timing of the latch pulse LP. Each latching element of the latch circuit LTC ₁₂ Le1~Le3, the latch pulse LP, each latch element of the latch circuit LTC ₁₂ of the plurality of voltage generation block 41 disposed side by side in the horizontal pixel direction Le1~Le
3 are commonly supplied. The latch pulse LP serves as a common clock for controlling the clocked inverter of each latch element. Therefore, within one horizontal scanning period, N1 bits of the image data for one line sequentially read the pixel regions with each latch circuit LCT ₁₁ of the plurality of voltage generation block 41, at the same time collectively, the latch circuit LTC ₁₂ Are latched in the latch elements Le1 to Le3. Therefore, each of the voltage level selection circuits 412 included in each of the plurality of voltage generation blocks 41 simultaneously outputs the voltage in the next horizontal scanning period.
Voltage selection is performed from among a plurality of reference voltages based on the image data input to each. Note that the second latch circuit L
The three latch elements in the TC ₁₂ are sequentially arranged in the arrangement direction of the pixel region S so that the circuit arrangement width can be reduced.

Next, the voltage level selection circuit 412 comprises eight decoder elements (AND gates a1 to a8) and eight pairs of switches s11.s12, s21.s22, s31.s
32, s41 / s42, s51 / s52, s61 / s6
2, s71 and s72, and s81 and s82. Here, the AND gate and the switch pair constitute the first to eighth selectors of the present invention. For example, the AND gate a1 and the switches s11 and s12 constitute a first selector.

Further, the voltage level selection circuit 412 provides nine levels of voltages V _{11 to} V ₁₉ (V ₁₁ > V ₁₂ >) as described below.
...> V ₁₉ ). The setting of the voltage value of this voltage level is performed as described with respect to the second embodiment.
The change width of the transmittance is set so that the change ratio of the transmittance of the voltage-transmittance characteristic of the pixel is constant, and the voltage obtained from the voltage-transmittance characteristic curve corresponding to the set transmittance is , And nine reference voltages. That is, the transmittance of the pixel obtained by these nine voltage levels has the same change ratio.

One of the two switches s1j of the j-th (j = 1, 2,..., 8) selector, which is located far from the display area of the liquid crystal display device (voltage input) The terminal (voltage terminal) is connected to the j-th reference voltage supply line (V _1j ), and the other terminal (voltage output terminal) is connected to one output line of the voltage V1m of the voltage level selection circuit 412. The voltage input terminal of the switch arranged on the side closer to the pixel region S of the liquid crystal display device is connected to the _{(j + 1) th} reference voltage supply line (V _{1 (j + 1)} ), and the voltage output terminal is connected to the voltage It is connected to the other output line of the voltage V1n of the level selection circuit.

The decoder element of the j-th selector is configured to send an ON operation signal to two switches of the selector when the value of the upper N1 bits is j-1. That is, each of the AND gates a1 to a8 has three input terminals in which the combination of the input phases is different from each other among the gates. One pair is turned on. That is, in the configuration of FIG. 4, when the value of the upper 3 bits is the smallest (that is, when the value is (000)), only the switches s81 and s82 are turned on and V ₁₈
And V ₁₉ are output to a voltage dividing circuit (corresponding to a second voltage generating unit) 422 (see FIG. 5) of the second voltage generating block 42,
Each time the value of the sequentially higher three bits increases, V ₁₇ and V _18, V ₁₆ and V _17, ···, as in the V ₁₁ and V _12, 2 two voltages V _{1 m} which the voltage level adjacent, V _1n (M = 1, 2,
.., 8, n = m + 1) in the second voltage generation block 4
2 to the voltage dividing circuit 422.

As described above with reference to FIG. 4, in each voltage generation block, not only the circuit elements but also the upper 3 bits of the 6-bit image data are selected for the voltage level within the circuit arrangement width. Wiring to transmit to the circuit 412;
The supply lines of the sampling pulse and the latch pulse and the output lines of the two voltages selected by the voltage level selection circuit 412 are arranged in the circuit arrangement direction (pixel region direction). Accordingly, the circuit has a small number of wirings arranged in one direction, and the latch circuit and the voltage level selection circuit are also divided and sequentially arranged in the pixel region direction, so that the arrangement width is narrowed. Therefore, the width of each voltage generation block in the horizontal pixel direction can be reduced.

FIG. 5 is a diagram showing a second voltage generation block (corresponding to a second voltage generation unit) 42 of each voltage generation unit 4 constituting the drive circuit 308 shown in FIG. The generation block 42 and the first block described in FIG.
Between the voltage generation block 43, among the 6-bit data bus of the digital image data D _A, the data bus of the lower 3 bits (N2 bits) are formed R, G, B for each color, respectively. In Figure 5, each data bus indicated by R2, G2, B2, is shown in BUS _L collectively these. The second voltage generation block 42 includes a latch circuit 421 and a voltage dividing circuit 422. Latch circuit 42
1 includes a first latch circuit LTC ₂₁ second latch circuit L
Consisting of TC ₂₂ Metropolitan. The latch circuit LTC ₁₁ and LTC ₁₂
Is composed of three latch elements Le1 to Le3, respectively.

Each latch element latches and holds 1-bit data. Each of such latch elements has the same configuration as each of the latch elements Le1 to Le3 of the latch circuit 411 in the first voltage generation block 41. Further, the control clock of the clocked inverter is also controlled by the latch circuit L
TC ₁₁ and LTC ₁₂ are the same, and the latch circuit L
TC ₁₁ is controlled by the sampling pulse SP, the latch circuit LTC ₁₂ is controlled by a latch pulse LP.

As described above, each first latch circuit LTC ₂₁ of the voltage generation block 41 for each of R, G, B colors
Is supplied with the sampling pulse SP from the shift register 44 described with reference to FIG. Latch circuit LTC _21, the lower 3 bits of the digital image data on the data bus 431 by the pulse SP (N2 bits)
Of the data. Each latching element Le1~Le3 latch circuit LTC ₂₁ is a lower three bits of the data captured, the latching elements of the latch circuit LTC ₂₂ Le1~
Send it to Le3. The latch circuit LTC ₂₂ the data of each latch element Le1~Le3 at the timing of the latch pulse LP2, and outputs to the next stage of the voltage dividing circuit 422.

The first second voltage generation block 4 in FIG.
The first latch circuit LTC ₂₁ 2, data 3 bits of image data bus R2 is held is inputted, likewise, the first latch circuit LTC ₂₁ of the second second voltage generation block 42 , The first latch circuit LTC ₂₁ of the third second voltage generation block 42,
Are latched simultaneously at the same time. Three latching element in the first latch circuit LTC _11, as can narrow the circuit arrangement width are sequentially arranged in the arrangement direction of the pixel area S.

The shift register 44 outputs not only the first voltage generation block 41 but also each of the first latch circuits L of the three second voltage generation blocks 42 arranged continuously.
The sampling pulse SP is transmitted to the TC ₂₁ at the timing of the shift clock CLK. The wiring of the pulse SP is wired within the circuit arrangement width of each voltage generation unit.
The latch circuit LTC ₂₁ (Le1~Le3), the lower 3 bits of the BUS _L by the pulse SP (N2 bits)
Of the data. Sampling pulse SP
Since supplied to the first latch circuit LCT ₂₁ three of the three voltage generation block 42, the lower 3 bits of the image data for three pixels in the horizontal pixel direction (3 pixels in RGB), 1 single It is latched simultaneously by the sampling pulse SP. Note that the shift register 44 in FIG.
Although it is illustrated that the sampling pulse SP is output only to the three voltage generation units, actually, shift data is input at the beginning of the horizontal scanning period, and the shift data is sequentially output by the shift clock CLK. The sampling pulse SP is sequentially shifted according to the shift.
Is generated, and a sampling pulse SP is sequentially supplied to a plurality of voltage generation units arranged in the horizontal pixel direction during a horizontal scanning period, and one line of image data to be displayed in the pixel region S during this period. The lower bits of
The latch circuit LCT ₂₁ operates to take in the data. Accordingly, the latch circuit LTC ₁₁ and LTC ₂₁ of the first voltage generation block 41 and the second voltage generation block 42 latches operate synchronously with the same sampling pulse SP.

[0087] Each latch element of the latch circuit LTC ₂₁ Le1
~Le3 is the upper three bits of data captured and transmitted to the latch element of the latch circuit LTC ₂₂ Le1~Le3. The latch circuit LTC _22, each latch element Le1~Le
3 is output to the next-stage voltage dividing circuit 422 at the timing of the latch pulse LP. Latch circuit LT
Each latching element Le1~Le3 of C _22, the latch pulse L
P not only latch circuit of the first voltage generating block 41, the latching elements Le latch circuit LTC ₂₂ of the plurality of voltage generation block 42 disposed side by side in the horizontal pixel direction
1 to Le3 are also commonly supplied. Latch pulse LP
Is a common clock for controlling the clocked inverter of each latch element. Therefore, within one horizontal scanning period, N of the image data for one line of the pixel region sequentially taken into each latch circuit LCT ₂₁ of the plurality of voltage generation blocks 41 is obtained.
2 bits are simultaneously collectively beginning of the next horizontal scanning period, the latch element of the latch circuit LTC ₂₂ Le1~Le3
It is taken in. Therefore, the plurality of voltage generation blocks 42
Each of the voltage dividing circuits 412 included in each of the... Simultaneously selects a divided voltage based on the image data input to them during the next horizontal scanning period. Note that three latching elements in the second latch circuit LTC _22, as can narrow the circuit arrangement width are sequentially arranged in the arrangement direction of the pixel area S.

The voltage dividing circuit 422 has eight decoder elements (AND gates b1 to b8) having three input terminals, outputs of these AND gates b1 to b8 as one input, and a reset pulse RS described later as the other input. (OR gates c1 to c8) and a switch t1 that is turned on / off in accordance with the outputs of these two input gates c1 to c8.
To t8 and a series connection circuit of eight thin film resistors r1 to r8. Here, each of the resistors, each switch, each two-input gate, and each AND gate are first to first.
This constitutes an eighth selector. For example, a resistor r1
Switch t1, two-input gate c1, and AND gate b
1 constitutes a first selection unit.

The voltage dividing circuit 422 has an input terminal for the reset pulse RS. AND gates b1 to b8
Has three input terminals having different combinations of input signal phases, and one of them outputs "1" according to the value of the lower three bits (N2 bits). In other words, the decoder element of the k-th (k = 1, 2,..., 8) selector is connected to the other terminal of the reset element of the selector when the value of the lower N2 bits is k-1. An ON operation signal is sent to the switch of the selection unit.

The two-input gate c1 is an OR gate.
The output of the ND gate b1 is input non-inverted, and the reset pulse RS is input non-inverted. On the other hand, two-input gate c
2 to c8 are AND gates, and AND gates b2 to b
8 is input non-inverted, and the reset pulse RS is input inverted. When the reset pulse RS is "0", the two input gates c1 to c8 are connected to the AND gates b1 to b8.
The output from b8 is transmitted to switches s1 to s8. That is, "1" is output from any of the AND gates b1 to b8, and when the reset pulse RS is "0", the outputs of the two-input gates b1 to b8 are used as the switches s1 to s8.
And one switch supplied with “1” is turned on. On the other hand, when the reset pulse RS is “1”, 2
The output of the input gate c1 becomes "1", and the outputs of the other two input gates c2 to c8 are fixed to "0". Therefore, the switch s1 is forcibly turned on, and the voltage V1n selected and supplied by the first voltage generation block 41 is output to the output line as it is.

The reset signal line for supplying the reset pulse RS is arranged over the plurality of second voltage generation blocks 42 in the horizontal pixel direction. When the reset pulse RS is “1”, each reset signal line The unit, that is, the output voltage from each second voltage generation block 42 is one of the two reference voltages selected by the corresponding first voltage generation block 41 (in FIGS. 4 and 5,
The high side) of the potential, is forcibly output is supplied to the data signal line L _D of the pixel area S.

The period during which the reset pulse RS is "1" is the first partial period of each horizontal scanning period. Considering instability period of the voltage selection operation in the latch circuit LCT ₁₂ and LCT _22, so that the output voltage side of the forced high potential during this period. Applying a high-potential side voltage to the data signal line and precharging with a higher voltage is more effective than applying a low-potential side voltage, and a data signal with an output voltage corresponding to image data from a subsequent voltage dividing circuit. This is because the charge of the line can be charged early. If the reset operation is unnecessary due to the characteristics of the liquid crystal panel, the signal line of the reset pulse RS and the two input gates c1 to c8 are unnecessary.

One terminal of each of the switches t1 to t8 is connected to an output line (which is directly connected to a data signal line), and the other terminal is connected to a tap of a series connection circuit (parallel to the data signal line) of thin film resistors r1 to r8. Have been. These resistors r
The two voltages V1m and V1n from the first voltage generation block 41 described above are applied to both ends of the direct connection circuits 1 to r8, and are divided into eight. The resistance values of the resistors r1 to r8 are set to be equal to each other.

The voltage dividing circuit 422 turns on one of the switches t1 to t8 in accordance with the value of the lower three bits of the image data, and connects the thin film resistors r1 to r8 between the two voltages V1m and V1n.
One of the divided voltages output from a predetermined terminal of the series connection circuit is selected by switches s1 to s8, and this is output to an output line, and output voltages V _drvR , V _drvG , V
It generates _DRVB, and outputs it to the data signal line L _D of the pixel area S shown in FIG. Note that the voltage generation unit 4
FIG. 6 shows an example of the characteristics of the output voltage (V _drv ) with respect to the input of 6-bit digital image data. As shown in FIG. 6, the voltage generation unit 4 can generate a voltage having characteristics according to the voltage-transmittance characteristics of the pixel.

The latch circuit shown in FIGS. 4 and 5
The AND gate, the OR gate, and the switch are configured by TFTs formed on the same glass substrate in the same process as the TFTs arranged in each pixel of the pixel region S.

As described above with reference to FIG. 5, in each voltage generation block, not only the circuit elements but also the lower 3 bits of the 6-bit image data are included in the voltage dividing circuit. 422, a wiring for supplying a sampling pulse or a latch pulse, and a voltage dividing circuit 422.
And the output line of the voltage selected in (1) are arranged in the circuit arrangement direction (pixel area direction). Accordingly, the circuit has a small number of wirings arranged in one direction, and the latch circuit and the voltage level selection circuit are also divided and sequentially arranged in the pixel region direction, so that the arrangement width is narrowed. Therefore, the width of each voltage generation block in the horizontal pixel direction can be reduced. Therefore, the pixel arrangement pitch of the pixel region S (or the arrangement pitch of the data signal lines) and the voltage generation unit of the drive circuit are made narrower together, and a high-definition liquid crystal panel with a built-in driver can be realized.

In the above embodiment, it is preferable that the N1 bit and the N2 bit have the same bit number or that the N2 bit number is larger than the N1 bit number. this is,
Since the first voltage generating means has a configuration for selecting two voltages, the second voltage generating means has a configuration for selecting one voltage, the number of data bits input to the first voltage generating means is small. This is because the circuit size increases as the number increases. For example, when the digital image data is 7 bits, the number of N1 bits is 3 and the number of N2 bits is 4 (or the number of N1 bits is 4 and the number of N2 bits is 3). For example, when the digital image data is 6 bits, it is preferable that both the number of N1 bits and the number of N2 bits be 3.

The first voltage generation block 41 and the second
As shown in FIGS. 4 and 5, the first latch circuits LCT ₁₁ and LCT ₂₁ of the voltage generation block 42 and the data buses BUS _H and BUS _L arranged adjacent thereto Instead of providing a latch circuit on the pixel region side of the arrangement, one latch element may be provided adjacent to one data bus, and the data bus and the latch element may be arranged alternately.

[0099] Further, in this embodiment, in one-to-one correspondence with the arrangement pitch of the data signal lines and the pixel, but the arrangement pitch of the voltage generating unit is set to be substantially equal, opposite side of the data signal line L _D Also place a voltage generation unit,
By alternately arranging the voltage generation units on the opposite side for each predetermined number of data signal lines (for example, one, three, six,...), The arrangement pitch of the voltage generation units becomes almost equal. The width can be doubled to provide a margin. For example, odd-numbered voltage supplies drive circuit to the data signal line in the figure (in the figure, the voltage generating unit for generating a voltage generating unit and a V _DRVB to generate a V _DRVR), an end portion side that is shown in the data signal line And a drive circuit (a voltage generation unit for generating V _drvG in the figure) for supplying a voltage to the even-numbered data signal lines is disposed at an end opposite to the data signal line (not shown). Since the generation units have a relationship of arranging one voltage generation unit for two data signal lines, there is room for arrangement. Therefore, the arrangement pitch of the data signal lines and the pixels can be narrowed, so that the pixels of the liquid crystal panel can be further refined.

[Fourth Embodiment] A process of forming a drive circuit (drive circuit 308), an active matrix portion 307, and the like on a glass substrate 302 shown in FIG. This will be described with reference to FIGS.

Process 1: As shown in FIG. 7, a buffer layer 701 is formed on an active matrix substrate 700, and an amorphous silicon layer 702 is formed on the buffer layer 701.

Process 2: Laser annealing is performed on the entire surface of the amorphous silicon layer 702 in FIG. 8 to polycrystallize the amorphous silicon layer, and a polycrystalline silicon layer 703 is formed as shown in FIG.

Process 3: The polycrystalline silicon layer 703 is patterned to form an island region 70 as shown in FIG.
4,705,706 are formed. Island area 70
Reference numeral 4705 denotes a layer in which an active region (source, drain) of a MOS transistor used as each switch shown in the embodiment is formed. Further, the island region 70
Reference numeral 6 denotes a layer serving as one pole of a charge storage capacitor provided as necessary for each pixel or the like.

Process 4: As shown in FIG. 10, a mask layer 707 is formed, and phosphorus (P) ions are implanted only into the island region 706 which becomes one pole of the thin film capacitance of the capacitance element, and the island region 706 is formed to have a low resistance. Become

Process 5: As shown in FIG. 12, a gate insulating film 708 is formed, and a gate insulating film 708 is formed on the gate insulating film 708.
The aN layers 710, 711, 712 are formed. TaN layer 7
10, 711 are MOSs used as various switches
A TaN layer 712 which is a layer to be a gate of the transistor;
Is a layer to be the other pole of the thin film capacitor. After forming these TaN layers, a max layer 713 is formed, and a gate TaN layer 71 is formed.
0 is used as a mask, phosphorus (P) ions are implanted in a self-aligned manner to form n-type source layer 715 and drain layer 7.
16 are formed.

Process 6: As shown in FIG. 12, mask layers 721 and 722 are formed, and using the gate TaN layer 711 as a mask, boron (B) ions are implanted in a self-aligned manner to form a p-type source layer 721 and Drain layer 72
Form 2

Process 7: As shown in FIG. 13, after forming an interlayer insulating film 725 and forming a contact hole in the interlayer insulating film, an electrode layer 726 made of ITO or Al is formed.
727, 728, 729 are formed. Although not shown in FIG. 13, electrodes are also connected to the TaN layers 710, 711, 712 and the polycrystalline silicon layer 706 via contact holes. Thereby, an n-channel TFT, a p-channel TFT, and the like used as each switch of the drive circuit are manufactured.

By using the processes 1 to 7 described above, the manufacture of the liquid crystal display device including the drive circuit is facilitated, and the cost can be reduced. Also,
Polysilicon has much higher carrier mobility than amorphous silicon, so high-speed operation is possible.
This is advantageous in terms of improving the performance of the circuit. As a method of forming the resistance portion, any one of a molding process of a polysilicon thin film layer having three kinds of sheet resistance values of the island region 706 (N +), the n-type source layer (P +) 5, and the drain layer (P) 716 is used. And can be formed in the same step. As the resistance value, since the impurity concentration of the layer of the island region 706 is the lowest among the three, the sheet resistance value is the highest, the length of the resistor can be the shortest, and the circuit area of the voltage dividing circuit can be reduced. Can be reduced.

It is to be noted that a process using amorphous silicon can be used instead of the above-described manufacturing process.
Further, in the above embodiment, the example in which the driving circuit and the pixel region are formed by the TFT and the thin film resistance element formed on the insulating substrate has been described. However, the present invention is not limited thereto. It may be formed. In that case, the pixel electrode formed in the pixel is a reflective electrode of a metal layer, a MOS transistor for supplying a data signal to the pixel electrode on the surface of the silicon substrate below the reflective electrode, and a charge of the supplied data signal is held. A charge storage capacitor is formed. A drive circuit including a MOS transistor is formed on the surface of the silicon substrate around the pixel region. The resistance element is formed as a polysilicon resistance on a silicon substrate. This panel is realized as a reflection-type active matrix panel in which a silicon substrate and a glass substrate are attached to each other and a liquid crystal is sandwiched between the substrates. Even in such a panel, by adopting the present invention, a drive circuit can be configured in accordance with the pixel arrangement pitch (data signal line arrangement) pitch. Further, the present invention can be used not only as an active matrix type liquid crystal display device but also as a driving circuit for a liquid crystal panel of a two-terminal element type such as a simple matrix type or MIM.

In the above embodiment, the description has been made on the assumption that the liquid crystal display device performs color display based on the image data of the three primary colors of RGB. However, the present invention is not limited to this. Needless to say, only a single-color image data may be input as a drive circuit for a liquid crystal display device that modulates monochromatic (only R, only G, and only B) light like the light valve. Also,
When white light is input and the light is modulated for monochrome display, luminance data may be input as image data.

Further, in the above embodiment, the drive circuit in the configuration in which the liquid crystal of the pixel is not driven by AC (only the voltage having the positive polarity with respect to the common electrode potential is applied to the pixel electrode) has been described. This is to simplify the description. However, the liquid crystal is generally driven by an alternating current. In the case of driving the liquid crystal of the pixel by AC, the driving circuit must be configured to output a voltage of a negative polarity with respect to the common electrode potential. For this purpose, when outputting a negative voltage, the reference voltage supplied to the first voltage generating means is switched to a negative voltage (the sign of the voltage is inverted with respect to the reference potential), and the voltage is generated from this. It is necessary that the applied voltage be a negative voltage. Further, in the second voltage generating means, the negative voltage may be generated with higher precision based on the negative voltage. Therefore, the liquid crystal display device is driven by line inversion (a driving method in which the polarity of the voltage applied to the liquid crystal of the pixel is inverted for each pixel row and the applied voltage polarity is further inverted for each pixel in each vertical scanning period) or the pixel inversion. Driving (a method of inverting the voltage polarity applied to the liquid crystal of the pixel for each pixel and further inverting the applied voltage polarity for each pixel in each vertical scanning period) and source line inversion driving (the liquid crystal of the pixel for each pixel column) , The polarity of the voltage applied to each pixel is inverted, and the polarity of the applied voltage is further inverted for each pixel in each vertical scanning period). It is necessary to switch the reference voltage supplied to the means.

Next, an embodiment of a liquid crystal display device manufactured by using the above-described active matrix substrate and driven by the above-described drive circuit, and an electronic apparatus having the liquid crystal display device, such as a portable computer or a liquid crystal projector, will be described. Will be described.

Fifth Embodiment As shown in FIG. 14, a liquid crystal display device 750 comprises a backlight 751, a polarizing plate 752, a TFT substrate 753, a liquid crystal 754, and a counter substrate (a color filter is formed as necessary). 755)
And a polarizing plate 756 in this order.
In this embodiment, as described above, the drive circuit 778 is formed on the TFT substrate 753.

Sixth Embodiment As shown in FIG. 15, a portable computer 760 has a main body 762 having a keyboard 761 and a liquid crystal display screen 763 on which a liquid crystal display device of the present invention is mounted. doing.

[Seventh Embodiment] As exemplified in FIG. 16, a liquid crystal projector 770 is a projection type projector using the liquid crystal display device of the present invention as a liquid crystal light valve. Is used. In the projector 770 in FIG. 16, the projection light emitted from the lamp unit 771 of the white light source is divided into R, G, and B by a plurality of mirrors 773 and two dichroic mirrors 774 inside the light guide 772.
It is divided into primary colors and guided to three liquid crystal panels 775, 776, 777 that display images of each color. The light modulated by each of the liquid crystal panels 775, 776, and 777 is applied to a dichroic prism 778.
It is incident from the direction. In the dichroic prism 778, the R (red) and B (blue) lights are bent by 90 °, and the G (green) light travels straight. Is projected.

Other electronic devices to which the present invention can be applied include an engineering workstation, a beger or a mobile phone, a word processor, a television, a video camera of a viewfinder type or a monitor direct view type, an electronic organizer, an electronic desk calculator, and a car navigation system. Device, P
Various devices including an OS terminal and a touch panel can be given.

[0117]

According to the driving circuit of the present invention, the first voltage generating means for inputting a predetermined number of bits of image data and the second voltage generating means for inputting the remaining predetermined number of bits of image data Therefore, a circuit of a predetermined number of bits may be secured as a circuit arrangement pitch required for the first voltage generating means. Further, it is only necessary to secure a circuit of the remaining predetermined number of bits as a circuit arrangement pitch required for the second voltage generation means. A layout can be made narrower in accordance with the arrangement pitch of the pixels of the device. Further, thereby, the area occupied by the drive circuit can be reduced, and a high-definition liquid crystal panel in which the pixel arrangement pitch is narrowed in accordance with this can be realized. Can be promoted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a drive circuit of the present invention.

FIG. 2 is a diagram showing a second embodiment of the drive circuit of the present invention.

FIG. 3 is an explanatory diagram of a third embodiment of the present invention, and is a diagram schematically illustrating a liquid crystal display device.

FIG. 4 is an explanatory view of a third embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing more specifically the first voltage generation means of the drive circuit of FIG.

FIG. 5 is an explanatory view of a third embodiment of the present invention, and FIG.
FIG. 3 is a diagram more specifically showing a second voltage generation unit of the drive circuit of FIG.

FIG. 6 is a diagram showing input / output characteristics of the first voltage generating means of FIG. 4;

FIG. 7 is a diagram showing a first process in manufacturing the drive circuit of the present invention.

FIG. 8 is a diagram showing a second process in manufacturing the drive circuit of the present invention.

FIG. 9 is a diagram showing a third process in manufacturing the drive circuit of the present invention.

FIG. 10 is a diagram showing a fourth process in manufacturing the drive circuit of the present invention.

FIG. 11 is a diagram showing a fifth process in manufacturing the drive circuit of the present invention.

FIG. 12 is a diagram showing a sixth process in manufacturing the drive circuit of the present invention.

FIG. 13 is a diagram showing a seventh process in manufacturing the drive circuit of the present invention.

FIG. 14 is a diagram illustrating a configuration of a liquid crystal display device driven by a driving circuit of the present invention.

FIG. 15 is a diagram showing a portable computer having a liquid crystal display device driven by the driving circuit of the present invention.

FIG. 16 is a diagram showing a projector having a liquid crystal display device driven by the driving circuit of the present invention.

FIG. 17 is a diagram showing a conventional liquid crystal display device equipped with a drive circuit having no γ correction function.

FIG. 18 is a diagram illustrating a conventional liquid crystal display device equipped with a drive circuit having a γ correction function.

FIG. 19 is a diagram illustrating a state in which a conventional drive circuit is connected to a liquid crystal display device via a connection terminal member.

[Explanation of symbols]

10, 20, 31A Glass substrate 11, 21, Voltage generation unit 121, 221, 431 Upper N1 bit data bus 122, 222, 432 Lower N2 bit data bus 131, 231, 411, 421 Latch means 132, 142, 412 Voltage generator 412 voltage level selecting circuit 422 dividing circuit 44 shift register W pixel area S V ₁₁ ~V ₁₉ reference voltage of the pixel array pitch S liquid crystal display device of a liquid crystal display device

Claims (16)

[Claims] 1. A liquid crystal for supplying a driving voltage generated by correcting a voltage-transmittance characteristic of a pixel as much as possible to a plurality of pixels arranged in a matrix via a plurality of data signal lines. In the driving circuit of the display device, the driving circuit includes a plurality of voltage generation units formed in a row outside of a pixel region on the substrate of the liquid crystal display device in correspondence with each of the data signal lines, Each voltage generation unit includes: a first voltage generation unit configured to generate a voltage obtained by correcting the voltage-transmittance characteristic with coarse accuracy based on a first predetermined number of bit data of the digital image data; Based on a second predetermined number of bit data, the voltage-transmittance characteristic is corrected from the voltage generated by the first voltage generation unit with an accuracy smaller than the coarse accuracy. Second to generate the drive voltage
Wherein the first voltage generating means is arranged at a position farther from the pixel region than the second voltage generating means, and the first voltage generating means is provided for the first voltage generating means. A first holding unit for holding a predetermined number of bit data of 1 is arranged at a position farther from the pixel area than the first voltage generating unit, and the second holding unit is provided for the second voltage generating unit. A driving circuit for a liquid crystal display device, wherein a second holding means for holding a predetermined number of bit data is arranged between the first voltage generating means and the second voltage generating means. 2. The method according to claim 1, wherein the first voltage generator selects two voltages from a plurality of voltages different from each other based on the first predetermined number of bit data. 2 based on a predetermined number of bit data
2. The driving circuit according to claim 1, wherein a voltage located between the two voltages is selected. 3. The first voltage generating means includes: the first holding means for holding the first predetermined number of bit data of the digital image data; and the first output means output from the first holding means. A voltage level selection circuit for selecting and outputting two adjacent voltages from among a plurality of voltages in accordance with the bit data, wherein the second voltage generation means is configured to output the second voltage of the digital image data The second memory for holding a predetermined number of bit data;
Holding means, and a voltage dividing circuit for dividing the voltage between the two voltages selected by the voltage level selecting circuit according to the bit data output from the second holding means to generate the drive voltage. The driving circuit for a liquid crystal display device according to claim 1, further comprising: 4. A driving circuit for a liquid crystal display device for generating a voltage to be supplied to a plurality of pixels arranged in a matrix through a plurality of data signal lines, wherein the driving circuit is provided on a substrate of the liquid crystal display device. A plurality of voltage generation units formed side by side in correspondence with each of the data signal lines, each of the voltage generation units being a first predetermined number of bit data of digital image data. A first voltage generating means for selecting two voltages from a plurality of voltages different from each other based on the second predetermined number of bits of the digital image data; Dividing one voltage and selecting one divided voltage
Wherein the first voltage generating means is arranged at a position farther from the pixel region than the second voltage generating means, and the first voltage generating means is provided for the first voltage generating means. A first holding unit for holding a predetermined number of bit data of 1 is arranged at a position farther from the pixel area than the first voltage generating unit, and the second holding unit is provided for the second voltage generating unit. A driving circuit for a liquid crystal display device, wherein a second holding means for holding a predetermined number of bit data is arranged between the first voltage generating means and the second voltage generating means. 5. A plurality of voltage supply lines to which a plurality of voltages different from each other are supplied are arranged parallel to each other with an interval therebetween, and said first holding means holding said first predetermined number of bits of data. And a signal line connecting the voltage level selection circuit and
And a first output line from which the two voltages are output from the voltage level selection circuit is arranged along a circuit arrangement direction of each of the voltage generation units, and the voltage level selection circuit is configured to output the plurality of voltages. A decoder element that decodes the first predetermined number of bit data output from the first holding unit between adjacent voltage supply lines of the supply lines, and a decoder element that is adjacent to the two by the output of the decoder element.
The two voltages supplied to the two voltage supply lines to the first
5. A liquid crystal display device according to claim 4, wherein a selector having a switch for controlling output is provided on the output line, and the first output line is commonly connected to each of the selectors. Drive circuit. 6. Each of the selectors is provided between two voltage supply lines adjacent to each other, and among the switches,
One terminal of a switch disposed far from the pixel region is connected to one of the two voltage supply lines, and the other terminal of the switch is connected to one of the first output lines, One terminal of a switch arranged near a pixel area is connected to the other of the two voltage supply lines, and the other terminal of the switch is connected to the other of the first output lines. 6. The driving circuit according to claim 5, wherein the element is configured to send an ON operation signal to the switch in one of the plurality of selection units. 7. A signal line connecting the second holding means for holding the data of the second predetermined number of bits and the voltage dividing circuit, and a second voltage output from the voltage dividing circuit.
Are arranged along the circuit arrangement direction of the voltage generating unit, and the voltage dividing circuit divides the two voltages output from the voltage level selecting circuit and connects a plurality of voltage output terminals. And a plurality of decoder elements for decoding the second predetermined number of bit data, and outputting a voltage extracted from a voltage output terminal of the resistor to the second output line by an output of the plurality of decoder elements. 5. The switch according to claim 4, further comprising a plurality of switches, wherein the resistor, the plurality of decoder elements, and the plurality of switches are arranged along a circuit arrangement direction of each of the voltage generation units. 6. Drive circuit for liquid crystal display. 8. A reset signal line disposed over the plurality of voltage generation units, and, when a reset signal is supplied from the reset signal line, one of the two voltages output from the voltage level selection circuit. 5. The driving circuit according to claim 4, further comprising control means for controlling a plurality of switches of the voltage dividing circuit so that a voltage is supplied to the data signal line. 9. A liquid crystal for supplying, via a plurality of data signal lines, a driving voltage generated by correcting voltage-transmittance characteristics of the pixels as much as possible to a plurality of pixels arranged in a matrix. In the driving circuit of the display device, the driving circuit includes a plurality of voltage generation units formed in a row outside of a pixel region on the substrate of the liquid crystal display device in correspondence with each of the data signal lines, Each voltage generation unit includes: a first voltage generation unit configured to generate a voltage obtained by correcting the voltage-transmittance characteristic with coarse accuracy based on a first predetermined number of bit data of the digital image data; Correcting the voltage-transmittance characteristic from the voltage generated by the first voltage generating means with an accuracy smaller than the coarse accuracy based on a second predetermined number of bits of data; And a second voltage generating means for generating the drive voltage, wherein the first voltage generating means is arranged at a position farther from the pixel area than the second voltage generating means, and The data bus for the predetermined number of bit data is
And a data bus of the second predetermined number of bit data is disposed at a position farther from the pixel area than the voltage generating means, and the data bus of the second predetermined number of bit data is connected to the first voltage generating means and the second A driving circuit for a liquid crystal display device, wherein the driving circuit is disposed between the plurality of voltage generation units and a voltage generation unit. 10. A driving circuit of a liquid crystal display device for generating a voltage to be supplied to a plurality of pixels arranged in a matrix through a plurality of data signal lines, wherein the driving circuit is provided on a substrate of the liquid crystal display device. A plurality of voltage generation units formed side by side in correspondence with each of the data signal lines, each of the voltage generation units being a first predetermined number of bit data of digital image data. A first voltage generating means for selecting two voltages from a plurality of voltages different from each other based on the second predetermined number of bits of the digital image data; Dividing one voltage and selecting one divided voltage
Voltage generating means, wherein the first voltage generating means comprises:
The data bus of the first predetermined number of bit data is located farther from the pixel area than the second voltage generating means, and is located farther from the pixel area than the first voltage generating means. And a data bus for the second predetermined number of bit data, the data bus being provided over the plurality of voltage generation units, and being provided between the first voltage generation means and the second voltage generation means. A driving circuit for a liquid crystal display device, wherein the driving circuit is arranged over a generation unit. 11. The data generating apparatus according to claim 11, wherein the plurality of voltage generating units are arranged at one end or both ends of the data signal line at a pitch substantially equal to the arrangement pitch of the data signal lines. A driving circuit for a liquid crystal display device according to claim 1. 12. The voltage generating unit according to claim 1, wherein:
A first voltage generating unit disposed on one end side of the data signal line and connected to one end of the data signal line; and a second end side of the second data signal line. 11. The driving circuit for a liquid crystal display device according to claim 1, further comprising: the second voltage generation unit disposed at a second position and connected to the other end of the data signal line. 13. The driving circuit according to claim 9, wherein the resistor is a thin film resistor formed on a glass substrate in a step of forming a thin film transistor of the pixel. 14. The liquid crystal display device is an active matrix type liquid crystal display device, wherein the resistor is formed in the same step as the formation of the source or drain of the transistor of the pixel or the transistor of the voltage generation unit. The driving circuit for a liquid crystal display device according to claim 9, wherein: 15. A liquid crystal display device driven by the driving circuit according to claim 1. Description: 16. An electronic apparatus comprising the liquid crystal display device according to claim 15.