JPH1127961A - Pulse power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse power supply, wherein when chargers are connected in parallel, variations in charging voltage is eliminated and the accuracy of pulse current supplied to a load is enhanced. SOLUTION: The control circuit of each charger is provided with a parallel synchronous control circuit which when an operation command is given, starts the operation of an inverter with delay of a separately set time. The delay time is obtained from clock counts counted by a counter CN relative to the operation command and a delay time setting on a preset circuit PS. After the delay time has passed, a frequency dividing circuit DIV starts the operation for generating an inverter operation frequency f, which is obtained as gate signals of the inverter in phases U and Y and in phases V and X from monostable multivibrators MM1 , MM2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse power supply for generating short pulses of high voltage and large current, and more particularly to a control device for initially charging an energy storage capacitor with a parallel-structured charger.

[0002]

2. Description of the Related Art As a pulse power supply for a pulse laser excitation, a pulse plasma generation, a pulse denitration apparatus, etc., there is a combination of a semiconductor switch and a saturable reactor or a saturable transformer serving as a magnetic switch. FIG. 5 shows a circuit example of a pulse power supply in which a semiconductor switch and a saturable reactor are combined.

[0003] In the figure, the first stage energy storage capacitor C ₀ is initially charged by the charger DCHV become high-voltage DC power source. Semiconductor switch SW indicated by GTO
Is the first stage switch. Saturable reactor SI
_0, the discharge pulse current I ₀ of the route indicated by an arrow from the capacitor C ₀ by turning the switch SW, become magnetic assist unit to reduce the switching loss of the switch SW in delay until its saturation.

The pulse transformer PT has a discharge pulse current I
₀ boosts the pulse voltage applied to the primary winding by charging the capacitor C _1. Saturable reactors SI ₁ is saturated when the charging of the capacitor C1 has reached a predetermined level, the magnetic pulse compression means for generating a discharge pulse current I ₁ from the capacitor C ₁ to capacitor C ₂ becomes low impedance .

[0005] Similarly, the saturable reactor SI ₂ will magnetic pulse compression means for generating a discharge pulse current I ₂ to peaking capacitor C _P at the charging capacitor C _2.

[0006] peaking capacitor C _P becomes a load of the pulse power source to constitute a laser oscillator with the laser head LH, is a high-pressure charged by the magnetic pulse compression pulse current, a discharge pulse current to the laser head LH in charge up to a certain voltage Supply.

The configuration of the pulse power supply is not limited to the configuration shown in FIG. 5, but includes various modifications such as a configuration using a saturable transformer instead of the pulse transformer PT and a configuration having a plurality of transformers.

[0008] Here, the charger DCHV are those with a period of the pulse current supply to the load is repeatedly charges the capacitor C _0, the charging accuracy determines the pulse current accuracy supplied to the load.

Further, to increase the capacity of the pulse power supply, generally increases the capacity of the energy storage capacitor C _0, performs the parallel operation by increasing the number of chargers.

FIG. 6 shows a case where two chargers are operated in parallel. The chargers 1 and 2 generate a pulse whose pulse width is fixed or modulated by the inverter INV, boost and insulate the pulse by the transformer T, and connect this output to a diode bridge, as shown in the circuit configuration on behalf of the charger 1. The current is rectified by the rectifier DB having the configuration, and the charging pulse current I ₁ to the capacitor C ₀ is supplied.
(I ₂ ). The control circuit CNT includes a capacitor C ₀
The inverter INV is operated by the charge command of
_When the charging voltage of ₀ reaches the set value, the inverter INV
To the standby state.

[0011]

In charging the capacitor C ₀ in a parallel configuration of a plurality of the charger [0005], each charger is controlled asynchronously with each other, individual control circuit CNT
Compares the voltage command value with the voltage detection value and controls the standby state when the voltage command value matches the voltage command value.

[0012] Therefore, the pulse current the charger occurs varies with different phases for each charging operation, variation occurs in the charge voltage of the capacitor C _0. This variation reduces the accuracy of the pulse current supplied to the load.

FIG. 7 shows waveforms when the output pulse currents of the two chargers have a phase difference. The pulse current I ₁ of the charger 1 of FIG. 6, the pulse current I ₂ of the charger 2 1
If there is a phase difference of 80 degrees, the combined current (I ₁ + I ₂ ) has the minimum energy in each cycle. On the other hand, when the pulse current I ₂ ′ of the charger 2 is in phase with I ₁ , the combined current (I ₁ + I ₂ ′) has the maximum energy in each cycle.

Due to these phase differences, the capacitor C ₀
Is charged to the set voltage, and the timing at which the inverter INV shifts to the standby state is different. As a result, the capacitor C ₀
The charging voltage varies.

An object of the present invention is to provide a pulse power supply which eliminates variations in charging voltage when the chargers are arranged in parallel and improves the accuracy of a pulse current supplied to a load.

[0016]

In order to solve the above-mentioned problems, the present invention eliminates the variation in the charging voltage of the capacitor by synchronizing the chargers operating in parallel, and has the following features. I do.

A plurality of chargers constituted by an inverter and a rectifier are started to operate when an operation command is given, a charging current generated individually from each of the chargers is synthesized to initially charge a capacitor, and a switch is operated. A pulse power supply that discharges the capacitor by control to generate a pulse current, and compresses the pulse current into a magnetic pulse and supplies the pulse current to a load.
The plurality of chargers are provided with a parallel synchronization control circuit that starts the operation of the inverter with a delay set individually when the operation command is given.

[0018]

FIG. 1 is a parallel synchronization control circuit diagram showing an embodiment of the present invention. This circuit is provided in each of the control circuits CNT of the chargers 1 and 2 in FIG.

The suppression circuit G ₁ receives a common operation command for the chargers 1 and 2 and suppresses the operation command with a charge completion signal. The D-type flip-flop FF ₁ sets the operation command from the inhibition circuit G _{1 with} a clock common to the chargers 1 and 2.

The counter CN has a flip-flop FF ₁
The counting of the clock is started by the data set described above, and the counting is started from the value preset by the preset circuit PS. D-type flip-flop FF ₂ is a carry signal from the counter CN to the clock input, a data set output of the flip-flop FF _1.

[0021] Therefore, the flip-flop FF _2, the counter C for the data set of the flip-flop FF ₁
Data is set with a delay of a clock time corresponding to the count value of N, and this delay time is determined by a preset value by the preset circuit PS.

Next, the AND gate G ₂ sets the flip-flop F on the condition that the data set of the flip-flop FF ₁ is set.
F ₂ is detected to be the dataset. Dividing circuit D
IV starts counting of the clock at the output of the AND gate G _2, to obtain a divided output of the duty ratio of 50% to match the inverter operation frequency f.

The AND gate G ₃ has a flip-flop F
Data sets F ₁ on condition to obtain an output of the frequency divider circuit DIV. The AND gate G ₄ obtains an inverted output of the frequency dividing circuit DIV through the logical inverter G ₅ on condition that the data set of the flip-flop FF ₁ is set.

The monostable multivibrators MM ₁ , MM
₂ is triggered by the outputs of the AND gates G ₃ and G ₄ , respectively, to obtain a pulse output having a constant width. This pulse output is used as gate signals of the U and Y phases and the V and X phases of the inverter INV in FIG.

With the above configuration, the operation signal of the inverter determined by the frequency dividing circuit DIV has a delay time set by the counter CN or the like with respect to the operation command and is generated at the timing specified by the clock. .

These relationships are as shown in the time chart of FIG. Flip-flop FF ₁ is a data set at the next clock time (time t ₁₎ the operation command is given, thereby the counter CN starts counting,
Flip-flop FF ₂ is delayed data set after a time T _D by the counting of the clock values that are set by preset circuit PS. At this timing (time t ₂ ), the frequency divider DIV
There dividing starts to operate, the signal INV (U, Y) to generate an output, the inverted signal INV (V a logic inverter G _5,
Give X), 1 to monostable multivibrator MM and MM ₂
A gate signal for inverter operation having a phase difference of 80 degrees is obtained. The pulse width of the multivibrators MM ₁ and MM ₂ is determined by the control rate of the inverter.

By the operation of the inverter, the capacitor C ₀
When the battery is charged to the desired voltage (time t ₃ ), the operation command is suppressed by the suppression circuit G ₁ and the flip-flop FF ₁ is reset. Inverter operation is stopped.

The above parallel synchronous control circuit as constituted is provided in the control circuit CNT of both the charger 1 of FIG. 6, the delay time T _D set in preset counter CN is in the charger 1 2 The values are made different from each other, and an inverter output is obtained at a synchronized timing.

[0029] This state is as shown in FIG. 3, with respect to the operation command, to start operation at the inverter INV is delayed time TD ₁ charger 1, the inverter INV of the charger 2 is delayed charger TD ₂ To start driving. As a result, the charging current outputs I ₁ and I 1 from both chargers 1 and 2 to the capacitor C ₀ .
₂ is a synchronized output that always has a constant phase difference.

Similarly, the synchronous operation by the n chargers is as shown in FIG. 4, in which the n chargers 1 to n have delay times T _{D1 to} T _Dn , respectively, in response to the operation command. To start operation and obtain synchronous operation. It is also a synchronous operation the current I ₁ ~I _n is to have the overlap period with each other.

[0031] Therefore, in charging of the capacitor C ₀ by a plurality of chargers, the output has always synchronized from each battery charger, can the energy of the synthesized pulse current .SIGMA.I _i by parallel operation always the same, the capacitor C ₀ Can be improved, and the pulse energy supplied to the load can be made constant.

[0032]

As described above, according to the present invention, a plurality of chargers operating in parallel are provided with a parallel synchronous control circuit for starting the operation of the inverter with a delay set individually for the operation command. With the provision, the energy of the combined pulse current can be made uniform at all times, and the variation in the charging voltage of the capacitor can be eliminated, and the accuracy of the pulse current supplied to the load can be improved.

Further, the parallel synchronous control circuit does not require connection between chargers for synchronous control, so that it is not necessary to change the circuit when changing the number of parallel operated chargers, and it is easy to unitize the charger configuration. become.

[Brief description of the drawings]

FIG. 1 shows a parallel synchronization control circuit of a pulse power supply according to an embodiment of the present invention.

FIG. 2 is a time chart of the embodiment.

FIG. 3 is a synchronous waveform of two chargers according to the embodiment.

FIG. 4 is a synchronous waveform of n chargers in the embodiment.

FIG. 5 is a circuit example of a pulse power supply.

FIG. 6 is an example of a parallel configuration of a charger.

FIG. 7 shows a charging operation waveform due to a difference in phase between two chargers.

[Explanation of symbols]

1,2 ... charger INV ... Inverter DB ... rectifier CNT ... control circuit C ₀ ... capacitor FF _1, FF ₂ ... flip-flop CN ... counter PS ... preset circuit DIV ... divider circuit MM _1, MM ₂ ... monostable multivibrator

Claims (1)

[Claims] An operation is started when a plurality of chargers constituted by an inverter and a rectifier are given an operation command, and a charging current generated individually from each charger is synthesized to initially charge a capacitor. In a pulse power supply that discharges the capacitor under control of a switch to generate a pulse current and compresses the pulse current into a magnetic pulse and supplies the pulse current to a load, the plurality of chargers are configured such that when the operation command is given, And a parallel synchronous control circuit for starting the operation of the inverter with a delay for each set time.