JPH1127701A - Image-pickup signal processing unit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image-pickup signal processing unit and its method, by which the circuit scale as a camera system is reduced at a low cost which space saving. SOLUTION: A time-base multiplex processing system 28 applies time-base multiplexing to 4 systems of serial digital red (R)/green (G)/blue (B) signals. A signal processing system 34 applies, to a time base multiplex signal from the time base multiplex processing system 28, video signal processing such as image enhancement(IE) processing which are contour emphasis processing (detail processing), process(PR) processings such as matrix processing, gamma processing and knee processing and encode(ENC) processing being compression coding processing. A multiple dividing processing system 39 divides the time base multiplex signal, that is subject to video signal processing by the video signal processing system 34, into four systems of video signals of an original time base.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus and method for performing signal processing on an image signal obtained by an image pickup apparatus.

[0002]

2. Description of the Related Art A television broadcasting company has a program production function equivalent to that of a studio program production facility for producing programs outside of a station, such as sports, and is capable of producing various programs regardless of environmental conditions. A OB van with a system configuration that can be used is used.

[0003] A relay vehicle has a plurality of camera head units (camera head units) used as relay cameras arranged at various locations.
A unit is mounted with a camera control unit (CCU) which is connected to a unit (CHU) by a triax cable which is a triaxial cable.

[0004] Conventionally, the CHU and the CCU are connected by one body, and a plurality of combinations thereof constitute a camera system.

[0005]

By the way, in the conventional camera system, as described above, one CHU and one CCU are used.
Since the connection is made on a one-to-one basis, a plurality of identical circuits exist, which is redundant and wasteful in terms of cost and space.

For this reason, in the conventional camera system, there is a limit in cost reduction and space saving, and there is a limit even if it is desired to increase the number of CHUs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an image pickup signal processing apparatus and method capable of reducing the circuit scale of a camera system and realizing cost reduction and space saving. .

[0008]

In order to solve the above-mentioned problems, an image signal processing apparatus according to the present invention multiplexes a plurality of video signals on a time axis by a multiplex processing means, and then executes a video signal processing by a video signal processing means. Processing is performed, and the video signal is separated into a plurality of video signals on the original time axis by separation processing means.

Further, the imaging signal processing method according to the present invention comprises:
In order to solve the above-mentioned problem, a plurality of video signals from a plurality of image pickup units are time-division multiplexed, then subjected to video signal processing, and further separated into a plurality of original video signals on a time axis.

[0010] For this reason, even a plurality of video signals from a plurality of image pickup means can function as one image pickup signal processing device, thereby eliminating waste in cost and space.

The video signal processing here includes image enhancer processing, processing processing, and encoding processing.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an image signal processing apparatus and method according to the present invention.

In this embodiment, as shown in FIG.
A camera head unit group 2 composed of two camera head units (CHUs), and a camera control unit (a single unit) that processes a color video signal composed of a red R signal, a green G signal, and a blue B signal from the camera head unit group 2 CCU) 23.

Of the four CHUs constituting the camera head unit group 2, the first is the camera (1) head unit 3, the second is the camera (2) head unit 8, and the third is the camera (3). ) The head unit 13 and the fourth unit are the camera (4) head unit 18.

Camera (1) The head unit 3 converts image light from a subject incident through an imaging lens 4 into a red signal R, a green signal G, and a blue signal B by a CCD solid-state imaging device 5 having a color separation prism. Are converted into digital R, G and B signals by an A / D converter 6 and further converted into serial signals by a parallel (P) / serial (S) converter 7 and output.

The camera (2) head unit 8 also includes
An imaging lens 9, a CCD solid-state imaging device 10, an A / D converter 11, and a P / S converter 12 are provided.
The digital R, G and B signals are converted into serial signals and output.

The camera (3) head unit 13
Also, an imaging lens 14, a CCD solid-state imaging device 15,
It has a / D converter 16 and a P / S converter 17, and similarly converts digital R, G and B signals into serial signals and outputs them.

The camera (4) head unit 18
Also, an imaging lens 19, a CCD solid-state imaging device 20, an A /
It includes a D converter 21 and a P / S converter 22, and similarly converts digital R, G and B signals into serial signals and outputs them.

The four serial digital R / G / B signals from the camera head unit group 2 are supplied to the CCU 23 via a transmission path such as a triax cable or fiber.

The CCU 23 is a time axis multiplexing processing system 28 for time axis multiplexing the above-mentioned four serial digital R / G / B signals, and contour enhancement processing is performed on the time axis multiplexed signal from the time axis multiplexing processing system 28. (Detail processing), such as image enhancer (IE) processing, matrix processing, gamma processing, knee processing, etc.
ocessing: PR) and a signal processing system 34 that performs video signal processing such as encoding (ENC) processing that is a compression encoding process, and a time axis on which the video signal processing is performed by the video signal processing system 34. A demultiplexing processing system 39 including, for example, three demultiplexers that separates the multiplexed signal into the original four video signals on the time axis. The four video signals from the three demultiplexers of the demultiplexing processing system 39 are output by the signal output system 58.

The above four serial digital R / Gs
The / B signal is first supplied to S / P converters 24, 25, 26 and 27 and is converted into a parallel signal. Hereinafter, S
The output signal of the / P converter 24 is a first-system parallel digital R / G / B signal, and the output signal of the S / P converter 25 is a second-system parallel digital R / G / B signal. The output signal of the / P converter 26 is a third system parallel digital R / G / B signal, and the output signal of the S / P converter 27 is the fourth system parallel digital R / G / B signal.
Signal.

The time axis multiplex processing system 28 includes four FIFOs 29, 30, 31 and 32 for four systems,
Switch 33 for switching the outputs of the FIFOs
Consists of

The parallel digital R / G / B signals of the first, second, third and fourth systems are FIFO-based.
The signals are supplied to the units 29, 30, 31, and 32, are delayed by a predetermined time in the order of arrival, are compressed, are switched by the changeover switch 33, and are multiplexed and output so as to be continuous on the time axis.

An ENC processing section 91 in the video signal processing system 34 converts the R / G / B signal into a Y / RY / BY signal, and then performs a color correction process, a saturation process, and the like. . The output of the ENC processing unit 91 is an ENC signal.

IE processing unit 35, PR processing unit 36 and EN
The C processing unit 91 performs each of the above processes by table processing using a table. The table processing of each of the processing units 35, 36, and 37 is controlled by a switching unit 38 whose switching is controlled by a timing pulse from a multiplex (MPX) timing control unit 37.

The demultiplexing processing system 39 includes three demultiplexers 40, 46 and 52 as described above. Each demultiplexer consists of one changeover switch and four FIFOs as follows.

The demultiplexer 40 includes a changeover switch 41
And FIFOs 42, 43, 44 and 45. The demultiplexer 46 includes a changeover switch 47 and FIFOs 48, 4
9, 50 and 51. The demultiplexer 52 includes a changeover switch 53 and FIFOs 54, 55, 56 and 57.

The demultiplexer 52 uses the switch 53 and the four FIFOs 54, 55, 56, and 57 to switch the digital R / G / B signals of the four systems processed by the PR processing unit 36 in the time axis direction. After quadrupling, the timing is adjusted and the D / A converters 71, 72, 73 and 7 are adjusted.
4 The above D / which constitutes the signal output system 58
The A converters 71, 72, 73 and 74 are connected to the first system R,
The G, B signals, the second R, G, B signals, the third R, G, B signals, and the fourth R, G, B signals are converted into analog signals, and output terminals 87, 88. , 89 and 90
For camera 1, camera 2, camera 3 and camera 4.

The demultiplexer 46 is provided with the ENC processing unit 91
Switch 47 for switching the Y / RY / BY signal from
And the four FIFOs 48, 49, 50 and 51,
After expanding 4 times in the time axis direction, adjust the timing,
It is supplied to D / A converters 63, 64, 65 and 66. Also, a serial digital interface (SDI) 6
7, 68, 69 and 70 are also provided. Signal output system 58
The above D / A converters 63, 64, 65, and 66 are composed of a first Y / RY / BY signal, a second Y / RY / BY signal, Y / RY-B of the third system
-Y signals and the Y / RY / BY signals of the fourth system are converted into analog signals, and output terminals 79, 80, 81 and 8
2 for camera 1, camera 2, camera 3 and camera 4
Supply for Also, SDI 67, 68, 69 and 70
Are the Y / RY / BY signals of the first system, and the Y / RY signals of the second system.
/ RY / BY signal, Y / RY / BY of the third system
The signal and the Y / RY / BY signal of the fourth system are multiplexed to form an SDI signal, and output terminals 83, 84, 85 and 8
6 for camera 1, camera 2, camera 3 and camera 4
Supply for use.

The demultiplexer 40 is provided with the ENC processing unit 91
The ENC signals for the four systems processed in step (1) are enlarged four-fold in the time axis direction using the changeover switch 41 and the four FIFOs 42, 43, 44, and 45, and then the timing is adjusted, and the D / A converter 59 , 60, 61 and 62. The D / A converter 5 constituting the signal output system 58
Reference numerals 9, 60, 61, and 62 denote a first system ENC signal, a second system ENC signal, a third system ENC signal, and a fourth system ENC signal.
The ENC signal of the system is converted into an analog signal and output terminal 7
5, 76, 77 and 78 are supplied for camera 1, camera 2, camera 3 and camera 4.

Here, as described above, these processes are performed independently on the signals of the first to fourth systems.
This is because the switching of each processing table is controlled by the switch 38 controlled by the MPX timing control unit 37.

As described above, in the camera system 1 according to the present embodiment, 4
Since the four video signals from the CHUs 3, 8, 13, and 18 can be processed by one CCU 23, the circuit scale of the camera system can be reduced, and the cost and space can be reduced.

The time axis multiplex processing system 28 of the camera system 1 and the multiplex separator 52 of the multiplex separation processing system 39 may have a configuration as shown in FIG.

FIG. 2 shows a configuration in which multiplexing is performed for each line. As a multiplexing method, line / field / frame units are conceivable, but each line is practical in consideration of delay.

The input terminal 101 is supplied with a first system parallel digital R / G / B signal. The input terminal 102 has a second parallel digital R / R.
A G / B signal is provided. Also, the input terminal 103
A third system of parallel digital R / G / B signals is supplied. The input terminal 104 is supplied with a fourth system of parallel digital R / G / B signals.

The time axis multiplex processing system corresponding to the time axis multiplex processing system 28 shown in FIG. 1 is a line which delays the video signal from the input terminal 102 by 0.25H with respect to the signal phase of the video signal from the input terminal 101. Memory 105 and input terminal 1
Line memory 10 which delays the video signal from H.03 by 0.5H
6, a line memory 107 for delaying the video signal from the input terminal 104 by 0.75H, and a line for delaying the read timing of the video signal from the input terminal 101 by a predetermined time and setting the read clock rate to four times the write clock rate. A memory 108, a line memory 109 that delays the read timing of a video signal from the line memory 105 by a predetermined time, and sets the read clock rate to four times the write clock rate, and a read timing of the video signal from the line memory 106 A line memory 110 that delays the time and sets the read clock rate to four times the write clock rate; and delays the read timing of the video signal from the line memory 107 by a predetermined time and sets the read clock rate to the write clock rate. Line memory 111 for four times
And a three-state buffer 11 for switching memory outputs from the line memories 108, 109, 110 and 111
2, 113, 114 and 115.

The demultiplexer corresponding to, for example, one demultiplexer 52 of the demultiplexer 39 shown in FIG. 1 is provided for the first system, the second system, and the third system from the signal processing system 116. And the video signal processing output for the fourth system in the time axis direction
Line memories 117, 118, 11 for double enlargement
9 and 120, a line memory 121 that delays the signal processing output for the first system expanded in the time axis direction by 0.75H by the line memory 117, and a line memory 118 expanded in the time axis direction by the line memory 118. A line memory 122 delays the signal processing output by 0.5H, and a line memory 123 delays the signal processing output for the third system expanded in the time axis direction by the line memory 119 by 0.25H.

For example, regarding the R signal, as shown in FIG. 3A, a horizontal blank (H-BL
The timing of K) is as follows. First, in the timing of FIG. 2A supplied to each input terminal, the first system (camera (1)), the second system (camera (2)), and the third system (camera) Both (3)) and the video signal of the fourth system (camera (4)) are in phase.

Next, the video signals of the cameras (2), (3) and (4) are compared with the video signals of the camera (1) through the line memories 105, 106 and 107, as shown in FIG. At the timing of (B),
As shown in FIG. 3B, the delay is 0.25H, 0.5H and 0.75H. This is because the line selection controller 130 supplies the line memories 105, 106 and 107 with read timing control signals RSTR1, RSTR2 and RSTR3 delayed by 0.25H. Note that the line selection controller 130 supplies the line memories 105, 106, and 107 with the write timing control signal RSTW having the same timing. The line memories 105, 106, and 107 are also supplied with a 13.5 MHz write / read clock from a frequency divider 128 obtained by dividing the 54 MHz clock from the clock generator 129.

Next, the line memories 108, 109, 1
Through the signals 10 and 111, the video signals of the camera (1), the camera (2), the camera (3), and the camera (4) are shown in FIG. 3C at the timing shown in FIG. Compression in the time axis direction. This is because the line memories 108, 10
The read control signals RSTR0 ', RSTR1', RSTR2 ', and RSTR3' are supplied to the readout signals 9, 110, and 111 such that the readout is performed with a delay of 0.75 H from the timing of FIG. And the write clock WCLK
(= 13.5 MHz), which is four times as high as 54 MHz. As shown in FIG. 3 (C), each signal has a section having no data of 3 / 4H.

Then, the three-state buffers 112 and 11
3, 114 and 115 are switched in accordance with the switching control signals END0 ', END1', END2 'and END3' from the line selection controller 130, so that at the timing shown in FIG. The switching multiplexed signal is time axis compressed as shown in D).

The signal processing system 116 performs an IE process, a PR process, and an ENC process on the time-axis-compressed switching multiplexed signal, similarly to the signal processing system 34 shown in FIG.
Now, from the signal processing system 116, at the timing shown in FIG. 2E, the multiplexed signal subjected to the PR processing as shown in FIG. 4E is sent to the line memories 117, 118, 119 and 120. Suppose that it was supplied.

The multiplex signal is supplied to the line memories 117, 1
18, 119 and 120, at the timing (F) in FIG. 2, as shown in (F) in FIG.
It is enlarged four times in the time axis direction. This means that the write timing of the multiplex signal to the line memories 117, 118, 119 and 120 is controlled by the write timing control signals RSTW0 ', RSTW1', RSTW2 'and RS from the line selection controller 130.
Supply TW3 'to make it different, and read timing
Read timing control signals RSTR0 '', RSTR1 '', RSTR2 ''
And RSTR3 ″ are supplied to make them different from each other because the read clock RCLK is 13.5 MHz which is / 4 times the write clock WCLK (= 54 MHz).

Then, via the line memories 121, 122 and 123, the video signal of the camera (1) is delayed by 0.75H, the video signal of the camera (2) is delayed by 0.5H, and the video signal of the camera (3) is Is delayed by 0.25H. Therefore, at the timing (G) in FIG. 2, a video signal having a phase, for example, an R signal is obtained as shown in (G) in FIG. These R signals are output from the output terminal 12.
4, 125, 126 and 127 are supplied to the signal output system 58 shown in FIG.

Even in a camera system having a CCU having the configuration shown in FIG.
Since the system video signal can be processed by one CCU, the circuit scale as a camera system can be reduced,
Cost reduction and space saving can be realized.

The imaging signal processing apparatus and method according to the present invention are not limited to the above embodiment, and one CCU can be used for five, six or more video signal inputs. Can be processed.

[0047]

According to the imaging signal processing apparatus of the present invention, a plurality of video signals are time-division multiplexed by a multiplex processing means, and the time-division multiplexed signal is subjected to video signal processing by a video signal processing means. Since the time-division multiplexed signal is separated into a plurality of video signals on the original time-axis, the circuit scale can be reduced,
Cost reduction and space saving can be realized.

Also, the imaging signal processing method according to the present invention
A plurality of video signals from a plurality of imaging units are time-division multiplexed, then processed, and further separated into a plurality of video signals on the original time axis, so that the circuit scale can be reduced, cost reduction, and space saving. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a camera system which is an embodiment of an imaging signal processing apparatus and method according to the present invention.

FIG. 2 is a circuit diagram showing another specific example of a main part of a camera control unit constituting the camera system.

3 is a timing chart of the circuit shown in FIG. 2 in a time axis multiplex processing system.

FIG. 4 is a timing chart of the demultiplexer of the circuit shown in FIG. 2;

[Explanation of symbols]

1 camera system, 2 camera head units, 3
Camera (1) Head Unit, 8 Camera (2) Head Unit, 13 Camera (3) Head Unit, 18
Camera (4) head unit, 23 camera control unit, 28 time axis multiplex processing system, 34 signal processing system, 39 demultiplexing processing system

Claims (8)

[Claims] 1. A multiplex processing means for time-multiplexing a plurality of video signals from a plurality of imaging means, a video signal processing means for performing video signal processing on a time-axis multiplexed signal from the multiplex processing means, and the video signal An image signal processing apparatus comprising: a separation processing unit configured to separate a time axis multiplexed signal from the processing unit into a plurality of video signals on an original time axis. 2. The imaging signal processing apparatus according to claim 1, wherein the plurality of video signals from the plurality of imaging means are each composed of a red R signal, a green G signal, and a blue B signal. 3. The imaging signal processing apparatus according to claim 1, wherein the multiplex processing means multiplexes the plurality of video signals on a time base in line units. 4. The imaging signal processing apparatus according to claim 1, wherein said video signal processing means performs image enhancer processing, processing processing, and encoding processing on said time axis multiplexed signal. 5. An imaging signal processing method, comprising: multiplexing a plurality of video signals from a plurality of imaging means on a time axis, processing the video signals, and further separating the video signals into a plurality of video signals on the original time axis. . 6. A method according to claim 1, wherein each of the plurality of video signals is a red R signal.
6. The imaging signal processing method according to claim 5, comprising a signal, a green G signal, and a blue B signal. 7. The imaging signal processing method according to claim 5, wherein the plurality of video signals are time-division multiplexed in line units. 8. The imaging signal processing method according to claim 5, wherein said video signal processing is image enhancer processing, processing processing, and encoding processing.