JPH11274437A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reading precision out of a memory cell transistor comprising a floating gate. SOLUTION: Memory cell transistor group comprising an array of memory cell transistors wherein a gate electrode and a drain electrode are faced each other relative to a common source line 8 and disposed in a matrix structure, and a reference transistor which is, wherein a gate electrode and a drain electrode are faced each other relative to a common source line, used as a discrimination reference value for judging whether a reading current of the memory cell transistor is 'H' level or 'L' level, are provided. Here, relative to deviation of a mask for forming an electrode in a process for manufacturing a semiconductor, position relationship is set so that the memory cell transistor group and the reference cell transistor are deviated in the same direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile semiconductor memory device having improved reading accuracy from a memory cell transistor having a floating gate.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: Elmer) in which a memory cell comprises a single transistor.
(ectrically Erasable Programmable ROM)
Each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In such a memory cell transistor having a double gate structure, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. Then, data is read by detecting a difference in operation characteristics of the memory cell transistor depending on whether or not charge is injected into the floating gate.

FIG. 5 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
FIG. 6 is a sectional view taken along line XX. This figure shows a split gate structure in which a part of the control gate is arranged side by side with the floating gate. A plurality of isolation regions 2 made of a selectively thick oxide film (LOCOS) are formed in a strip shape in a surface region of a P-type silicon substrate 1 to partition an element region. A floating gate 4 is arranged on a silicon substrate 1 with an oxide film 3 interposed between adjacent isolation regions 2.
This floating gate 4 is arranged independently for each memory cell. Also, the oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 and makes the end of the floating gate 4 an acute angle. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during data erasing operation. On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, control gates 6 are arranged corresponding to each column of the floating gates 4. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3. The floating gate 4 and the control gate 6 are arranged such that adjacent rows are plane-symmetric with each other. N-type first diffusion layers 7 and second diffusion layers 8 are formed in a substrate region between control gates 6 and a substrate region between floating gates 4. The first diffusion layers 7 are surrounded by the isolation regions 2 between the control gates 6 and are independent of each other.
The second diffusion layer 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, first diffusion layer 7, and second diffusion layer 8 constitute a memory cell transistor. Then, aluminum wiring 10 is arranged on control gate 6 via oxide film 9 in a direction crossing control gate 6. This aluminum wiring 10 is connected to first diffusion layer 7 through contact hole 11.

In the case of such a memory cell transistor having a double gate structure, the on-resistance between the source and the drain varies according to the amount of charge injected into the floating gate 4. The amount of electric charge injected into the floating gate 4 makes it possible to store data in a nonvolatile manner.

[0005]

In a nonvolatile semiconductor memory device as shown in FIGS. 5 and 6, a cell current flowing between a first diffusion layer 7 (drain) and a second diffusion layer 8 (source) is provided. Is compared with a reference value to read data. The reference value is also created by a reference cell transistor having a semiconductor structure as shown in FIG. This reference value needs to be a constant value. However, in practice, it is not always constant due to misalignment of the electrode mask in the semiconductor manufacturing process.

FIG. 4 shows this state. FIG. 4 shows a part of the nonvolatile semiconductor memory device shown in FIG. Now, it is assumed that the control gate 6 is shifted to the left as shown in FIG. Then
The first diffusion layer 7 (drain) diffused using the control gate 6 shifts from the solid line to the position indicated by the dotted line to the left.
As a result, the gate length becomes longer by the distance X from the original length d, and the cell current is reduced accordingly.

On the other hand, the opposite phenomenon occurs in the memory cell transistor shown in FIG. 4 which is arranged with the source electrode interposed therebetween. That is, the control gate 6 is shifted to the left, the gate length is shortened by the distance X, and the cell current is increased accordingly. Therefore, it is conceivable to use two opposed reference cell transistors in parallel. By doing so, the increase or decrease of the cell current can be offset.

However, only one of two opposing memory cell transistors is used as a memory cell transistor for reading data. For this reason, even if the reference value is constant, the data to be read has variations, and some data have a small read margin. For this reason, it has been desired that the cell current can be stably read even if the mask alignment for the electrode is misaligned in the semiconductor manufacturing process.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a memory cell transistor in which a gate electrode and a drain electrode are arranged to face a common source line. Are arranged in a matrix, and a gate electrode and a drain electrode are arranged to face a common source line, and the read current of the memory cell transistor is at “H” level. A reference cell transistor used as a reference value for determining whether the memory cell transistor group is at the “L” level, wherein the memory cell transistor group and the reference It is characterized in that the positional relationship between the cell transistor and the cell transistor is set so as to be shifted in the same direction.

[0010]

FIG. 1 is a circuit diagram showing a first embodiment of the nonvolatile semiconductor memory device of the present invention. FIG.
FIG. 3 is a circuit diagram of a memory cell portion. This figure shows a case where memory cells are arranged in 4 rows × 4 columns. First, the basic operation of the memory cell will be described.

In a memory cell transistor 20 having a double gate structure, a control gate is connected to a word line 21 and a drain and a source are connected to a bit line 22 and a source line 23, respectively. Each bit line 22 is connected to a data line 25 via a selection transistor 24. A sense amplifier (not shown) for reading a voltage value is connected to each bit line 22. And
A write clock φW having a constant period is applied to each memory cell transistor 20 from the source line 23, and a read clock φR is applied from the data line 25. In an ordinary device, a control gate itself commonly formed by the memory cell transistors 20 in the same row is used as the word line 21, and an aluminum wiring connected to the source is used as the bit line 22. A source region extending in parallel with the control gate is used as the source line 23.

The row selection information LS1 to LS4 is generated based on row address information,
By selecting one of these, a specific row of the memory cell transistors 20 is activated. Column selection signals CS1 to CS
Numeral 4 is generated based on the column address information, and activates a specific column of the memory cell transistors 20 by turning on one of the selection transistors 24. Thereby, one of the plurality of memory cell transistors 20 arranged in a matrix is designated according to the row address information and the column address information, and is connected to the data line 25.

When writing data to the memory cell transistor 20, a ground potential (for example, 0 V) is applied from the bit line 22 to the memory cell transistor 20, and a write potential (for example, 14 V) is applied from the source line 23. I do. Thus, data is written in the specific memory cell transistor 20 selected in response to the row selection information LS1 to LS4 and the column selection information CS1 to CS4, that is, charge is injected into the floating gate. When reading data written in the memory cell transistor 20, the memory cell transistor 2
For 0, the read potential from the bit line 22 (for example, 5
V) from the source line 23 to the ground potential (for example, 0
V). At this time, a current flows through the memory cell transistor 20 in the selected state, and the potential of the bit line 22 changes according to the on-resistance value of the memory cell transistor 20, so that the bit line potential is read by the sense amplifier. You.

Reference numerals 50 and 51 in FIG. 1 denote reference cell transistors. This reference cell transistor 5
Reference numerals 0 and 51 denote whether the gate electrode and the drain electrode are arranged opposite to the common source line 52, and whether the read current of the memory cell transistor 20 is at the “H” level or the “L” level. Used as a discrimination reference value. For example, among the memory cell transistors 20 forming the memory cell transistor group, the source line 2 shown in FIG.
It is assumed that the memory cell transistor 20 located on the upper side of No. 3 is selected. In that case, the common source line 52
Is used as a reference signal source. That is, the switch 53 is switched to the b side. The memory cell transistor 20 and the reference cell transistor 50 are arranged so as to be physically parallel to each other, and the one on the same side (upper side) as the common source line is selected.

Then, even if the gate length of the memory cell transistor 20 changes due to a mask shift, the gate length of the reference cell transistor 50 also changes by the same amount. That is, the read value and the reference value are linked, and the relative value does not change and the margin does not change. Therefore, data from the memory cell transistor 20 can be stably read.

Conversely, assume that the memory cell transistor 20 located below the source line 23 in FIG. 1 is selected. In that case, the switch 53 is switched to the a side by using the reference cell transistor 51 located below the common source line 52 as a reference signal source. FIG. 3 is a sectional view of a semiconductor structure of the reference cell transistors 50 and 51 of FIG. Reference cell transistor 5
0, 51 are gate electrodes 50A,
51A and the drain electrodes 50B and 51B are arranged to face each other, and the cell current of these two transistors can be selected by the switch 53.

FIG. 2 shows a circuit for comparing cell currents of the memory cell transistor 20 and the reference cell transistor 50 selected in FIG. Now, it is assumed that the memory cell transistor 20 is turned on, the cell current I flows, and the current I / 2 flows to the reference cell transistor 50. The cell current I is converted into a voltage V by a current / voltage conversion circuit 55, and the reference cell current I / 2 is converted into a voltage V / 2 by a current / voltage conversion circuit 56. Then, the current I0 flows through the transistor 57, and the current I0 / 2 flows through the transistor 58. Then, the current I 0/2 flows from the terminal 60 to the transistor 57 by the operation of the current mirror circuit 59. This current makes it clear that the cell transistor is on.

FIG. 7 is a diagram showing a pattern arrangement of the nonvolatile semiconductor memory device of FIG. 7, the same elements as those in FIG. 5 are denoted by the same reference numerals. The left side of FIG. 7 shows a memory cell transistor portion, and the right side shows a reference cell transistor. In FIG. 7, 2A is an isolation region, 4A is a floating gate, 6A is a word line (control gate), 52 is a common source line,
A and 10B are bit lines, and 50 and 51 are reference cell transistors of FIG.

As is clear from the comparison of the left and right pattern arrangements in FIG. 7, the respective regions for forming the transistors are arranged in the same size on the left and right sides in parallel. For example,
The left control gate 6 and the right word line 6 are arranged in parallel with the same width. Note that the reference cell transistors 50 and 51 have the shape shown in the figure because the word lines are commonly connected.

The left bit line 10 (aluminum wiring 10) is parallel to the right bit lines 10A and 10B,
The width is the same, and the same applies to the left and right common source lines. By taking such a shape on the left and right, even if a mask shift occurs, the same effect is exerted on the left and right elements, and the amount of variation can be made the same.

[0021]

According to the present invention, the memory cell transistor and the reference cell transistor are arranged so as to be physically parallel to each other, and both of them are selected on the same side as the common source line. Then, even if the gate length of the memory cell transistor changes due to a mask shift, the gate length of the reference cell transistor also changes by the same amount. That is, the read value and the reference value are linked, and the relative value does not change and the margin does not change. Therefore, the reading accuracy from the memory cell transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram illustrating a comparison operation of the first embodiment.

FIG. 3 is a sectional view showing a semiconductor structure of a nonvolatile semiconductor memory device according to the present invention;

FIG. 4 is a semiconductor cross-sectional structure diagram of a conventional nonvolatile semiconductor memory device.

FIG. 5 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 6 is a sectional view taken along line XX of FIG. 5;

FIG. 7 is a diagram showing a pattern arrangement of the nonvolatile semiconductor memory device of FIG. 1;

[Explanation of symbols]

 Reference Signs List 20 memory cell transistor 21 word line 22 bit line 23 source line 50 reference cell transistor 51 reference cell transistor 52 common source line 53 switch

Claims (2)

[Claims] 1. A memory cell transistor group in which a memory cell transistor in which a gate electrode and a drain electrode are arranged to face a common source line is arranged in a matrix. An electrode and a drain electrode are disposed opposite to each other, and a reference cell transistor used as a reference value for determining whether a read current of the memory cell transistor is at an “H” level or an “L” level And a positional relationship between the memory cell transistor group and the reference cell transistor is set so as to be shifted in the same direction with respect to a mask shift for forming an electrode in a semiconductor manufacturing process. Nonvolatile semiconductor memory device. 2. The memory cell transistor and the reference cell transistor are arranged to have a common source region, two floating gates arranged to face the common source region, and to be arranged to face the common source region. 2. The non-volatile semiconductor memory device according to claim 1, comprising two control gates and two drain regions arranged opposite to the common source region.