JPH11274397A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11274397A JPH11274397A JP10079597A JP7959798A JPH11274397A JP H11274397 A JPH11274397 A JP H11274397A JP 10079597 A JP10079597 A JP 10079597A JP 7959798 A JP7959798 A JP 7959798A JP H11274397 A JPH11274397 A JP H11274397A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- semiconductor elements
- semiconductor element
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子をベー
ス基材上に実装し樹脂封止してなる半導体装置に関す
る。The present invention relates to a semiconductor device having a semiconductor element mounted on a base material and sealed with a resin.
【０００２】[0002]
【従来の技術】半導体装置における半導体素子の封止形
態としては、一般に、セラミックや金属などを使用した
気密封止と、絶縁性合成樹脂を使用した樹脂封止（樹脂
モールド封止）とが知られている。後者の樹脂封止は、
前者の気密封止に比べて信頼性が若干劣るものの半導体
素子の占拠率が極めて高いこと、さらには量産が可能で
製造コストを低く抑え得ることなど、生産性と経済性の
面で大きなメリットを有している。2. Description of the Related Art In general, as a sealing form of a semiconductor element in a semiconductor device, there are known a hermetic sealing using a ceramic or a metal, and a resin sealing (resin molding sealing) using an insulating synthetic resin. Have been. The latter resin encapsulation
Although the reliability is slightly inferior to the former hermetic sealing, there are significant advantages in terms of productivity and economy, such as an extremely high occupancy rate of semiconductor elements, and the fact that mass production is possible and manufacturing costs can be kept low. Have.
【０００３】このような樹脂封止型の半導体装置の一種
として、従来より、金属製のリードフレーム上に半導体
素子を搭載し、ワイヤボンディングなどにより電気的に
接続するとともに、半導体素子とワイヤとの接合部を、
エポキシ樹脂などの樹脂材料のモールド成形により被覆
・封止した構造のものが知られている。As one type of such a resin-encapsulated semiconductor device, a semiconductor element is conventionally mounted on a metal lead frame and electrically connected by wire bonding or the like, and the semiconductor element is connected to a wire. The joint
A structure in which a resin material such as an epoxy resin is covered and sealed by molding is known.
【０００４】あるいは、ガラス−エポキシ銅張積層板の
ような銅張積層板を用いて、インナーリード等の配線群
およびこれらの配線群を他面側に導出するスルーホール
接続部をそれぞれ形成し、得られた配線板の上に半導体
素子を搭載して、ワイヤボンディング等を行なうととも
に、モールド成形により樹脂封止層を形成した構造の半
導体装置も開発されている。Alternatively, by using a copper-clad laminate such as a glass-epoxy copper-clad laminate, wiring groups such as inner leads and through-hole connecting portions for leading these wiring groups to the other side are formed. A semiconductor device having a structure in which a semiconductor element is mounted on the obtained wiring board to perform wire bonding and the like and a resin sealing layer is formed by molding is also being developed.
【０００５】そしてこのような半導体装置では、Ｉ／Ｏ
端子数の増加、外形の小型化、あるいは実装の容易化な
どの要請に対処するため、配線板の裏面に外部接続端子
として、はんだ等のボールを格子（アレイ）状に配列し
てバンプを形成した、ボールグリッドアレイとよばれる
構造が多用されている。さらには、半導体装置の薄型化
あるいは小型化にパッケージングの面から対処したもの
として、たとえば外形を半導体素子（チップ）の大きさ
に合わせてコンパクトに形成したチップサイズパッケー
ジなどが知られている。In such a semiconductor device, I / O
Bumps are formed by arranging balls of solder etc. in a grid (array) form external connection terminals on the back side of the wiring board in order to respond to demands such as an increase in the number of terminals, downsizing of the outer shape, and ease of mounting. Such a structure called a ball grid array is frequently used. Further, a chip size package whose outer shape is made compact according to the size of a semiconductor element (chip), for example, is known as a method of coping with the thinning or miniaturization of a semiconductor device from the viewpoint of packaging.
【０００６】[0006]
【発明が解決しようとする課題】ところでこのような半
導体装置は、半導体素子の占める面積で表される情報量
あるいはシステム領域を有しており、情報量向上の要求
に対しては、一般に、半導体素子を高度に集積させる、
すなわち半導体素子面積をそれに見合うように拡大させ
ることによって対処している。したがって、半導体素子
の樹脂封止体である半導体装置においては、パッケージ
をコンパクトに形成したとしても、情報量の向上に伴い
パッケージサイズが大型化することは避けられなかっ
た。However, such a semiconductor device has an information amount or a system area represented by an area occupied by a semiconductor element. Highly integrated elements,
That is, the problem is dealt with by enlarging the area of the semiconductor element to match it. Therefore, in a semiconductor device which is a resin-sealed body of a semiconductor element, even if the package is formed in a compact size, it is inevitable that the package size increases with an increase in the amount of information.
【０００７】しかしながら、近年、電子機器の高機能化
とともに小型化がさらに強く求められており、半導体装
置を情報量向上のために大型化させることは、他の機能
を担う部材の占める容積を奪うことにつながるので、好
ましくない。そこで、半導体装置においては、基板上に
占めるパッケージの面積を増加させることなく、その情
報量を向上させることが求められていた。[0007] However, in recent years, there has been a strong demand for more compact electronic devices as well as higher functionality. Increasing the size of a semiconductor device in order to increase the amount of information takes up the volume occupied by members having other functions. It is not preferable because it leads to things. Therefore, in a semiconductor device, it has been required to improve the information amount without increasing the area of the package occupying the substrate.
【０００８】本発明は、上記事情に対処しようとして成
されたものであり、従来と同じパッケージ面積で情報量
を向上させ効率よく入出力を行い得る高機能の半導体装
置を提供すること、あるいは従来より小さいパッケージ
面積で同等の機能を有する半導体装置を提供すること
を、その目的としている。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a high-performance semiconductor device capable of efficiently inputting and outputting information with the same package area as the conventional one. It is an object of the present invention to provide a semiconductor device having the same function with a smaller package area.
【０００９】[0009]
【課題を解決するための手段】すなわち本発明の半導体
装置は、所要の配線群が形成されたベース基材上に、複
数個の半導体素子が多段に重ね合わされて実装され、前
記複数個の半導体素子の実装部が絶縁性樹脂により被覆
され封止されて成ることを、その特徴としている。That is, in the semiconductor device of the present invention, a plurality of semiconductor elements are mounted in a multi-tiered manner on a base material on which a required wiring group is formed. It is characterized in that the mounting portion of the element is covered with an insulating resin and sealed.
【００１０】本発明の半導体装置は、前記複数個の半導
体素子が、大きさの順に多段に重ね合わされ、かつ前記
複数個の半導体素子のうちで最大面積のものが前記ベー
ス基材表面に接して実装されていることを、さらなる特
徴としている。[0010] In the semiconductor device of the present invention, the plurality of semiconductor elements may be stacked in multiple stages in the order of size, and one of the plurality of semiconductor elements having a maximum area may be in contact with the surface of the base substrate. The feature is that it is implemented.
【００１１】本発明においてベース基材としては、従来
の半導体装置において使用可能であるたとえば樹脂基
板、セラミック基板、あるいは金属基板などが同様に使
用可能である。また、半導体素子の実装部を被覆し封止
する絶縁性樹脂としても、従来の半導体装置において使
用可能であるたとえばエポキシ樹脂などが使用可能であ
る。In the present invention, a resin substrate, a ceramic substrate, a metal substrate, or the like, which can be used in a conventional semiconductor device, can be similarly used as the base substrate. Further, as the insulating resin for covering and sealing the mounting portion of the semiconductor element, for example, an epoxy resin which can be used in a conventional semiconductor device can be used.
【００１２】本発明において、半導体素子を重ね合わせ
る段数には、パッケージ高さが許容範囲内にある限りで
はとくに上限はない。また、薄いウエハを用いるように
すれば、パッケージ高さを従来の高さの範囲内に納める
ことも容易である。あるいはベース基材としてキャビテ
ィ構造を有する基板も良好に使用可能であるので、本発
明の半導体装置は、メイン基板へソケット挿入とするこ
とも可能である。また、メイン基板に接続するための外
部接続子としては、たとえばはんだボールや挿入ピンな
どを用いることができる。In the present invention, there is no particular upper limit on the number of stages in which the semiconductor elements are overlapped as long as the package height is within an allowable range. If a thin wafer is used, it is easy to keep the package height within the range of the conventional height. Alternatively, since a substrate having a cavity structure can be favorably used as the base material, the semiconductor device of the present invention can also be inserted into the main substrate with a socket. Further, as an external connector for connecting to the main board, for example, a solder ball or an insertion pin can be used.
【００１３】本発明の半導体装置は、従来の半導体装置
の製造工程の繰返しによって容易に製造することが可能
であり、特別な製造装置を必要としないので従来の製造
装置を使用することもできる。The semiconductor device of the present invention can be easily manufactured by repeating the manufacturing process of the conventional semiconductor device, and does not require any special manufacturing device, so that the conventional manufacturing device can be used.
【００１４】本発明の半導体装置の製造に際しては、ま
ず従来装置と同様にベース基材の少なくとも一主面に信
号線やインナーリード群などの配線群を常法にしたがっ
て形成し、必要に応じてこれらの配線群を他主面に導出
するための導通孔を、やはり常法にしたがって形成す
る。次いで、搭載すべき半導体素子の中で一番面積の大
きいものをベース基材の所定の位置に配置し、エポキシ
樹脂系などの絶縁性接着剤により接着固定（ダイボン
ド）し、その上に二番目に大きいものを重ねて同様に接
着固定し、所要の段数に達するまでこの操作を繰返す。In manufacturing the semiconductor device of the present invention, first, a wiring group such as a signal line or an inner lead group is formed on at least one principal surface of the base material in a conventional manner as in the case of the conventional device. Conducting holes for leading these wiring groups to the other main surface are also formed according to a conventional method. Next, the semiconductor element having the largest area among the semiconductor elements to be mounted is placed at a predetermined position on the base material, and is fixed (die-bonded) with an insulating adhesive such as an epoxy resin, and the second is placed thereon. , And repeat the operation until the required number of stages is reached.
【００１５】そのようにして半導体素子を重ね合わせて
ベース基材に搭載した後、最下段に位置する最大面積の
半導体素子の電極端子を、ベース基材に形成された配線
群の所定の位置に、金線などのボンディングワイヤを用
いて接続する。次いで、下から２段目に位置する二番目
に大きい半導体素子の電極端子を、同様にベース基材上
の配線群の所定の位置に接続する。After the semiconductor elements are superimposed on each other and mounted on the base material in this manner, the electrode terminals of the semiconductor element having the largest area located at the lowermost stage are placed at predetermined positions of the wiring group formed on the base material. And a bonding wire such as a gold wire. Next, the electrode terminal of the second largest semiconductor element located in the second stage from the bottom is similarly connected to a predetermined position of the wiring group on the base substrate.
【００１６】すべての半導体素子の電極端子が、ベース
基材に形成された配線群の所定の位置にワイヤボンディ
ングされた後、半導体素子とボンディングワイヤとそれ
らの接合部を被覆し封止する樹脂封止層を形成する。そ
の後、ベース基材裏面にはんだボールを格子状に配列し
てバンプを形成するなどして外部接続端子を設けて、本
発明の半導体装置が得られる。After the electrode terminals of all the semiconductor elements are wire-bonded to predetermined positions of the wiring group formed on the base material, a resin seal for covering and sealing the semiconductor elements, the bonding wires and their joints. A stop layer is formed. Thereafter, external connection terminals are provided by, for example, arranging solder balls on the back surface of the base material in a grid pattern to form bumps, thereby obtaining the semiconductor device of the present invention.
【００１７】本発明においては、複数個の半導体素子
が、大きさの順に多段に重ね合わされ、かつそれらのう
ちで最大面積のものがベース基材表面に接して搭載され
た構造であるので、製造にあたっては、すべての半導体
素子を搭載したのちまとめてワイヤボンディングを行う
ことができる。According to the present invention, since a plurality of semiconductor elements are stacked in multiple stages in the order of size, and a semiconductor element having the largest area is mounted in contact with the surface of the base substrate. In this case, after all the semiconductor elements are mounted, wire bonding can be performed collectively.
【００１８】[0018]
【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１９】実施例１ 図１にその断面の概略を示すように、ベース基材の一方
の表面に、銅箔のフォトパターニングで所要の配線群
（図示されていない）を予め形成し、それらの配線群を
ベース基材の裏面に導出するための複数の孔（図示され
ていない）を、形成した。そして、このようにして準備
されたベース基材１の表面上の所定の位置に半導体素子
２を配置し、エポキシ樹脂系接着剤により接着固定し
た。そして、半導体素子２の上に、半導体素子２よりも
面積の小さい半導体素子３を重ねて同様に接着固定し
た。EXAMPLE 1 As shown schematically in FIG. 1, a required wiring group (not shown) is previously formed on one surface of a base material by photo-patterning a copper foil. A plurality of holes (not shown) for leading the wiring group to the back surface of the base material were formed. Then, the semiconductor element 2 was arranged at a predetermined position on the surface of the base material 1 prepared in this way, and was adhered and fixed with an epoxy resin-based adhesive. Then, the semiconductor element 3 having an area smaller than that of the semiconductor element 2 was overlaid on the semiconductor element 2, and similarly bonded and fixed.
【００２０】その後、半導体素子２の電極端子を、ベー
ス基材１に形成された配線群の所定の位置に、ボンディ
ングワイヤ４を用い常法にしたがって接続した。次い
で、半導体素子３の電極端子を、同様にベース基材上の
配線群の所定の位置にボンディングワイヤ５を用いて常
法にしたがって接続した。Thereafter, the electrode terminals of the semiconductor element 2 were connected to predetermined positions of a group of wirings formed on the base material 1 using bonding wires 4 in a conventional manner. Next, the electrode terminals of the semiconductor element 3 were similarly connected to predetermined positions of the wiring group on the base material by using the bonding wires 5 according to a conventional method.
【００２１】ワイヤボンディング完了後、半導体素子
２、３とボンディングワイヤ４、５とそれらの接合部を
被覆し封止する樹脂封止層６を、常法にしたがいエポキ
シ樹脂を用いてトランスファーモールドにより形成し
た。その後、ベース基材１の裏面に、はんだボール７を
格子状に取り付けてバンプを形成して、外部接続端子と
した。After completion of the wire bonding, a resin sealing layer 6 for covering and sealing the semiconductor elements 2 and 3 and the bonding wires 4 and 5 and their joints is formed by transfer molding using an epoxy resin according to a conventional method. did. Thereafter, solder balls 7 were attached in a grid pattern on the back surface of the base material 1 to form bumps, thereby forming external connection terminals.
【００２２】このようにして得られた本発明の半導体装
置は、半導体素子２の占めるパッケージ面積と同面積
で、半導体素子３の情報量も加わった高機能のものであ
った。 実施例２ ベース基材として、図２にその断面の概略を示すキャビ
ティ構造のベース基材１０を用いた他は実施例１と同様
にして、本発明の半導体装置を作製した。実施例１と同
様に半導体素子２の占めるパッケージ面積と同面積で、
半導体素子３の情報量も加わった高機能のものが得られ
た。The semiconductor device of the present invention obtained as described above has a high function with the same area as the package area occupied by the semiconductor element 2 and the information amount of the semiconductor element 3. Example 2 A semiconductor device of the present invention was manufactured in the same manner as in Example 1 except that a base substrate 10 having a cavity structure whose outline is shown in FIG. 2 was used as the base substrate. The same area as the package area occupied by the semiconductor element 2 as in the first embodiment,
A high-performance semiconductor element 3 with an added amount of information was obtained.
【００２３】なお以上の実施例は半導体素子の２段の重
ね合わせに関するものであるが、本発明は、上記２段の
重ね合わせに限定されるものではない。また外部接続端
子としてはんだボールを使用しているが本発明はこれに
限定されるものではない。Although the above embodiments relate to two-stage superposition of semiconductor elements, the present invention is not limited to the two-stage superposition. Although solder balls are used as external connection terminals, the present invention is not limited to this.
【００２４】比較例 図３は、実施例１、２の半導体装置で用いられたものと
同様の半導体素子２を用いて得られた従来の樹脂封止型
の半導体装置の断面の概略図である。図１、２と共通す
る部分には同じ符号が付してある。Comparative Example FIG. 3 is a schematic sectional view of a conventional resin-encapsulated semiconductor device obtained by using a semiconductor element 2 similar to that used in the semiconductor devices of Examples 1 and 2. . 1 and 2 are denoted by the same reference numerals.
【００２５】この半導体装置は、実施例１、２とほぼ同
じパッケージサイズであるが、実施例１、２に比較して
半導体素子３の情報量を含まない分だけ機能が劣るもの
であった。This semiconductor device has substantially the same package size as the first and second embodiments, but is inferior to the first and second embodiments in that the information amount of the semiconductor element 3 is not included.
【００２６】[0026]
【発明の効果】以上説明したように、本発明によれば、
従来と同じパッケージ面積で効率よく入出力を行い得る
高機能の半導体装置、あるいは従来より小さいパッケー
ジ面積で同等の機能を有する半導体装置を、特殊な装置
や工程を必要とせずに提供し得る。As described above, according to the present invention,
A high-performance semiconductor device capable of efficiently performing input / output with the same package area as that of the related art, or a semiconductor device having the same function with a smaller package area of the related art can be provided without requiring a special device or process.
【図１】実施例１の半導体装置の構造を説明するための
断面概略図である。FIG. 1 is a schematic sectional view illustrating the structure of a semiconductor device according to a first embodiment.
【図２】実施例２の半導体装置の構造を説明するための
断面概略図である。FIG. 2 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment.
【図３】比較例の半導体装置の構造を説明するための断
面概略図である。FIG. 3 is a schematic sectional view illustrating the structure of a semiconductor device of a comparative example.
【符号の説明】 １……ベース基材 ２、３……半導体素子 ４、５……ボンディングワイヤ ６……樹脂封止層 ７……はんだボール １０……キャビティ構造のベース基材[Description of Signs] 1 ... Base substrate 2, 3 ... Semiconductor element 4, 5 ... Bonding wire 6 ... Resin sealing layer 7 ... Solder ball 10 ... Base material having cavity structure
Claims (2)
に、複数個の半導体素子が多段に重ね合わされて実装さ
れ、前記複数個の半導体素子の実装部が絶縁性樹脂によ
り被覆され封止されて成ることを特徴とする半導体装
置。A plurality of semiconductor elements are mounted on a base material on which a required wiring group is formed in a multi-tiered manner, and mounting portions of the plurality of semiconductor elements are covered with an insulating resin and sealed. A semiconductor device characterized by being stopped.
多段に重ね合わされ、かつ前記複数個の半導体素子のう
ちで最大面積のものが前記ベース基材表面に接して実装
されていることを特徴とする請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the plurality of semiconductor elements are stacked in multiple stages in the order of size, and a semiconductor element having a maximum area among the plurality of semiconductor elements is mounted in contact with the surface of the base substrate. The semiconductor device according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10079597A JPH11274397A (en) | 1998-03-26 | 1998-03-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10079597A JPH11274397A (en) | 1998-03-26 | 1998-03-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11274397A true JPH11274397A (en) | 1999-10-08 |
Family
ID=13694422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10079597A Withdrawn JPH11274397A (en) | 1998-03-26 | 1998-03-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11274397A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002151644A (en) * | 2000-09-04 | 2002-05-24 | Fujitsu Ltd | Laminated semiconductor device and manufacturing method thereof |
| KR100631910B1 (en) * | 1999-12-13 | 2006-10-04 | 삼성전자주식회사 | Multi-chip package using same chip |
-
1998
- 1998-03-26 JP JP10079597A patent/JPH11274397A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100631910B1 (en) * | 1999-12-13 | 2006-10-04 | 삼성전자주식회사 | Multi-chip package using same chip |
| JP2002151644A (en) * | 2000-09-04 | 2002-05-24 | Fujitsu Ltd | Laminated semiconductor device and manufacturing method thereof |
| JP4570809B2 (en) * | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | Multilayer semiconductor device and manufacturing method thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050607 |