JPH11274397A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH11274397A
JPH11274397A JP7959798A JP7959798A JPH11274397A JP H11274397 A JPH11274397 A JP H11274397A JP 7959798 A JP7959798 A JP 7959798A JP 7959798 A JP7959798 A JP 7959798A JP H11274397 A JPH11274397 A JP H11274397A
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semiconductor device
semiconductor
plurality
semiconductor elements
mounted
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JP7959798A
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Japanese (ja)
Inventor
Koichi Yamada
幸一 山田
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Toshiba Chem Corp
東芝ケミカル株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with advanced functions, which causes information content to be increased by using the same package area as the conventional case, and effectively enable inputting and outputting. SOLUTION: This semiconductor device has a structure in which a plurality of semiconductor elements 2, 3 are multistagewise stacked and mounted on a base substratum member 1 on which a necessary wiring group is formed, and mounted parts of a plurality of the semiconductor elements are covered with insulating resin and encapsulated. It is preferable that a plurality of the semiconductor elements are multistagewise stacked in the order of size, and the semiconductor element whose area is a maximum out of the plurality of the semiconductor elements is mounted which is in contact with respect to the surface of the base substratum member.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、半導体素子をベース基材上に実装し樹脂封止してなる半導体装置に関する。 The present invention relates to relates to a semiconductor device comprising sealed mounting to a resin sealed semiconductor device on a base substrate.

【0002】 [0002]

【従来の技術】半導体装置における半導体素子の封止形態としては、一般に、セラミックや金属などを使用した気密封止と、絶縁性合成樹脂を使用した樹脂封止(樹脂モールド封止)とが知られている。 The sealing form of the semiconductor device in a semiconductor device, in general, a hermetically sealed using a ceramic or metal, resin sealing (resin mold sealing) using an insulating synthetic resin TogaTomo It is. 後者の樹脂封止は、 The latter resin sealing,
前者の気密封止に比べて信頼性が若干劣るものの半導体素子の占拠率が極めて高いこと、さらには量産が可能で製造コストを低く抑え得ることなど、生産性と経済性の面で大きなメリットを有している。 It occupancy of a semiconductor device of which reliability is somewhat inferior as compared with the former hermetic seal is very high, such that more capable suppressing the manufacturing cost can be mass-produced, significant benefits in terms of productivity and economy It has.

【0003】このような樹脂封止型の半導体装置の一種として、従来より、金属製のリードフレーム上に半導体素子を搭載し、ワイヤボンディングなどにより電気的に接続するとともに、半導体素子とワイヤとの接合部を、 [0003] As one type of such a resin sealed semiconductor device, conventionally, a semiconductor element is mounted on a metal lead frame, a wire bonding or the like as well as electrically connected, the semiconductor element and the wire and the the junction,
エポキシ樹脂などの樹脂材料のモールド成形により被覆・封止した構造のものが知られている。 A structure that hermetically coated-sealing by molding a resin material such as epoxy resins.

【0004】あるいは、ガラス−エポキシ銅張積層板のような銅張積層板を用いて、インナーリード等の配線群およびこれらの配線群を他面側に導出するスルーホール接続部をそれぞれ形成し、得られた配線板の上に半導体素子を搭載して、ワイヤボンディング等を行なうとともに、モールド成形により樹脂封止層を形成した構造の半導体装置も開発されている。 [0004] Alternatively, the glass - with copper-clad laminate such as an epoxy copper clad laminate, the wiring group such as inner leads and the through hole connection portion to derive these wiring group on the other side are formed respectively, obtained by mounting a semiconductor element on the wiring board, it performs a wire bonding or the like, even a semiconductor device having the structure to form a resin sealing layer has been developed by molding.

【0005】そしてこのような半導体装置では、I/O [0007] In such a semiconductor device, I / O
端子数の増加、外形の小型化、あるいは実装の容易化などの要請に対処するため、配線板の裏面に外部接続端子として、はんだ等のボールを格子(アレイ)状に配列してバンプを形成した、ボールグリッドアレイとよばれる構造が多用されている。 Increasing the number of terminals, formed to deal with requests, such as ease of size reduction, or implementation of the outline, as external connection terminals on the rear surface of the circuit board, the bumps are arranged a ball such as solder lattice (array) was, is frequently used structure called a ball grid array. さらには、半導体装置の薄型化あるいは小型化にパッケージングの面から対処したものとして、たとえば外形を半導体素子(チップ)の大きさに合わせてコンパクトに形成したチップサイズパッケージなどが知られている。 Furthermore, as those addressed in terms of packaging for thinning or miniaturization of semiconductor devices, such as a chip size package formed compactly contoured to the size of the semiconductor element (chip) is known.

【0006】 [0006]

【発明が解決しようとする課題】ところでこのような半導体装置は、半導体素子の占める面積で表される情報量あるいはシステム領域を有しており、情報量向上の要求に対しては、一般に、半導体素子を高度に集積させる、 [0005] Meanwhile such a semiconductor device has an information amount or a system area represented by the area occupied by a semiconductor device, for the required amount of information improves, in general, a semiconductor is highly integrated device,
すなわち半導体素子面積をそれに見合うように拡大させることによって対処している。 That is addressed by expanding to meet the semiconductor element area in it. したがって、半導体素子の樹脂封止体である半導体装置においては、パッケージをコンパクトに形成したとしても、情報量の向上に伴いパッケージサイズが大型化することは避けられなかった。 Accordingly, in the semiconductor device is a resin sealing body of a semiconductor device, even to form a package in a compact, the package size with improvement in the amount of information increases in size was inevitable.

【0007】しかしながら、近年、電子機器の高機能化とともに小型化がさらに強く求められており、半導体装置を情報量向上のために大型化させることは、他の機能を担う部材の占める容積を奪うことにつながるので、好ましくない。 However, recent years, size reduction is required more strongly with high functionality of electronic devices, increasing the size of the order of a semiconductor device information amount improved deprives the volume occupied by the member responsible for other functions since the leads to, which is not preferable. そこで、半導体装置においては、基板上に占めるパッケージの面積を増加させることなく、その情報量を向上させることが求められていた。 Therefore, in the semiconductor device, without increasing the area of ​​the package it occupied on the substrate, improving the amount of information has been required.

【0008】本発明は、上記事情に対処しようとして成されたものであり、従来と同じパッケージ面積で情報量を向上させ効率よく入出力を行い得る高機能の半導体装置を提供すること、あるいは従来より小さいパッケージ面積で同等の機能を有する半導体装置を提供することを、その目的としている。 [0008] The present invention has been made in an attempt to address the above circumstances, to provide a semiconductor device of the conventional and improved the amount of information in the same package area efficiently advanced capable of performing input and output, or conventional to provide a semiconductor device having the same function in a smaller packaging area, and its purpose.

【0009】 [0009]

【課題を解決するための手段】すなわち本発明の半導体装置は、所要の配線群が形成されたベース基材上に、複数個の半導体素子が多段に重ね合わされて実装され、前記複数個の半導体素子の実装部が絶縁性樹脂により被覆され封止されて成ることを、その特徴としている。 The semiconductor device SUMMARY OF THE INVENTION Namely, the present invention is, on the required base substrate wiring group is formed, a plurality of semiconductor elements are mounted superimposed in multiple stages, the plurality of semiconductor that mounting of the device is made sealed is coated with an insulating resin, and its features.

【0010】本発明の半導体装置は、前記複数個の半導体素子が、大きさの順に多段に重ね合わされ、かつ前記複数個の半導体素子のうちで最大面積のものが前記ベース基材表面に接して実装されていることを、さらなる特徴としている。 [0010] The semiconductor device of the present invention, the plurality of semiconductor elements are superimposed in multiple stages in order of magnitude, and the largest area among the plurality of semiconductor elements in contact with the base substrate surface that it is implemented, and further characterized.

【0011】本発明においてベース基材としては、従来の半導体装置において使用可能であるたとえば樹脂基板、セラミック基板、あるいは金属基板などが同様に使用可能である。 [0011] As the base material in the present invention can be used, for example, a resin substrate in the conventional semiconductor device, such as a ceramic substrate or a metal substrate, can be used as well. また、半導体素子の実装部を被覆し封止する絶縁性樹脂としても、従来の半導体装置において使用可能であるたとえばエポキシ樹脂などが使用可能である。 Moreover, as also the insulating resin that seals covering the mounting portion of the semiconductor device can be used such as epoxy resin can be used in the conventional semiconductor device.

【0012】本発明において、半導体素子を重ね合わせる段数には、パッケージ高さが許容範囲内にある限りではとくに上限はない。 [0012] In the present invention, the number of overlapping the semiconductor elements, no particular upper limit as far as package height is within an acceptable range. また、薄いウエハを用いるようにすれば、パッケージ高さを従来の高さの範囲内に納めることも容易である。 Further, the joint use of such a thin wafer, it is easy to pay package height within the conventional height. あるいはベース基材としてキャビティ構造を有する基板も良好に使用可能であるので、本発明の半導体装置は、メイン基板へソケット挿入とすることも可能である。 Alternatively since the substrate having the cavity structure as a base material is good usable, the semiconductor device of the present invention, it is also possible to socket inserted into the main board. また、メイン基板に接続するための外部接続子としては、たとえばはんだボールや挿入ピンなどを用いることができる。 Further, as the external connectors for connection to the main board, for example, it can be used as the solder balls and the insertion pin.

【0013】本発明の半導体装置は、従来の半導体装置の製造工程の繰返しによって容易に製造することが可能であり、特別な製造装置を必要としないので従来の製造装置を使用することもできる。 [0013] The semiconductor device of the present invention can be readily prepared by repeating the process of manufacturing the conventional semiconductor device, it is also possible to use a conventional manufacturing device does not require special manufacturing equipment.

【0014】本発明の半導体装置の製造に際しては、まず従来装置と同様にベース基材の少なくとも一主面に信号線やインナーリード群などの配線群を常法にしたがって形成し、必要に応じてこれらの配線群を他主面に導出するための導通孔を、やはり常法にしたがって形成する。 [0014] When manufacturing the semiconductor device of the present invention, first the prior art device and the wiring group, such as signal lines and the inner lead groups on at least one major surface of the base material similarly formed in a conventional manner, if necessary the through hole for deriving these wiring groups other main surface, also formed in a conventional manner. 次いで、搭載すべき半導体素子の中で一番面積の大きいものをベース基材の所定の位置に配置し、エポキシ樹脂系などの絶縁性接着剤により接着固定(ダイボンド)し、その上に二番目に大きいものを重ねて同様に接着固定し、所要の段数に達するまでこの操作を繰返す。 Then, the larger of the most area in the semiconductor device to be mounted in place of the base material, an insulating adhesive such as epoxy resin is bonded and fixed (die bonding), the second on the bonded and fixed similarly overlaid things large, and this operation is repeated until the required number of stages.

【0015】そのようにして半導体素子を重ね合わせてベース基材に搭載した後、最下段に位置する最大面積の半導体素子の電極端子を、ベース基材に形成された配線群の所定の位置に、金線などのボンディングワイヤを用いて接続する。 [0015] After mounting the base member by its manner overlapping the semiconductor element, the electrode terminals of the semiconductor element with the largest area which is located at the bottom, at a predetermined position of the wiring group formed on the base substrate , connected using bonding wires such as gold wires. 次いで、下から2段目に位置する二番目に大きい半導体素子の電極端子を、同様にベース基材上の配線群の所定の位置に接続する。 Then, the electrode terminals of the semiconductor device the second largest, located at the second stage from the bottom is similarly connected to a predetermined position of the wiring group on the base substrate.

【0016】すべての半導体素子の電極端子が、ベース基材に形成された配線群の所定の位置にワイヤボンディングされた後、半導体素子とボンディングワイヤとそれらの接合部を被覆し封止する樹脂封止層を形成する。 The electrode terminals of all of the semiconductor elements after being wire-bonded to a predetermined position of the wiring group formed on the base substrate, a resin sealing that seals covering the semiconductor element and bonding wires and their joints to form a sealing layer. その後、ベース基材裏面にはんだボールを格子状に配列してバンプを形成するなどして外部接続端子を設けて、本発明の半導体装置が得られる。 Then, by arranging solder balls on the back base material in a lattice shape provided with external connection terminals, such as by forming bumps, the semiconductor device of the present invention is obtained.

【0017】本発明においては、複数個の半導体素子が、大きさの順に多段に重ね合わされ、かつそれらのうちで最大面積のものがベース基材表面に接して搭載された構造であるので、製造にあたっては、すべての半導体素子を搭載したのちまとめてワイヤボンディングを行うことができる。 In the present invention, a plurality of semiconductor elements are superimposed in multiple stages in order of magnitude, and so the largest area among them are mounted on a structure in contact with the base substrate surface, producing in the wire bonding can be performed collectively after mounting all the semiconductor elements.

【0018】 [0018]

【発明の実施の形態】以下、本発明の実施例を図面に基づいて説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be explained based on the embodiment of the present invention with reference to the drawings.

【0019】実施例1 図1にその断面の概略を示すように、ベース基材の一方の表面に、銅箔のフォトパターニングで所要の配線群(図示されていない)を予め形成し、それらの配線群をベース基材の裏面に導出するための複数の孔(図示されていない)を、形成した。 As shown schematically in cross section in Embodiment 1 Figure 1, on one surface of the base material, a required wiring group in photo-patterning of the copper foil (not shown) formed in advance, their a plurality of holes for the wiring group derived to the back surface of the base substrate (not shown) to form. そして、このようにして準備されたベース基材1の表面上の所定の位置に半導体素子2を配置し、エポキシ樹脂系接着剤により接着固定した。 Then, in this way the semiconductor element 2 is disposed at a predetermined position on the prepared surface of the base material 1, and adhered and fixed by an epoxy resin adhesive. そして、半導体素子2の上に、半導体素子2よりも面積の小さい半導体素子3を重ねて同様に接着固定した。 Then, on the semiconductor element 2 and bonded and fixed in the same manner overlapping a small semiconductor element 3 in area than the semiconductor element 2.

【0020】その後、半導体素子2の電極端子を、ベース基材1に形成された配線群の所定の位置に、ボンディングワイヤ4を用い常法にしたがって接続した。 [0020] Thereafter, the electrode terminals of the semiconductor element 2, a predetermined position of the wiring group formed on the base substrate 1, and connected in a conventional manner using the bonding wires 4. 次いで、半導体素子3の電極端子を、同様にベース基材上の配線群の所定の位置にボンディングワイヤ5を用いて常法にしたがって接続した。 Then, the electrode terminals of the semiconductor element 3, and connected in a conventional manner using a bonding wire 5 to a predetermined position of the wiring group on the base substrate as well.

【0021】ワイヤボンディング完了後、半導体素子2、3とボンディングワイヤ4、5とそれらの接合部を被覆し封止する樹脂封止層6を、常法にしたがいエポキシ樹脂を用いてトランスファーモールドにより形成した。 [0021] After forming the wire bonding completed, the resin sealing layer 6 which seals covering their junction with the semiconductor elements 2, 3 and the bonding wires 4, 5, by a transfer molding with an epoxy resin by a conventional method did. その後、ベース基材1の裏面に、はんだボール7を格子状に取り付けてバンプを形成して、外部接続端子とした。 Thereafter, the back surface of the base substrate 1, to form a bump by attaching the solder balls 7 in a lattice shape, and the external connection terminal.

【0022】このようにして得られた本発明の半導体装置は、半導体素子2の占めるパッケージ面積と同面積で、半導体素子3の情報量も加わった高機能のものであった。 The semiconductor device of the present invention obtained in this way is the same area as the package area occupied by the semiconductor element 2, it was of high function applied amount of information of the semiconductor element 3. 実施例2 ベース基材として、図2にその断面の概略を示すキャビティ構造のベース基材10を用いた他は実施例1と同様にして、本発明の半導体装置を作製した。 As Example 2 base material, except for using the base substrate 10 of the cavity structure showing the outline of the cross section in FIG. 2 in the same manner as in Example 1 to prepare a semiconductor device of the present invention. 実施例1と同様に半導体素子2の占めるパッケージ面積と同面積で、 In package area and the area occupied Similarly the semiconductor element 2 as in Example 1,
半導体素子3の情報量も加わった高機能のものが得られた。 Those information amount of the semiconductor element 3 is also applied high performance was obtained.

【0023】なお以上の実施例は半導体素子の2段の重ね合わせに関するものであるが、本発明は、上記2段の重ね合わせに限定されるものではない。 [0023] Note that above examples relate to the superposition of the two stages of the semiconductor device, but the present invention is not limited to the superposition of the two stages. また外部接続端子としてはんだボールを使用しているが本発明はこれに限定されるものではない。 Also using solder balls as external connection terminals but the present invention is not limited thereto.

【0024】比較例 図3は、実施例1、2の半導体装置で用いられたものと同様の半導体素子2を用いて得られた従来の樹脂封止型の半導体装置の断面の概略図である。 [0024] Comparative Example FIG 3 is a schematic cross-sectional view of a semiconductor device of a conventional resin sealed obtained using the same semiconductor element 2 and those used in the semiconductor device of Examples 1 and 2 . 図1、2と共通する部分には同じ符号が付してある。 The portions similar to FIGS are denoted by the same reference numerals.

【0025】この半導体装置は、実施例1、2とほぼ同じパッケージサイズであるが、実施例1、2に比較して半導体素子3の情報量を含まない分だけ機能が劣るものであった。 [0025] The semiconductor device is substantially the same package size as in Example 1, was achieved only function is poor amount that does not include the information of the semiconductor device 3 as compared with Examples 1 and 2.

【0026】 [0026]

【発明の効果】以上説明したように、本発明によれば、 As described in the foregoing, according to the present invention,
従来と同じパッケージ面積で効率よく入出力を行い得る高機能の半導体装置、あるいは従来より小さいパッケージ面積で同等の機能を有する半導体装置を、特殊な装置や工程を必要とせずに提供し得る。 The semiconductor device of the conventional and high-performance capable of performing efficiently input the same package area, or a semiconductor device having the same function in a small package area than conventional, may provide without requiring special equipment or processes.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】実施例1の半導体装置の構造を説明するための断面概略図である。 1 is a cross-sectional schematic view illustrating the structure of a semiconductor device of Example 1.

【図2】実施例2の半導体装置の構造を説明するための断面概略図である。 2 is a sectional schematic view for explaining the structure of a semiconductor device of Example 2.

【図3】比較例の半導体装置の構造を説明するための断面概略図である。 3 is a cross-sectional schematic view illustrating the structure of a semiconductor device of the comparative example.

【符号の説明】 1……ベース基材 2、3……半導体素子 4、5……ボンディングワイヤ 6……樹脂封止層 7……はんだボール 10……キャビティ構造のベース基材 [Description of Reference Numerals] 1 ...... base substrate 2 ...... semiconductor elements 4, 5 ...... bonding wires 6 ...... resin sealing layer 7 ...... solder balls 10 ...... base material of the cavity structure

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 所要の配線群が形成されたベース基材上に、複数個の半導体素子が多段に重ね合わされて実装され、前記複数個の半導体素子の実装部が絶縁性樹脂により被覆され封止されて成ることを特徴とする半導体装置。 To 1. A on desired base substrate wiring group is formed, a plurality of semiconductor elements are mounted superimposed in multiple stages, the mounting portion of the plurality of semiconductor elements are covered with an insulating resin sealing the semiconductor device characterized by comprising locked.
  2. 【請求項2】 前記複数個の半導体素子が大きさの順に多段に重ね合わされ、かつ前記複数個の半導体素子のうちで最大面積のものが前記ベース基材表面に接して実装されていることを特徴とする請求項1記載の半導体装置。 Wherein said plurality of semiconductor elements are superimposed in multiple stages in order of magnitude, and that the largest area among the plurality of semiconductor elements are mounted in contact with the base substrate surface the semiconductor device according to claim 1, wherein.
JP7959798A 1998-03-26 1998-03-26 Semiconductor device Pending JPH11274397A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151644A (en) * 2000-09-04 2002-05-24 Fujitsu Ltd Laminated semiconductor device and manufacturing method thereof
KR100631910B1 (en) 1999-12-13 2006-10-04 삼성전자주식회사 Multi-chip package using same chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100631910B1 (en) 1999-12-13 2006-10-04 삼성전자주식회사 Multi-chip package using same chip
JP2002151644A (en) * 2000-09-04 2002-05-24 Fujitsu Ltd Laminated semiconductor device and manufacturing method thereof
JP4570809B2 (en) * 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 The stacked semiconductor device and a manufacturing method thereof

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