JPH11274097A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming stable crystalline on the phosphorus- doped amorphous silicon surface in a manufacture of a semiconductor device such as a DRAM, in particular a method for forming an HSG-Si electrode for a semiconductor device. SOLUTION: When a substrate has an amorphous silicon layer to which an impurity is added, this manufacturer of a semiconductor device has a process of removing a natural oxide film on the surface of the amorphous silicon layer, a process of applying heat treatment to the substrate, a process of exposing the substrate to a silicon compound gas under a certain partial pressure, and a process of applying heat treatment to the substrate in a non-oxidizing gas atmosphere. At this time, prior to the process of removing a natural oxide film from the amorphous silicon layer surface, this manufacturing method, for a semiconductor device has a process of dipping the substrate in pure water.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an electrode of a semiconductor device such as a DRAM.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices such as DRAMs have become highly integrated, the cell size has been reduced, and the area of a portion for forming a capacitor has also been reduced. Therefore, in order to secure a sufficient capacitance, a stacked capacitor or the like having a large capacitance portion area has been used.

However, the degree of integration of a semiconductor device is 64 Mbi.
With the increase of t and 256 Mbit, the cell area is further reduced, and even if these structures are used, it is required to further reduce the thickness of the capacitance insulating film. Currently practically, SiO
₂ / Si ₃ N ₄ etc. are used as capacitor insulating films, but the limit of thinning of these insulating films is about 4 nm. Difficult to do.

As means for solving this, Japanese Patent Laid-Open No. 3-2
No. 72165 discloses LPCVD (Low Pres).
sure Chemical Vapor Depos
In the deposition of a silicon film using an ition method, a method of obtaining hemispherical crystal grains (hereinafter, referred to as “grain”) near a temperature at which the crystalline state of the silicon film changes from amorphous to polycrystalline is described. ing. By applying this grain to the electrode, the unevenness can be formed on the surface of the electrode, and the amount of charge stored in the electrode can be greatly increased. However, according to the publication, the irregularities caused by the grains can be grown only in a specific temperature range. Further, there remains a problem that it is difficult to control the grain size and the like.

Japanese Patent Application Laid-Open No. 5-304273 discloses that disilane gas (Si ₂
By irradiating H ₆ gas), first forming a microcrystalline nucleus, after which, depositing a silicon atom to migrate amorphous silicon surface microcrystalline nuclei, describes a method of growing mushroom-like grains I have. With this method,
A uniform grain having a controlled density can be formed on the electrode surface, and the problem of difficulty in controlling the grain size can be solved.

Also, in 1992, “Solid Sta
te Devices and Materials "
On page 422 of "Hemispherical Gr."
ained Silicon (hereinafter "HSG-Si")
That. ) Formation on in-sit
u Phosphorous Doped Amorp
house-Si Using the Seeing
The title of "Method" describes that grains with controlled grain size and density can be formed on an amorphous silicon electrode to which phosphorus is added. This method
There is an advantage in that it is not necessary to perform an impurity addition process that causes grain deformation such as ion implantation after forming irregularities on the amorphous silicon surface.

Further, “International
Electron Devices Meeting, page 259, states "A New Cylindal Ca."
capacitor Using Hemispheric
al Grained Si (HSG-Si) for
Entitled "256 Mb DRAMs", it is described that irregularities due to microcrystals can be formed even on electrodes having a cylinder structure. By using this technology for forming electrodes, a 256 Mbit DRAM can be manufactured. From the above, the technique described in Japanese Patent Laid-Open No. 5-304273 is a very effective method for forming electrodes of a highly integrated semiconductor memory.

However, when the above method is used, there is a problem that irregularities cannot be formed on amorphous silicon having a phosphorus concentration exceeding 5 × 10 ²⁰ atoms / cm ³ .
This is because phosphorus atoms on the surface of the film hinder the formation of unevenness. In addition, since the formation of the irregularities proceeds by supplying silicon atoms from the amorphous silicon, there is also a problem that when the side wall of the cylinder electrode or the like is thin, individual grains cannot be grown sufficiently.

[0009]

On the other hand, JP-A-8-30
No. 6646 discloses that amorphous silicon not doped with phosphorus or doped with impurities is irradiated with silane gas at 1 × 10 ⁻³ Torr or less to grow amorphous silicon selectively, and annealing is continuously performed. A method is described in which microcrystals are grown on amorphous silicon to form irregularities on the electrode surface.

FIG. 11 shows a flowchart of the process of forming the HSG-Si described in Japanese Patent Application Laid-Open No. 8-306646. That is, after the lower electrode is formed (Step 1), the electrode surface is washed with a mixed solution of ammonia, hydrogen peroxide solution and pure water (Step 2), and the solution is added to an aqueous solution of HF / H ₂ O = 1/30.
The native oxide film on the surface is removed by immersing the electrode for 0 second (Step 4), the wafer is dried (Step 5), and then HSG
-Si is formed (Step 6).

In the step 5, by selectively growing amorphous silicon, the number of silicon atoms supplied to the electrode surface is increased, and spherical or hemispherical grains are formed stably. . This method can be applied to the formation of a capacitor electrode of a semiconductor device such as a DRAM, and the amount of accumulated electric charge of the electrode can be greatly reduced by forming grains on the electrode by applying grains to the electrode. Can be increased.

However, when the conventional method is used as it is, as shown in FIG. 12, if the irradiation time of the silane gas is long, the phosphorus-doped amorphous silicon is locally crystallized. Therefore, when annealing continuously, silicon atoms cannot migrate only at that portion,
Since microcrystals cannot be formed, irregularities cannot be formed on a part of the electrode surface. On the other hand, when the irradiation time of the silane gas is reduced, the density of microcrystals formed on the phosphorus-doped amorphous silicon decreases, and as a result, the density of irregularities formed on the electrode decreases. Improvement cannot be achieved.

FIG. 12 shows a density of 3 × 10 ^{20 at.}
Irradiation of silane gas is performed when amorphous silicon containing phosphorus at ms / cm ³ and 5 × 10 ²⁰ atoms / cm ³ is irradiated with silane gas for a given period of time, respectively, and then annealed in a nitrogen gas atmosphere for 40 minutes. FIG. 4 is a diagram showing a relationship between time and a capacity increase rate of an electrode. The vertical axis represents the capacity increase rate, and the horizontal axis represents the irradiation time.

In the above conventional method, it is difficult to stably form microcrystals on the surface of phosphorus-doped amorphous silicon. To form microcrystals stably on the surface of phosphorus-doped amorphous silicon, it is necessary to use a silicon compound gas. It is necessary to finely control the irradiation amount and irradiation time. Therefore, development of a method for more stably and efficiently forming microcrystals on the surface of phosphorus-doped amorphous silicon is demanded.

The present invention has been made in view of the above circumstances, and in a method of forming an electrode of a semiconductor device, particularly, in a method of forming an electrode of a semiconductor device, a microcrystal is stably formed on a surface of a phosphorus-doped amorphous silicon. It is intended to provide a method of forming.

[0016]

In order to solve the above-mentioned problems, the present invention comprises a step of removing a natural oxide film on the surface of an amorphous silicon layer of a substrate having an amorphous silicon layer to which impurities are added; A step of heat-treating the substrate; a step of exposing the substrate to a silicon compound gas at a predetermined partial pressure; and a step of heat-treating the substrate in a non-oxidizing gas atmosphere. A method of manufacturing a semiconductor device, comprising a step of immersing the substrate in pure water before a step of removing a natural oxide film on a surface of an amorphous silicon layer.

In the method of manufacturing a semiconductor device according to the present invention, the temperature of the pure water is 50 ° C. or higher, more preferably,
It is preferably warm pure water at 50 to 80 ° C.

In the present invention, the impurity is preferably a phosphorus compound or an arsenic compound. The concentration of the impurity is 1 × 10 ¹⁸ to 1 × 10 ²² atoms / cm ^3.
The degree is preferred.

In the present invention, the step of heat-treating the substrate preferably includes the step of heating the substrate in a vacuum (eg, 1 ×).
About 10 ^-8 Torr), or argon, helium, a step of heat-treating the substrate in an inert gas such as nitrogen gas. The heat treatment temperature is usually 400 to 700 ° C.
Degree, preferably around 550 ° C.

In the present invention, the step of exposing the substrate to the silicon compound gas at the predetermined partial pressure is preferably a step of irradiating the substrate with the silicon compound gas at a partial pressure value of 1 × 10 ⁻³ Torr or less. is there.

Further, the silicon compound gas is preferably a silane gas or a disilane gas. Further, the silicon compound gas may be diluted with an inert gas such as argon, nitrogen, and helium.

In the present invention, as a method for stably forming microcrystals on the surface of the phosphorus-doped amorphous silicon, the surface of the phosphorus-doped amorphous silicon is treated with warm pure water to adjust the phosphorus concentration on the surface of the phosphorus-doped amorphous silicon in advance. The point is to keep it low.

Conventionally, as described in the above-mentioned JP-A-8-306646, the phosphorus concentration on the surface of phosphorus-doped amorphous silicon is controlled by irradiating silane gas while controlling the irradiation amount and irradiation time to add impurities. This has been done by forming amorphous silicon on the outermost surface. However, for the reasons described above, there is a problem that irregularities cannot be formed on a part of the electrode surface, or a decrease in the density of microcrystals formed on the phosphorus-doped amorphous silicon causes the irregularities formed on the electrode to be reduced. There are problems such as a decrease in density and an improvement in the amount of accumulated charge, and it has been difficult to stably form microcrystals.

According to the present invention, the phosphorus concentration on the phosphorus-doped amorphous silicon surface is reduced by treating the surface of the phosphorus-doped amorphous silicon with pure water, preferably with warm pure water having a temperature of 50 ° C. or higher. Later, Japanese Patent Application Laid-Open No. 8-3
By using the electrode forming technique described in Japanese Patent No. 06646, irregularities (HSG-Si) can be more easily, efficiently and stably formed on the electrode surface. Therefore,
The amount of charge stored in the electrodes of a semiconductor device such as a DRAM or SRAM can be stabilized, and the yield and reliability can be improved.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail. FIG. 1 shows a general-purpose DRAM (Dynamic Ra) manufactured by the semiconductor manufacturing method of the present invention.
FIG. 2 is a cross-sectional view of FIG. In general-purpose DRAMs of 256 Mbit or later, a stack capacitor having a structure called a fin or a cylinder is used from a simple stack structure to obtain a capacitor area. In FIG. 1, for example, 105 is a lower electrode,
Reference numeral 106 denotes a dielectric film, and 107 denotes an upper electrode. The present invention can be applied particularly as a method for forming the lower electrode 105.

FIG. 2 shows a flowchart of the manufacturing process of the present invention. FIG. 2 shows the semiconductor manufacturing process, in particular, D
4 is a flowchart of a process of forming an electrode of a semiconductor device such as a RAM. This step includes the following six steps. That is, (Step 1) Impurities such as phosphorus and arsenic are reduced to 1 × 10 ^{20 to} 5 ×
Forming a lower electrode 1 made of amorphous silicon doped at about 10 ²⁰ atoms / cm ³ by photolithography and dry etching;

(Step 2) A step of removing contamination on the wafer surface by cleaning the wafer with a mixed solution of ammonia, hydrogen peroxide and pure water.

(Step 3) Purify the wafer with pure water, preferably 5
A step of immersing in warm pure water of 0 ° C. or more for 5 to 20 minutes.

In this step, the wafer is treated with pure water, preferably hot pure water at a temperature of 50 ° C. or higher, to elute impurities such as phosphorus and arsenic on the surface of the electrode to remove amorphous silicon to which phosphorus or arsenic is added. It reduces the concentration of phosphorus or arsenic near the surface of the layer. By reducing the concentration of phosphorus or arsenic near the surface of the amorphous silicon layer, microcrystals can be stably formed on the surface of the amorphous silicon layer.

The pure water used in the present invention has no reactivity with silicon. The pure water is preferably of high specific resistance having been deionized and having fine particles which are not dissolved in water removed by a filter. It is also necessary to remove bacteria. The quality of such pure water is generally 14-18 at room temperature.
It has a specific resistance of MΩ · cm, has fine particles of 0.2 to 0.45 μ or more removed, and has a bacterial content of 0%.
It is preferably 10 to 10 particles / cm ³ .

The temperature of pure water is preferably 50 ° C. or higher. If the temperature of the pure water is lower than 50 ° C., the elution of phosphorus and arsenic is insufficient, and the effect of the present invention is not sufficiently exhibited.

(Step 4) H at an HF / H ₂ O ratio of 1/30
A step of immersing in an F (hydrogen fluoride) aqueous solution for 1 to 10 minutes to remove a natural oxide film on the surface of the lower electrode.

(Step 5) A step of drying the wafer.

(Step 6) A step of forming HSG-Si.
This step is performed, for example, by LPCVD (Low Press).
ure Chemical Vapor Depos
Ition) method, 20 to 100 SCCM (cc /
min) of the silicon compound gas, preferably at a pressure of 1 × 10
^-3 Torr or less, 1 minute to 60 minutes, 400 to wafer
Irradiation at 800 ° C. forms HSG-Si. Here, when the partial pressure value exceeds 1 × 10 ⁻³ Torr, SiH ₄ is clustered in the gas phase, and it is not preferable because the selectivity between amorphous Si and SiO ₂ or SiN cannot be maintained.

The step of forming the HSG-Si is performed on the surface of the lower electrode made of amorphous silicon containing impurities.
By irradiating a silicon compound gas such as silane or disilane at a predetermined pressure, a microcrystalline nucleus of silicon is formed on the electrode surface, and then annealed under a non-oxidizing atmosphere, preferably under a high vacuum, Unevenness on the electrode surface (HSG-S
i).

FIG. 3 shows the HSG using disilane gas.
The explanatory view of the growth mechanism of -Si is shown. First, silicon microcrystal nuclei are grown on the amorphous silicon film A by irradiating a disilane gas. Thereafter, by performing annealing in a high vacuum, hydrogen atoms terminated on the film surface are desorbed, and silicon atoms on the film surface can migrate. The migrated silicon atoms gather in microcrystal nuclei grown by irradiation with disilane gas, and hemispherical grains are formed. The reason why the grains become hemispherical is that the grains have a structure with the smallest surface energy and that silicon atoms migrate also on the microcrystal nuclei.

FIG. 4 shows a conceptual diagram of a growth mechanism in the case where HSG-Si is formed by irradiating silane gas onto amorphous silicon (hereinafter referred to as “PDAS”) B doped with phosphorus. The mechanism of HSG-Si growth can be considered in the same manner as in the case of annealing by irradiating the disilane gas shown in FIG.

Next, the present invention will be described in more detail with reference to embodiments of the present invention. First Embodiment The first embodiment is an example in which the present invention is applied to manufacture of a lower electrode of a DRAM. First, as shown in FIG.
A field oxide film 202 is selectively formed on a silicon semiconductor substrate 201 of a mold type, and a polysilicon gate 203 (also serves as a word line) of a transistor in a DRAM cell.
Are formed selectively. In the drawing, two DRAMs are used.
A gate 203 for a cell is formed via a gate insulating film 210, and an N-type impurity (phosphorus or arsenic) is selectively introduced into the semiconductor substrate 201 using the field oxide film 202 as a mask. Impurity regions 208 as source / drain regions are formed. Thereafter, a silicon oxide film or a silicon oxide film (such as a BPSG film) 204 containing boron and / or phosphorus is formed on the entire surface.

Next, as shown in FIG. 5B, a bit line contact hole 211 is formed in the insulating film 204 to expose a part of the common region 209 of the two cells. This contact hole 211 is made of polysilicon 2 containing impurities.
And a refractory metal silicide layer 213 such as tungsten silicide.
12 is formed. Thus, a bit line 214 is formed.

Next, as shown in FIG. 5C, an insulating film such as a silicon oxide film is deposited on the entire surface to form a thick insulating layer 21.
5 is formed, and the capacitor contact hole 216 is selectively formed. A phosphorus-doped amorphous silicon layer is formed on the entire surface of the insulating film 215 by filling the contact hole 216. After patterning by photolithography, an amorphous silicon electrode 217 for storage of the capacitor is formed by selective etching.

Thereafter, contamination of the wafer surface is removed by washing with a mixed solution of ammonia, hydrogen peroxide solution and pure water, and the wafer is immersed in hot pure water at 60 ° C. for 10 minutes. As a result, impurities such as phosphorus and arsenic on the electrode surface are eluted to lower the concentration of phosphorus or arsenic near the surface of the amorphous silicon layer to which phosphorus or arsenic is added.

Subsequently, the wafer was subjected to an HF / H ₂ O ratio of 1/3.
The silicon oxide film is immersed in an aqueous solution for 30 seconds to remove the natural oxide film on the surface of the amorphous silicon electrode, thereby forming a silicon film region and a silicon oxide film region on the wafer surface.

Next, the wafer is introduced into a vertical LPCVD furnace heated to 530 ° C. Since this device has a vacuum load lock mechanism, it can be introduced into the reaction chamber without oxidizing the surface of the silicon electrode. The ultimate vacuum of the reaction chamber is 1 × 10 ⁻⁸ Torr.
After holding the wafer for 30 minutes in this chamber until the wafer temperature is stabilized, 50 SCCM (cc / mi
n) silane gas (20% helium dilution)
Irradiation is performed at 06 Torr for 45 minutes, and vacuum annealing is continuously performed in the chamber at a pressure of 1 × 10 ⁻⁸ Torr for 40 minutes. By performing the above operation, as shown in FIG. 6 (d), HSGs having irregularities formed on the surface of the electrode 218 by grain growth of hemispherical or spherical silicon on the surface.
-Si can be formed.

Next, as shown in FIG. 6E, a heat treatment is performed in a nitrogen gas atmosphere to
A dielectric film 219 including a thermal silicon nitride film is formed thereon. By the heat treatment at this time, phosphorus diffuses from inside into silicon grains on the surface of each electrode 218. In addition, polycrystallization of the silicon electrode 218 proceeds. Then, a cell plate electrode layer 220 is formed by depositing phosphorus-doped polycrystalline or amorphous silicon. Thereafter, the DRAM can be manufactured by a known post-process.

The cell plate electrode layer formed as described above is made of a polycrystalline silicon film having a large grain on the electrode surface and a small grain boundary (crystal grain boundary), and the charge storage capacity is greatly increased. I have.

Second Embodiment A second embodiment is directed to a DRAM having cylindrical electrodes.
This is an example in which the present invention is applied. First, after a capacitor contact hole 311 is formed in the insulating film 315, a phosphorus-doped amorphous silicon layer is deposited on the insulating film 315 while filling the contact hole 311, and further an insulating film such as a silicon oxide film is formed. Perform patterning.
As a result, as shown in FIG. 7A, each capacitor contact hole 311 is buried, and the insulating film 32 is formed thereon.
An amorphous silicon layer having 1 is formed.

Thereafter, a phosphorus-doped amorphous silicon layer is deposited on the entire surface, and etch back is performed until the upper surface of the insulating film 321 is exposed. Then, by removing the insulating film 321, a cylindrical amorphous silicon layer 317 of each capacitor is formed as shown in FIG. 7B.

Thereafter, as in the first embodiment, the surface of each silicon layer 317 is cleaned, a relatively thick non-doped amorphous silicon is deposited by irradiation with silane gas, and annealing is performed in an inert gas. As a result, a cylindrical silicon electrode 318 having an uneven surface is formed.

Next, a dielectric film 319 is formed, and a cell plate electrode layer 320 is formed thereon. As described above, a DRAM having a large capacitance value with a small occupation area can be manufactured.

Third Embodiment In a third embodiment, a method of manufacturing a semiconductor device according to the present invention
AM (StaticRandom Access Me)
An example is shown in which the present invention is applied to a load transistor of the same type.
8 to 10 show sectional views of the process.

First, the element isolation film 402 is formed in the element isolation region on the surface of the P-type silicon substrate 401 by selective oxidation using the LOCOS method. Next, 8
Thermal oxidation is performed at 50 ° C. to form a gate oxide film 410.
Next, a contact hole 411 is formed in a predetermined position of the gate oxide film 410 using a resist mask by a wet etching method using buffered hydrofluoric acid or the like. The reason why these contact holes can be formed by wet etching is that there is no problem even if the diameter of these contact holes is slightly increased by a slight over-etching.

Next, the entire surface is formed by an LPCVD method.
Situ P (phosphorus) -doped silicon film is 620
C. to form an N-type polycrystalline silicon film. Subsequently, a tungsten silicide film is deposited by a sputtering method. Next, these laminated films are patterned by dry etching using a resist as a mask to form a gate electrode 403. Gate electrode 403
Are connected to the surface of the P-type silicon substrate 401 via the contact holes 411, respectively. At this time, for example, the gate electrode 403 in the contact hole 411
The overlap margin between the tip of the gate oxide film 410 and the tip of this is about 0.1 μm.

Then, arsenic ions are implanted using the field oxide film 402 and the gate electrode 403 as masks,
An N-type diffusion layer 408 is formed on the surface of a P-type silicon substrate 401. The impurity concentration of this N-type diffusion layer 408 is 10 ²⁰
FIG. 8A is a cross-sectional view of the state at this time, with the concentration being about 10 to ²¹ atoms / cm ³ .

Next, a silicon oxide film 404 as an interlayer insulating film is formed on the entire surface by LPCVD. Next, a ground contact hole reaching an N-type diffusion layer (not shown) is opened in the interlayer insulating film using a resist mask, and a tungsten silicide film is deposited on the entire surface by a sputtering method. Next, an opening is formed in a predetermined region of the tungsten silicide film, and a ground line 421 connected to the N-type diffusion layer through a ground contact hole is formed.

Thereafter, an interlayer insulating film 415 made of silicon oxide having a flat surface is deposited on the entire surface by LPCVD. FIG. 8B is a sectional view showing the state at this time.

Next, as shown in FIG. 8C, the gate electrodes 40 penetrate through the interlayer insulating films 404 and 415, respectively.
A contact hole 422 reaching 3 is formed. This contact hole can be opened by dry etching using a resist (not shown) as a mask.

Subsequently, a polycrystalline silicon film is formed on the entire surface by the LPCVD method, and 10 ¹⁶ to 10
Arsenic, which is an N-type impurity at ¹⁹ atoms / cm ³ , is doped. However, in this case, the impurities may be P-type impurities. Next, the obtained polycrystalline silicon film is patterned by dry etching using a resist as a mask to form a gate electrode 423. A state sectional view at this time is shown in FIG.

Next, these gate electrodes 423 are respectively connected to the gate electrodes 403 via the contact holes 422. Next, a gate insulating film 426 made of a silicon oxide film is formed on the entire surface by LPCVD. The film formation at this time can be performed, for example, at 800 ° C. in an atmosphere in which a silane gas and a N ₂ O gas are mixed. Since a film deposited in this atmosphere has excellent step coverage, a silicon oxide film is used as a gate insulating film in this embodiment, but a stacked film of an oxide film and a nitride film (a so-called ONO film) may be used.

Next, a contact hole 424 is formed in the gate electrode 423 by anisotropic dry etching of the gate insulating film 426 using a photoresist film (not shown) having an opening substantially at the position of the contact hole 422 as a mask. This anisotropic dry etching is preferably performed slightly over-etching. This is because, for example, the gate electrode 42 covering the side wall portion of the contact hole 422
This is to prevent the gate insulating film 426 from remaining as a sidewall spacer on the surface of the substrate 3 as much as possible.

It should be noted that isotropic etching is not preferable as the etching for forming these contact holes 422. If these contact holes are formed by isotropic etching, portions of these contact holes protruding from the gate electrode and the like due to over-etching will interfere with the etching of the polycrystalline silicon film performed in a later step. It is.

As a material forming the gate electrode 423, a polycrystalline silicon film is preferable. If these gate electrodes 423 are formed of a silicide film, a polycide film, a high-melting-point metal film, or the like, there is a portion where the gate insulating film 426 is in direct contact with these, and the reliability of the gate insulating film is reduced. I do.

Next, after the photoresist film is removed by ashing, acid cleaning is performed. Next, the entire surface of the gate electrode 423 is immersed in hot pure water at 70 ° C. for 10 minutes to reduce the arsenic content on the gate electrode surface.
By this operation, when HSG-Si is formed in a later step,
Microcrystals can be formed stably.

Thereafter, the surface of the gate insulating film 426 is cleaned with hydrofluoric acid in order to remove the gate insulating film 426 and the natural oxide film which are not removed from the surface of the gate electrode 423 covering the side wall of the contact hole 422. . Subsequently, an amorphous silicon film is formed at 550 ° C. over the entire surface by the LPCVD method. The deposition of the amorphous silicon film can be performed, for example, using a high-vacuum CVD apparatus having an ultimate vacuum of 1 × 10 ⁻⁸ Torr. This film formation is performed by introducing a silane (diluted with 20% He) gas at a flow rate of 200 cc / min into the chamber, and setting the flow rate to 1 at 0.1 Torr.
This is done by depositing a 5 nm film. Through the above processing, an amorphous silicon film having unevenness on the surface is formed over the oxide film 426.

Next, by patterning the obtained polycrystalline silicon film, a polycrystalline silicon film pattern 4 is formed.
25, and these polycrystalline silicon film patterns 42 are formed.
5 are connected to the gate electrode 423 via the contact holes 424, respectively. FIG. 9 (e) shows a sectional view of the state obtained by the above-mentioned operations.

Next, the polycrystalline silicon film pattern 425 covering at least the gate electrode 423 and the gate electrode 4
Boron ions are implanted using the photoresist film 427 covering the portion of the polysilicon film pattern 425 covering the portion 23 as a mask. Thus, a P-type diffusion region 429 is formed in the polycrystalline silicon film pattern 425,
The channel region is left. The impurity concentration of the P-type diffusion region 429 is approximately 10 ¹⁸ to 10 ²⁰ atoms / cm ³ . In particular, a P-type diffusion region 42 which is a P-type drain region
When the impurity concentration of No. 9 is 10 ²¹ atoms / cm ³ or more, the leak current of the load P-channel TFT containing these impurities increases. Therefore, control of the impurity concentration is important. FIG. 10F shows a sectional view of the device at this time.

Next, after the photoresist film 427 is removed, an interlayer insulating film 430 having a flat surface is formed on the entire surface, and the bit contact hole 431 reaching the N-type diffusion layer 429 is dried using a resist (not shown) as a mask. Open holes by etching. Subsequently, the N-type diffusion layer 4
A pair of bit lines 432 connected to 29 are formed.
FIG. 10 is a sectional view of the device obtained as described above.
(G).

Thereafter, the load transistor of the SRAM can be manufactured through a predetermined post-process according to a known method. Since the SRAM manufactured as described above has HSG-Si on its electrode, the SRAM has high charge storage capacity and high reliability.

Although the present invention has been described based on several embodiments, the present invention is not limited to the above embodiments, and the process conditions such as the temperature of hot pure water and the time for immersing a wafer in hot pure water are not limited. It can be appropriately selected without departing from the gist of the present invention.

As described above, the method of manufacturing a semiconductor device according to the present invention relates to the manufacture of a semiconductor device, and
As a method of forming a lower electrode of a semiconductor storage device such as a RAM,
Can be widely applied.

[0070]

As described above, the present invention relates to a method for manufacturing a semiconductor device, particularly, an HSG used for an electrode of a semiconductor device.
In the method of forming Si, the surface of the amorphous silicon doped with impurities such as phosphorus and arsenic is treated with pure water, preferably warm pure water, so that the impurity concentration on the amorphous silicon surface is reduced in advance. Microcrystals can be stably formed on the surface of the amorphous silicon.

Therefore, according to the method of manufacturing a semiconductor device of the present invention, the amount of charge stored in a capacitor of a semiconductor device such as a DRAM can be increased and stabilized, and a semiconductor device with improved yield and high reliability can be manufactured.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a DRAM manufactured according to the present invention.

FIG. 2 is a process chart of forming HSG-Si in the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 shows HSG-Si by disilane gas irradiation.
It is a conceptual diagram explaining a formation mechanism.

FIG. 4 is a conceptual diagram illustrating an HSG-Si formation mechanism by silane gas irradiation.

FIG. 5 is a state sectional view of a main step in a manufacturing process of the DRAM of the first embodiment; FIG. 2A is a diagram in which an element isolation region is formed on a substrate, a gate oxide film and a gate electrode are formed, and then an interlayer insulating film is formed.
(B) is a view in which a contact hole is opened from the state shown in (a) to form a bit line, and (c) is
FIG. 3B is a diagram showing that a storage-like amorphous silicon electrode is formed by depositing a silicon oxide film and then opening a contact hole from the state shown in FIG.

FIG. 6 is a state sectional view of a main step in a manufacturing process of the DRAM of the first embodiment; FIG.
FIG. 9C is a diagram in which HSG-Si is formed by cleaning the electrode surface from the state shown in FIG. 7C, treating with hot pure water, and performing annealing, and FIG. 9E shows the dielectric film 219 from the state shown in FIG. FIG. 4 is a diagram in which a cell plate electrode layer is formed.

FIG. 7 is a sectional view of a main step in a manufacturing process of a DRAM having a cylindrical electrode according to the second embodiment; FIG. 3A is a diagram in which an element isolation region is formed on a semiconductor substrate, a gate oxide film, a gate electrode, and a bit line are formed, and then an amorphous silicon layer having an insulating film formed thereon is formed. (B) is a diagram in which, from the state shown in (a), phosphorus-doped amorphous silicon is deposited, etched back, the insulating film is removed, and a cylindrical amorphous silicon electrode layer is formed. (C) is a view in which a dielectric film is formed from the state shown in (b) and a cell plate electrode layer is formed.

FIG. 8 is a state sectional view of a main step in a manufacturing process of the load transistor of the SRAM according to the third embodiment; (A) forming an element isolation region on a semiconductor substrate,
FIG. 3B is a diagram in which a gate insulating film, a gate electrode, and an N-type diffusion layer are formed, and FIG. 4B is a diagram in which an interlayer insulating film, a ground line, and a second interlayer insulating film are formed from the state shown in FIG. FIG. 4C is a diagram in which a contact hole is opened from the state shown in FIG.

FIG. 9 is a state sectional view of a main step in a manufacturing process of the load transistor of the SRAM according to the third embodiment; 8D is a diagram in which a gate electrode is formed from the state shown in FIG. 8C, and FIG. 8E is a diagram in which a gate insulating film is formed from the state shown in FIG. It is the figure formed.

FIG. 10 is a state sectional view of a main step in a manufacturing process of the load transistor of the SRAM according to the third embodiment; (F) is a diagram in which, after forming a resist film from the state shown in FIG. 9 (e), predetermined patterning is performed, and ion implantation of boron is performed to form an N-type diffusion layer. FIG. 4 is a diagram in which a resist film is removed from the state shown in FIG. 4F, an interlayer insulating film is formed, a bit contact hole is opened, and a bit line is formed.

FIG. 11 is a process diagram of a conventional HSG-Si formation.

FIG. 12 is a diagram showing a relationship between a silane gas irradiation time and a capacity increase rate of an electrode.

[Explanation of symbols]

101, 201, 301, 401 ... silicon semiconductor substrate, 102, 202, 302, 402 ... field oxide film, 103, 203, 303, 403, 423, 425
... gate electrode, 104, 404, 415, 430 ... interlayer insulating film, 105 ... lower electrode, 106, 219, 319 ...
Dielectric film, 107: upper electrode, 109, 209, 309
... common regions, 110, 210, 410, 426 ... gate insulating films, 204 ... BPSG films, 208, 308 ... impurity regions, 211, 216, 311, 408, 411, 42
2,424,428,431 ... contact hole, 21
2, 312: polysilicon layer, 213, 313: metal silicide layer, 214, 314, 432: bit line, 21
5,315,321 ... insulating film, 217, 318, 423
... Amorphous silicon electrode, 218,318 ... HSG-S
i, 220, 320 ... cell plate electrode layer, 317, B
... Amorphous silicon film doped with phosphorus, 408 ... N type diffusion layer, 421 ... ground line, 427 ... photoresist film,
425, 429: P-type diffusion layer, A: amorphous silicon film

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8242

Claims (7)

[Claims] A step of removing a natural oxide film on a surface of the substrate having an amorphous silicon layer to which impurities are added; a step of heating the substrate; and a step of heating the substrate by a predetermined partial pressure. A method of manufacturing a semiconductor device, comprising: exposing the substrate to a silicon compound gas; and heat-treating the substrate in a non-oxidizing gas atmosphere, wherein a natural oxide film on a surface of the amorphous silicon layer is removed. And d. Immersing the substrate in pure water before the method. 2. The method according to claim 1, wherein said pure water is warm pure water having a temperature of 50 ° C. or higher. 3. The method according to claim 1, wherein the impurity is a phosphorus compound or an arsenic compound. 4. The method according to claim 1, wherein the step of heating the substrate is a step of heating the substrate in a vacuum or in an inert gas. 5. The step of exposing the substrate to a silicon compound gas at the predetermined partial pressure is a step of exposing the substrate to a silicon compound gas at a partial pressure of 1 × 10 ⁻³ Torr or less. Of manufacturing a semiconductor device. 6. The method according to claim 1, wherein the step of exposing the substrate to the silicon compound gas at the predetermined partial pressure is a step of irradiating the substrate with the silicon compound gas at a partial pressure of 1 × 10 ⁻³ Torr or less. The manufacturing method of the semiconductor device described in the above. 7. The method for manufacturing a semiconductor device according to claim 1, wherein said silicon compound is silane or disilane.