JPH11272551A - Flash control system for cache memory and cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a bus time out error by dividing a cache memory into a plurality of small sections, returning control to cache control logic whenever the flashing of the small sections completes, processing a bus operation which is held and continuing a flashing operation on the next small section. SOLUTION: Flash control logic is divided into two hierarchies. Low-order control logic controls a flashing processing in individual small sections and high-order control logic monitors low-order control logic until the flashing processing of all cache memory areas completes. Cache control logic 14-1 gives a signal permitting the flashing processing to flash low-order control logic 14-4 at the timing of the good punctuation of a bus operation. Flash low-order control logic 14-4 executes the flashing processing of the small section. When the processing on one small section completes, cache control logic 14-1 starts the bus operation which is held with the notice of a processing termination signal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control method for apparently speeding up access to a memory in a computer system, and more particularly, to storing the latest data stored in the cache memory in a main memory (main memory). It relates to a control method when writing back.

[0002]

2. Description of the Related Art First, a general method of a cache memory will be described, and then a general form of flash processing for collectively writing back data from a cache to a main memory (main memory) will be described.

FIG. 2 shows a state of an entry in a cache memory. Cache memory 1 in the initial state
Is empty, and each entry is invalid (Invali
d) In state 3. If the entry corresponding to the address to which the processor has issued the access request is not found in the cache (cache miss), the data at the corresponding address is fetched from the main memory 2 into the cache (read I).
N), the entry is set to a valid state 4. In the valid state 4, the contents of the cache entry and the contents of the main memory 2 match. In the example of FIG. 2, the entry corresponding to the address 207 is in the valid state (V) 4 and matches the data 5678 in the main memory 2.

In the case of the write-back type cache targeted by the present invention, when a write access from the processor hits a valid entry in the cache, only the entry in the cache is updated and the data in the main memory is updated. Therefore, there is a mismatch between the contents of the cache 1 and the main memory 2. Such an entry is modified (M
modified state 5, and the latest data exists only in the cache 1. In the example of FIG.
Is in the change (M) state 5, and the data 4871 is the latest data at this address. At this time, the main memory 2 has old data 3729, and is in a state of being inconsistent with the cache contents.

[0005] Flush processing in the cache memory refers to a change (Mod) for each entry in the cache.
(ifified) state 5 is written back to the main memory 1 so that the data matches, and the entry state is valid (Vali).
d) A process for returning to the state 4.

FIG. 3 shows an example of a simple cache configuration of the direct map system. Each entry in the cache 1 includes an address tag 11, data 12, and a bit 13-1 indicating an entry state. In this example, for the sake of simplicity, an address space of 16-bit data having a 16-bit address is assumed, and a direct mapping method of 256 entries is shown. Because of the direct map method, the entry position where each data is stored is determined by the lower address bit value 7-3. The upper address bit 7-2 is used as the address tag.

When a read access is made to a certain address, the cache 1 stores the lower address bits 7-
3 is read, the stored address tag 11 is compared with the upper address bit 7-2 for which the access was requested, and the status bit 13-1 read from the entry is determined. .

If the status is valid (V) or changed (M) and the address tags (11, 7-2) match, this access hits the cache 1 and the data 12 Is transmitted to the data bus 6 as read data. If the entry status read at the time of read access is invalid (I), it is a read miss, and the cache newly registers the upper bit 7-2 of the access address as an address tag in the entry and is supplied from the main memory. The read data 6 is written to this entry as a valid state (V).

When there is a write hit for an entry in the valid state (V), the cache overwrites the data stored in the entry with the write data 6 and
Update the status bits from valid (V) to changed (M).

Normally, the cache performs entry access using the lower bits 7-3 of the given address. However, when there is a flush processing request, the cache is switched to the internal address counter 8 and all entries are successively read. Flash is performed while reading.

FIG. 4 shows a control flow during the flash processing. When there is a flush request, the cache scans all entries, writes back to the main memory every time a "change (M) state" is detected, and sequentially eliminates inconsistencies with the main memory. .

To realize this, as shown in FIG. 4, a cache access at the time of a flush request is performed by the internal address counter 8 by the SEL1 selector 9-1 of FIG.
Side, and 0 is substituted as the initial value of this counter (flash address). Thereafter, flush processing is performed for each entry over the entire area of the cache memory. First, the cache entry corresponding to the flash address is accessed. If this entry is not in the "change (M) state", the flash address is incremented and the process proceeds to the next entry. On the other hand, if the read entry is in the “changed (M) state”,
The data is matched by writing back to the main memory 2 via the store buffer 16, and the entry state is updated to "valid (V)". Then, the flash address 8 is incremented, and the same processing is repeated until the last entry.

[0013]

FIG. 5 shows a bus configuration around a cache memory and a normal operation mode of the cache. The cache control circuit 42 is connected to the CPU 40 via the processor bus 41, while being connected to the main memory 44 and the interface 46 with the I / O side via the main bus 45. Here, the cache control circuit 42 must respond to both access requests from the processor (CPU) 40 and the I / O side. These access requests can be mainly classified into the following four from the point of data flow.

Cache hit access from processor The processing is completed only by data transfer between the processor 40 and the cache 43. No transaction is transmitted to the main bus 45.

A cache miss access from the processor A transaction is transmitted to the main bus 45 and the main memory 4
4 and the corresponding address is read. In case of a read mistake,
At the same time as transferring data from the main memory 44 to the processor bus 41, the data is taken into the cache memory 43 and newly registered in the entry. In the case of a write error, the main memory 44
From the cache memory 43,
The write data from the processor 40 is overwritten. If another address is registered in the “changed (M)” state in the entry in which the cache miss has occurred, this address is stored in the main memory 4.
Write back to 4.

Access to I / O space from processor Transmits transaction to main bus 45. This space is a cache-prohibited space, and the cache memory 4
No access to 3 is made.

DMA (Direct Memory) from the I / O side
Access) Access The bus right of the main bus 45 is normally
There are two. When performing DMA access to the memory from the I / O side 47, first, a bus right must be requested to the cache control circuit to obtain an access right to the main bus 45. After the bus right is granted, the I / O side (46,
47) accesses the main bus 45, but at the same time,
A snoop is performed on the cache memory 43, and the entry at the corresponding address and its state are inspected. Here, when a snoop read hit occurs in the entry of the “change (M) state”, since there is no latest data in the main memory 44, the reading of the main memory 44 is stopped and the cache memory 43 transfers the data to the I / O side 46. Supply the latest data.
Even if a snoop hit occurs in the cache 43, if the entry is in the “valid (V)” state, the data in the main memory 44 is guaranteed to be the latest data.
The data is supplied from the main memory 44 instead of 3.

The above is the normal operation. While the cache is performing the flushing process, the access from both buses is suspended, and the process waits until the flushing process is completed. FIG. 6 shows this state. When the flush process is started, the cache control circuit 42 suspends the return of the acknowledge signal for the access from the CPU 40, and extends the processor bus cycle until the flush process is completed. Also, even if a bus right request for DMA is issued from the I / O side during the flash processing, access to the main bus 45 from the I / O side is substantially prohibited without granting the bus right until the flash is completed. I do. In this state, the cache control circuit 42 sequentially accesses all the cache entries, and if there is one in the “change (M)” state, writes back to the main memory 44 to set it to the “valid (V)” state.

As described above, during the flash processing, the CPU
From the point of view of 40, the non-response state continues for a long time even if an access request is issued to the bus. Similarly, on the I / O side, a non-response state for a signal requesting the bus right continues for a long time.

In the above example, a cache configuration of 256 entries is shown for simplification of the drawing, but the number of entries is generally on the order of tens of thousands to several millions. Here, it is assumed that there are 64K entries, and each entry stores 32 bytes of data.
It is assumed that 20 clocks (CPU clocks) are required for each entry to write back to the main memory via a main bus that operates on the basis of a half frequency clock (assumed to be Hz). Assuming that 80% of all entries are in the changed (M) state, the flash processing takes about 10 ms. During this time, the CPU and the I / O keep the bus unresponsive, and the larger the cache capacity, the more the bus timeout error occurs.

In order to solve such a problem, conventionally, as disclosed in Japanese Patent Application Laid-Open No. Hei 8-44626 ("a flush cycle control method for a cache system"), the state search of each entry of the cache is speeded up. Had been done, to avoid. However, even with such a method, the capacity of the cache memory is increased, and the cache monopolizes the bus for a long time, for example, when most of the cache entries are in a changed state and need to be written back to the main memory. As a result, the above problem is not essentially solved.

An object of the present invention is to provide a control method capable of performing flash processing without keeping the bus in an exclusive state for a long time even when the cache memory has a large capacity.

[0023]

FIG. 7 and FIG. 8 show the relationship between the conventional cache control logic and the flash control logic and the operation thereof, and first clarify the cause of the above problem. The flush start instruction 20 is given to the cache control logic 14-1. Cache control logic 14-1
When the flash instruction 20 is given, the timing at which the operation of the processor bus and the main bus is well separated is
The control is transferred to the flash control logic 14-2 by the flash processing start signal 21. Here, flash control logic 1
4-2 starts the flash processing 28, and one cache control logic suspends the bus operation until the flash processing completion signal 22 is returned without starting the operation even when an access request from the bus is issued. Flash processing 28
Is completed, the flush control completion signal 22 is returned from the flush control logic 14-2 to the cache control logic 14-1, and the cache control logic 14-1 starts the bus operation which has been suspended.

Here, the problem of the bus timeout is the length of time during which the bus is held in a non-response state during the flush processing 28. Flash processing 2
8 is limited by the operation speed of the main memory and the main bus, so that the time length required for all the processing cannot be reduced.

Therefore, the cache memory is divided into a plurality of small sections, and control is returned to the cache control logic each time the flushing of each small section is completed, and the bus operation which has been suspended is processed. By continuing the flash processing for the section, a bus timeout error during the flash processing can be avoided.

[0026]

FIG. 9 and FIG. 10 show a flash hierarchy control method according to the present invention. In this method, the cache memory is divided into a plurality of small sections, and control is returned to the cache control logic each time the flushing of each small section is completed, and after processing the suspended bus operation, the next small section is executed. The flash control logic is split into two layers to avoid bus timeout errors during the flash process by continuing the flash process for. The lower control logic controls the flash processing in each small section, and the upper control logic monitors the lower control logic until the flash processing of all the cache memory areas is completed.

As shown in FIG.
Is performed on the flash higher-level control logic 14-3.
The flash higher-level control logic 14-3 requests the cache control logic 14-1 to transfer control for flash processing by the flash processing request signal 23.
The cache control logic 14-1 gives a signal 24 for permitting the flash processing to the flash lower-level control logic 14-4 at a timing when the bus operation is well separated. The flash lower-level control logic 14-4 performs the flash processing (flash sub-processing) 30 for the small section, and when the processing for one small section is completed, this is sent to the cache control logic 14-1 by the flash sub-processing end signal 25. Notice. The cache control logic 14-1 initiates the pending bus operation 27. On the other hand, the flash higher-level control logic 14-3 keeps outputting the flush processing request signal 23 until the flush processing of all the cache memory areas is completed (period 29 in FIG. 10). At a timing when the bus operation is well separated, the flash enable 24 is issued to the flash lower control logic 14-4.

Thereafter, every time the flash processing 30 of each small section is completed, the flash processing is performed for all the small sections while repeating the insertion of the reserved bus operation processing 27. When the flash processing 30 of the last small section is completed, the lower flash control logic 14-4 outputs a flash sub-processing end signal 25 to the cache control logic 14-1 and outputs the same to the upper flash control logic 14-3. In response, a flash processing completion signal 26 is issued. As a result, the flash host control logic 14-3 negates the flash processing request signal 23, and all flash operations are completed.

FIG. 11 shows the operation flow of the flash upper control logic, and FIG. 12 shows the operation flow of the flash lower control logic.

The flash higher-level control logic asserts a flash processing request signal after clearing a flash address to 0 in response to a flash processing instruction. Thereafter, the flash processing request signal is kept asserted until a flash processing completion signal is output from the flash lower control logic.

On the other hand, when the flash processing permission is given from the cache control logic,
An entry in the cache corresponding to the flash address is accessed to determine whether or not the state is “change (M)”.
When write-back is required in the "change (M)" state, the data is written to the main memory via the store buffer, and the entry state is set to "valid (V)". When the processing of one entry is completed, the flash address is incremented and the processing of the next entry is performed. When all the processes in the small section (sub-section) are completed, a flash sub-processing end signal is output, and the lower flash control ends. At this time, if the processing has been completed for all the small sections, a flash processing completion signal is output to the flash higher-level control logic, and the processing ends.

FIG. 1 is a block diagram showing a configuration example of a memory control system according to an embodiment of the present invention, which integrates the above-described control logic and data path of a cache.

The control logic 14 constantly monitors transactions on the bus, and detects that the CPU has written to a specific address allocated as the control space, thereby initiating the start of a flush process in the cache.
Recognizes that he is pointing. That is, although not specifically shown, by providing a register for taking in data on the data bus when decoding a transaction to be written to a specific address in the cache control logic, a write pulse to this register or The output of this register can be used as the flash instruction signal 20.

Flash upper control logic 14-3 in FIG.
Outputs the flash processing request signal 23 in response to the previous flash instruction signal 20, and instructs the address counter 8 for flash processing to substitute the initial value '0' by the control signal 100. The cache control logic 14-1 outputs the flush permission signal 24 at a well-defined timing. Flash lower control logic 14-
4 receives the flash permission signal 24 and switches the SEL1 selector 9-1 to the address counter 8 side by the selection signal 102, and gives a flash address to the cache memory 1. As a result, the cache memory 1
Reads the contents of the entry pointed to by the address counter.

The flash sub-control logic 14-4 examines the current status bit 13-1 of the entry read. State 13-1 of the read entry is valid (V)
Alternatively, if the entry is invalid (I), nothing is performed on this entry. If this entry indicates the state M (change), the control signal 105 checks whether or not the store buffer 16 is empty. If it is empty, it waits for it to become empty, and if it is empty, it writes the held data 12 of this entry to the store buffer 16. Similarly, the read address tag and the flash address (entry number) indicated by the address counter 8 are set
Each is stored in the address buffer 17 as upper / lower bits of the address (the value of this address buffer is used as a write address when writing back the data in the store buffer 16 to the main memory). In parallel with this, the new state V (valid) of this entry is written back to the cache memory 1 by 13-2.

Next, the flash lower control logic 14-4
Checks the state of the address sub-count end signal 107 from the address counter 8 to determine whether or not the flush process for the small cache section has been completed. In particular,
Whether the lower bits of the address counter 8 are a specific value, for example, whether all the lower 4 bits are “1” is detected by an AND gate or the like, and it is determined whether the flash small section is completed.

When the processing of the small section is not completed, the flash lower-order control logic 14-4 increments the value of the address counter 8 by +1 according to the address counter control signal 100. Hereinafter, the above-described processing content is repeated for the next entry pointed to by the address counter 8.

When the flash lower-level control logic 14-4 detects from the value of the address counter 8 that the processing of the flash subsection has been completed, the cache control logic 14-4
A flash sub-processing end signal 25 is output for -1 to notify that the small section processing has been completed. Here, the cache control logic 14-1 processes a pending bus transaction, if any, to perform a normal cache access.

At a timing when a bus transaction is well-separated (when one or a plurality of transactions have been processed), the cache control logic 14-1 receives the flush enable signal 2 again when there is a flush request 23.
4 transfers control to the flash lower control logic 14-4.

The flash lower control logic 14-4 performs a flash process on the next small section while incrementing the value of the address counter 8 by one. When the flash sub-processing end signal 25 and the address count end signal 101, which are the status signals of the address counter 8, indicate the completion of the processing of all areas of the cache memory along with the completion of the flash subsection, the flash lower control logic 14-4 sets the flash The sub-processing end signal 25 is sent to the cache control logic 14-1.
And outputs a flash processing completion signal 26 to the flash higher-level control logic 14-3.

In response to the flush sub-process end 25, the cache control logic 14-1 resumes the bus transaction process which has been suspended. On the other hand, the flash higher-level control logic 14-3 receives the flash processing completion signal 26 and negates the flash processing request signal 23.

Here, although not specifically described, in the flash processing, the entry in the state M (change) is written back to the main memory via the store buffer 16 and the address buffer 17. The store buffer 16 and the address buffer 17 are managed by the cache control logic 14-1. Upon detecting that a new address and data have been stored in the address buffer 17 and the store buffer 16, respectively, the cache control logic 14-1 acquires the bus right and selects the SEL2 selector 9
-2, the selection signal 103 selects the store buffer 16, and the control signals 104 and 106
By driving the state buffers 15-1 and 15-2,
The data and address are sent out on the bus, and the data is written back to the corresponding address in the main memory. When this process is completed, the store buffer 16 and the address buffer 17 become empty, and can accept new data and addresses.

Here, writing back to the main memory via the store buffer 16 and the address buffer 17 at the time of the flash processing is performed by performing the cache entry search for the flash and the write-back operation to the main storage in parallel to improve the performance. It is not essential to the present invention. Therefore, when a cache entry having a state of M (change) is detected, the cache entry search is temporarily stopped and the cache entry is directly read from the cache to the corresponding address in the main memory without using a store buffer or the like. The written data may be written back.

In the present embodiment, in order to prevent a bus timeout error by dividing the cache flush processing time, the lower bits of the address counter used to search for the state M entry during the flush processing are used. That is, each time a plurality of lower bits of the flash address counter become a specific value (for example, all the lower 4 bits are “1”), the flash processing is temporarily suspended, and the bus transaction waiting in the suspended state is processed. The description has been made using an example in which the above is performed.

However, the essence of the present invention is to divide the flush processing time to such an extent that the pending bus transaction does not cause a time-out error, and the present invention is not limited to the above-mentioned example. The time may be interrupted at regular intervals.

To do this, a counter is prepared for the timer, and when transferring control from the cache control logic to the flash lower control logic, an appropriate value is loaded into this counter, and thereafter, the flash processing is performed. During this period, the value of this counter is decremented by 1 with a clock having a known cycle, and when the value of the counter becomes '0', the processing of the flash small section is stopped, and control is returned to the cache control logic. I do.

Contrary to this example, the value of the timer counter is reset at the start of processing of each flash small section (the value of the counter is set to "0"), and the value of this counter is controlled by a clock during the processing of the flash small section. The value is incremented by one, and when the value of the counter reaches a specific value (either detected by comparing with the counter value by a register holding a specific value and a comparator, or the value of each output bit of the counter as it is or Inverting and inputting to the multi-input AND gate detects that the value has reached a specific value), interrupts the processing of the flash small section, returns control to the cache control logic, and is in a suspended state. Bus transaction may be performed.

Further, in the above-described embodiment, the small section is determined by the number of cache entries searched for flash (to detect that all of the plurality of lower bits of the flash address counter become "1"). Although defined, a small section may be defined by the number of entries that have been written back to the main memory by the flash processing when the change state (state M) is detected. That is, a "write-back" counter is prepared in place of the timer counter, this counter is reset when the control is transferred from the cache control logic to the lower-level control logic, and the "state M (changed state)" )) Is incremented by 1 each time the counter reaches a certain value, the processing of the flash small section is interrupted, and control is returned to the cache control logic again.

In any method, the essence of the present invention is to divide the flush processing time so that a bus transaction in a pending state during the flush processing does not cause a time-out error. Either method may be used depending on the number, a fixed time using a timer counter, or the number of entries written back to the main memory.

According to the hierarchical control method described above, the time during which a bus access request from the CPU or I / O waits in a no-response state during the flash processing is limited to the flash processing time for each small section. Since 512 entries are actually one small section, if the write-back time per entry is 20 clocks (50 MHz clock) and 80% of the entries are in the "changed (M) state", the flashing of each small section is performed. Processing time is 160μs
Becomes Even if the cache memory has a large capacity, the number of small sections increases, but the processing time of each small section does not increase and a bus timeout error does not occur.

[0051]

As described above, according to the present invention, in the flush processing of a large-capacity cache memory, the cache memory is divided into a plurality of small sections, and each time the flushing of each small section is completed, the normal cache is read. Returns control to the control logic and the CPU that was suspended during the flush
And after processing memory access from the bus device,
Since flash processing can be continued for the next small section, a bus timeout error during flash processing in a large-capacity cache memory can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one configuration example of a memory control system to which a cache memory control method is applied to one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a state transition of each entry in a cache memory.

FIG. 3 is a block diagram illustrating a configuration example of a memory control system to which a normal cache memory control method is applied;

FIG. 4 is a flowchart illustrating a control flow of a normal flash process.

FIG. 5 is an explanatory diagram showing a hierarchical structure of a bus and various access modes.

FIG. 6 is an explanatory diagram showing an access state from each bus at the time of flush processing of the cache memory.

FIG. 7 is an explanatory diagram showing the configuration of a conventional cache control logic and flush control logic.

FIG. 8 is an explanatory diagram showing the operation concept of the conventional cache control logic and flush control logic.

FIG. 9 is an explanatory diagram showing the configuration of a cache control logic and a flash control logic (flash upper control logic, flash lower control logic) when the present invention is implemented.

FIG. 10 shows a cache control logic and a flash control logic (flash upper control logic,
FIG. 4 is an explanatory diagram showing an operation concept of flash lower-order control logic).

FIG. 11 is a flowchart showing an operation flow of the flash higher-level control logic in the present invention.

FIG. 12 is a flowchart showing an operation flow of the flash lower control logic according to the present invention.

[Explanation of symbols]

1 Cache Memory 2 Main Memory 3 Entry Invalid State (Invalid State) 4 Entry Valid State (Valid State) 5 Entry Change State (Modified State) 6 Data 7-1 Address 7-2 Upper Address Bit 7-3 Lower Address Bit 8 Address Counter 9-1 Lower address bit selector (SEL1 selector) 9-2 Transmission data selector (SEL2 selector) 10 Address tag comparator 11 Address tag 12 Read data 13-1 Entry current status bit 13-2 Entry next status bit 14 Control Logic 14-1 Cache control logic 14-2 Flash control logic 14-3 Flash upper control logic 14-4 Flash lower control logic 15-1 Data transmission 3 state buffer 16 Store buffer 17 Address Buffer 20 Flash instruction signal 21 Flash processing start signal 22 Flash processing completion signal 23 Flash processing request signal 24 Flash enable signal 25 Flash sub-processing end signal 26 Flash processing completion signal 27 Cache normal operation period 28 Flash processing period 29 Flash processing incomplete period 30 Flash sub-processing period 40 CPU 41 Processor bus 42 Cache control circuit 43 Cache memory 44 Main memory 45 Main bus 46 Bus I / F 47 I / O bus 100 Address counter control signal 101 Address count end signal 102 Address selection signal 103 Send data Select signal 104 Data transmission control signal 105 Store buffer control signal 106 Address transmission control signal 107 Address sub count end signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Muraoka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.

Claims (6)

[Claims] In a write-back type cache memory, a flash process for storing the latest data, searching for an entry in a cache that is in a state inconsistent with the main storage, and writing it back to the main storage, wherein all the caches are started from the start of the flash processing A flush control method for a cache memory, characterized in that a search for a cache tag corresponding to a memory access request from a bus is performed at least once prior to completion of an entry search. 2. An m-bit (n> m) of an n-bit address for identifying a memory space, data corresponding to the address, and status data indicating a status of the data in a cache are associated with each other. Access request detecting means for monitoring a transaction on a bus and detecting that the transaction requests a read or a write to an address in a memory space; First cache memory access control means for accessing the cache memory in response to the read or write request detected by the request detection means, and monitoring of a transaction or control signal on the bus to detect the presence of a flush request Flash request detecting means; Second cache memory access control means for sequentially accessing each entry of the cache memory for the flash processing in response to the detection of the flash request by the detection means, and after the flash request detection means detects the flash request, If there is a read or write request to the memory by the access request detection means until the second cache memory access control means finishes accessing all the cache memory entries, at least one time the first cache memory access control means makes the first access request. A cache memory access control means for performing a cache memory access. 3. An m-bit (n> m) in an n-bit address for identifying a memory space, data corresponding to the address, and status data indicating a status of the data in a cache are associated with each other. Access request detecting means for monitoring a transaction on a bus and detecting that the transaction requests a read or a write to an address in a memory space; First cache memory access control means for accessing the cache memory in response to the read or write request detected by the request detection means, and monitoring of a transaction or control signal on the bus to detect the presence of a flush request Flash request detecting means; A second cache memory access control means for sequentially accessing each entry of the cache memory for the flash processing in response to the detection of the flush request by the detection means, and the second cache memory access control means starts the cache memory access Counting means for starting counting in response to the operation, and count value detecting means for detecting that the count value of the counting means has become a specific value or a value exceeding the specific value. When it is detected that the count value in the counting means has reached a specific value or a value exceeding the value, the first cache memory access control means responds to the read or write request already detected by the access request detecting means. If there is an access request in which the cache memory access by the Flash control method of the cache memory, characterized in that to perform the cache memory access corresponding to Seth request. 4. A flash memory control method according to claim 3, wherein said second cache memory access control means starts counting in response to the start of cache memory access for flush processing. Counting the number of cache entries retrieved by the second cache memory access control means for flushing, and detecting that the number of checked cache entries has reached a specific value or a value exceeding it. In this case, if there is an access request in which the cache memory access by the first cache memory access control unit is in an uncompleted state in the read or write request already detected by the access request detection unit, the access of the cache memory corresponding to the access request is performed. Key which is characterized by performing Flash control system of Sshumemori. 5. The cache control method according to claim 3, wherein the second cache memory access control means starts counting in response to the start of the cache memory access for the flash processing. Then, the number of cache entries written back to the main memory by the flash processing is counted, and when it is detected that the number of cache entries that have been written back has reached a specific value or a value exceeding it, an access request is issued. If there is an access request in which the cache memory access by the first cache memory access control unit is in an unfinished state in the read or write request already detected by the detection unit, the cache memory corresponding to the access request is accessed. Cache memory flash Interview control system. 6. A cache memory employing the flash control method according to claim 1, wherein a bus time-out error of a bus transaction whose access is suspended during a flash process is prevented. .