JPH1127251A - Frame synchronizing control device - Google Patents

Frame synchronizing control device

Info

Publication number
JPH1127251A
JPH1127251A JP9173591A JP17359197A JPH1127251A JP H1127251 A JPH1127251 A JP H1127251A JP 9173591 A JP9173591 A JP 9173591A JP 17359197 A JP17359197 A JP 17359197A JP H1127251 A JPH1127251 A JP H1127251A
Authority
JP
Japan
Prior art keywords
state
reception
synchronization
electric field
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9173591A
Other languages
Japanese (ja)
Inventor
Kazutaka Shiragami
一隆 白神
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9173591A priority Critical patent/JPH1127251A/en
Publication of JPH1127251A publication Critical patent/JPH1127251A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a frame synchronizing control device for improving multipath fading resistance by controlling an aperture gate which allows detection of a synchronous word on the basis of a reception electric field intensity when the reception is performed in a time-division multiple radio system. SOLUTION: This device is provided with an electric field intensity measuring circuit 6 for measurement, performs a state transition by a synchronizing word detection and slightly widens a width of an aperture gate when the electric field intensity exceeds a fixed value in executing a burst reception in a reception synchronizing state. Thus, a synchronizing word can be detected because the width of the aperture gate is not exceeded even when a place of the synchronizing word deviates from a whole slot by a multipath, and a fine frame synchronization is obtained and a higher quality speech is made possible because a reception state can maintain the synchronizing state.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、時分割多重通信方
式のディジタル無線通信方式におけるフレーム同期制御
装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization control apparatus in a digital radio communication system of a time division multiplex communication system.

【0002】[0002]

【従来の技術】従来、移動体通信において、1つの周波
数を時間軸上で複数のフレームに分割し、それぞれを異
なる局に割り当てるTDMA(時分割多重通信)方式を
用いた場合、フレーム同期を確立するために同期ワード
が用いられている。受信回路は、この同期ワードの検出
を行うことにより、1バースト中のデータの位置を検出
し、受信データ処理動作が可能となる。
2. Description of the Related Art Conventionally, in mobile communication, when one frequency is divided into a plurality of frames on a time axis and each is assigned to a different station, frame synchronization is established when a TDMA (Time Division Multiplexing Communication) system is used. A synchronization word is used to do this. The reception circuit detects the position of the data in one burst by detecting the synchronization word, thereby enabling the reception data processing operation.

【0003】以下、図面を参照しながら従来のフレーム
同期制御回路について説明する。図3は、従来のフレー
ム同期制御装置の構成図である。図3において、1は無
線部、2は同期ワード検出器、3は受信状態遷移回路、
4はアパーチャゲート制御回路、5は受信状態遷移回路
3とアパーチャゲート制御回路4からなる受信同期制御
回路である。
Hereinafter, a conventional frame synchronization control circuit will be described with reference to the drawings. FIG. 3 is a configuration diagram of a conventional frame synchronization control device. In FIG. 3, 1 is a wireless unit, 2 is a synchronous word detector, 3 is a reception state transition circuit,
Reference numeral 4 denotes an aperture gate control circuit, and reference numeral 5 denotes a reception synchronization control circuit including a reception state transition circuit 3 and an aperture gate control circuit 4.

【0004】以上のように構成された従来のフレーム同
期制御回路について、以下その動作を説明する。通常の
同期状態においては、無線部1にて復調されたデータは
同期ワード検出器2に入力され、アパーチャゲート制御
回路4からのアパーチャゲート信号が「1」の期間の
み、検出動作が行われる。同期ワードが検出されると同
期ワード検出信号が、受信状態遷移回路3に入力され
る。受信同期制御回路5は内部にタイマーを有し、次の
スロットまで、前記同期ワード検出信号が入力されたタ
イミングを保持し、次の受信スロットでは、前記の同期
ワード検出タイミングに対して狭い範囲で前後一定期間
「1」、その他の期間は「0」となるようアパーチャゲ
ートを制御し、本来同期ワードを検出するはずのない位
置での同期ワード検出の確立を低減させている。
The operation of the conventional frame synchronization control circuit configured as described above will be described below. In the normal synchronization state, the data demodulated by the radio unit 1 is input to the synchronization word detector 2, and the detection operation is performed only during the period when the aperture gate signal from the aperture gate control circuit 4 is "1". When the synchronization word is detected, a synchronization word detection signal is input to the reception state transition circuit 3. The reception synchronization control circuit 5 has a timer therein, and holds the timing at which the synchronization word detection signal is input until the next slot. In the next reception slot, the reception synchronization control circuit 5 has a narrow range with respect to the synchronization word detection timing. The aperture gate is controlled so as to be "1" for a certain period before and after and "0" for other periods, thereby reducing the establishment of synchronization word detection at positions where synchronization words should not be detected.

【0005】この様に、同期ワード検出器2は狭くなっ
たアパーチャゲートの範囲内で同期ワードの検出を行
い、同期ワード検出が出来なくなると、前方保護状態を
経由して非同期状態へ移行する。
As described above, the synchronous word detector 2 detects the synchronous word within the narrowed aperture gate, and when the synchronous word cannot be detected, the synchronous word detector 2 shifts to the asynchronous state via the forward protection state.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、前記従
来の方法では受信電界強度が十分ある場合にも関わら
ず、マルチパス等の影響で、同期ワードの位置がアパー
チャ幅を越えて移動した場合、同期ワード不検出とな
り、その後その状態が続くと、非同期状態となり、幅の
広いアパーチャゲートに制御が移るまで、同期ワードが
検出出来ず、フレーム同期は行えないという課題を有し
ていた。
However, in the above-mentioned conventional method, when the position of the synchronization word moves beyond the aperture width due to the influence of multipath or the like, despite the fact that the received electric field strength is sufficient, the synchronization is not sufficient. If a word is not detected and the state continues thereafter, the state becomes an asynchronous state, and there is a problem that a synchronization word cannot be detected and frame synchronization cannot be performed until control is transferred to a wide aperture gate.

【0007】そこで本発明は、電波状態の情報を状態遷
移に反映させてアパーチャゲート制御を行うことによ
り、高品質のフレーム同期制御を得ることができるフレ
ーム同期制御装置を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a frame synchronization control device capable of obtaining high quality frame synchronization control by performing aperture gate control while reflecting information of a radio wave state in state transition. .

【0008】[0008]

【課題を解決するための手段】請求項1に記載の発明
は、入力された受信電波を復調しバーストデータを出力
する無線部と、入力したバーストデータに対して同期ワ
ード検出を行い、その検出結果により同期ワード検出信
号を出力する同期ワード検出器と、この同期ワード検出
器からの検出信号に基づいてフレーム同期状態の遷移を
判定し、その判定された状態において状態信号を出力す
る受信状態遷移回路と、前記同期ワード検出器に対して
前記状態信号に対応したアパーチャ制御を行うアパーチ
ャゲート制御回路とを備えた受信同期制御回路から構成
され、同期状態において前記同期ワード検出器に対する
アパーチャゲート幅を可変制御する。
According to a first aspect of the present invention, there is provided a radio section for demodulating an input received radio wave and outputting burst data, detecting a synchronization word for the input burst data, and detecting the detection. A synchronization word detector that outputs a synchronization word detection signal based on the result, and a reception state transition that determines a transition of a frame synchronization state based on the detection signal from the synchronization word detector and outputs a state signal in the determined state. And a reception synchronization control circuit including an aperture gate control circuit that performs aperture control corresponding to the state signal on the synchronization word detector, and controls an aperture gate width for the synchronization word detector in a synchronization state. Variable control.

【0009】請求項2に記載の発明は、前記無線部に入
力された電波の電界強度を測定する電界強度測定回路を
備え、前記受信状態遷移回路から前記同期ワード検出器
に出力するアパーチャゲートの制御を電界強度の値に基
づいて制御する。
According to a second aspect of the present invention, there is provided an electric field strength measuring circuit for measuring the electric field strength of a radio wave input to the radio section, and an aperture gate for outputting from the reception state transition circuit to the synchronous word detector. Control is performed based on the value of the electric field strength.

【0010】[0010]

【発明の実施の形態】請求項1に記載の発明は、入力さ
れた受信電波を復調しバーストデータを出力する無線部
と、入力したバーストデータに対して同期ワード検出を
行い、その検出結果により同期ワード検出信号を出力す
る同期ワード検出器と、この同期ワード検出器からの検
出信号に基づいてフレーム同期状態の遷移を判定し、そ
の判定された状態において状態信号を出力する受信状態
遷移回路と、前記同期ワード検出器に対して前記状態信
号に対応したアパーチャ制御を行うアパーチャゲート制
御回路とを備えた受信同期制御回路から構成され、同期
状態において同期ワード検出器に対するアパーチャゲー
ト幅を可変制御するようにしているので、同期状態に応
じてスロット毎にアパーチャゲートを可変させ、最適な
フレーム同期状態を確立することができる。
According to the first aspect of the present invention, there is provided a radio section for demodulating an input received radio wave and outputting burst data, detecting a synchronization word with respect to the input burst data, and detecting a synchronization word based on the detection result. A synchronization word detector that outputs a synchronization word detection signal, a reception state transition circuit that determines a transition of a frame synchronization state based on a detection signal from the synchronization word detector, and outputs a state signal in the determined state. An aperture gate control circuit for performing aperture control corresponding to the state signal on the synchronous word detector, and variably controls an aperture gate width for the synchronous word detector in a synchronous state. So that the aperture gate can be varied for each slot according to the synchronization state, It can be established.

【0011】請求項2に記載の発明は、請求項1に記載
のフレーム同期制御装置において、無線部に入力された
電波の電界強度を測定する電界強度測定回路を備え、受
信状態遷移回路から同期ワード検出器に出力するアパー
チャゲートの制御を電界強度の値に基づいて制御するよ
うにしているので、電波状態の情報を状態遷移に反映さ
せてフレーム同期を行うことにより、高品質のフレーム
同期制御を得ることができる。
According to a second aspect of the present invention, there is provided the frame synchronization control apparatus according to the first aspect, further comprising an electric field intensity measuring circuit for measuring an electric field intensity of a radio wave input to the radio section, and synchronizing from the reception state transition circuit. Since the aperture gate output to the word detector is controlled based on the electric field strength value, high-quality frame synchronization control is achieved by performing frame synchronization by reflecting the radio wave state information in the state transition. Can be obtained.

【0012】以下、本発明の実施の形態について、図面
を参照しながら説明する。図1は本発明の実施の形態1
におけるフレーム同期制御装置の構成図、図2は本発明
の実施の形態1における状態遷移図である。図1におい
て、1は無線部、2は同期ワード検出器、3は受信状態
遷移回路、4はアパーチャゲート制御回路、5は受信状
態遷移回路3とアパーチャゲート制御回路4からなる受
信同期制御回路、6は電界強度測定回路である。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows Embodiment 1 of the present invention.
And FIG. 2 is a state transition diagram in Embodiment 1 of the present invention. In FIG. 1, 1 is a radio unit, 2 is a synchronous word detector, 3 is a reception state transition circuit, 4 is an aperture gate control circuit, 5 is a reception synchronization control circuit including a reception state transition circuit 3 and an aperture gate control circuit 4, Reference numeral 6 denotes an electric field strength measurement circuit.

【0013】以上の様に構成されたフレーム同期制御装
置について、以下その動作を説明する。無線部1にて復
調されたバーストデータは、同期ワード検出器2に入力
され同期ワードの検出が可能な場合、検出信号を受信状
態遷移回路3に対して出力する。検出信号を受けた受信
状態遷移回路3は、図2に示す状態遷移図に基づき非同
期状態から、連続して同期ワードを検出することにより
後方保護状態を経て同期状態に移行する。同期状態にお
いて受信状態遷移回路3は状態制御信号をアパーチャゲ
ート制御回路4に与えることによりアパーチャゲートの
幅の調整を行う。通常、同期状態ではアパーチャゲート
は狭い範囲で設定されているが、電界強度測定回路6か
らの電界強度データを受信して一定値を越えている場
合、マルチパスフェージング等により前回のバーストと
受信タイミングが異なっても十分復調が可能であると判
定し、アパーチャゲートの幅を広めに制御して、多少の
バーストデータの位置のずれに対してもアパーチャの範
囲を越えることなく受信出来るよう動作する。
The operation of the frame synchronization control device configured as described above will be described below. The burst data demodulated by the radio unit 1 is input to the synchronization word detector 2 and outputs a detection signal to the reception state transition circuit 3 when the synchronization word can be detected. The receiving state transition circuit 3 which has received the detection signal transitions from the asynchronous state to the synchronous state via the backward protection state by detecting the synchronous word continuously based on the state transition diagram shown in FIG. In the synchronized state, the reception state transition circuit 3 adjusts the width of the aperture gate by providing a state control signal to the aperture gate control circuit 4. Normally, the aperture gate is set in a narrow range in the synchronous state. However, when the electric field intensity data from the electric field intensity measurement circuit 6 is received and exceeds a certain value, the previous burst and the reception timing due to multipath fading or the like are caused. It is determined that demodulation is sufficiently possible even if is different, and the width of the aperture gate is controlled to be wider so that even a slight displacement of burst data can be received without exceeding the aperture range.

【0014】[0014]

【発明の効果】本発明は、受信電界強度からのデータを
受信状態遷移に加味出来るため、同期状態において電界
強度が十分大きい場合にアパーチャゲートを広げること
により、極端なマルチパスフェージングに対して同期ワ
ードの不検出を防止することが可能となり、良好なフレ
ーム同期を得ることができる。
According to the present invention, since the data from the received electric field strength can be added to the reception state transition, the aperture gate is widened when the electric field strength is sufficiently large in the synchronous state, thereby synchronizing with extreme multipath fading. It is possible to prevent non-detection of words, and to obtain good frame synchronization.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1におけるフレーム同期制
御装置の構成図
FIG. 1 is a configuration diagram of a frame synchronization control device according to a first embodiment of the present invention.

【図2】本発明の実施の形態1における状態遷移図FIG. 2 is a state transition diagram according to the first embodiment of the present invention.

【図3】従来のフレーム同期制御装置の構成図FIG. 3 is a configuration diagram of a conventional frame synchronization control device.

【符号の説明】[Explanation of symbols]

1 無線部 2 同期ワード検出器 3 受信状態遷移回路 4 アパーチャゲート制御回路 5 受信同期制御回路 6 電界強度測定回路 DESCRIPTION OF SYMBOLS 1 Radio part 2 Synchronous word detector 3 Reception state transition circuit 4 Aperture gate control circuit 5 Reception synchronization control circuit 6 Electric field strength measurement circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】入力された受信電波を復調しバーストデー
タを出力する無線部と、入力したバーストデータに対し
て同期ワード検出を行い、その検出結果により同期ワー
ド検出信号を出力する同期ワード検出器と、この同期ワ
ード検出器からの検出信号に基づいてフレーム同期状態
の遷移を判定し、その判定された状態において状態信号
を出力する受信状態遷移回路と、前記同期ワード検出器
に対して前記状態信号に対応したアパーチャ制御を行う
アパーチャゲート制御回路とを備えた受信同期制御回路
から構成され、同期状態において前記同期ワード検出器
に対するアパーチャゲート幅を可変制御することを特徴
とするフレーム同期制御装置。
1. A radio unit for demodulating an input received radio wave and outputting burst data, and a sync word detector for detecting a sync word for the input burst data and outputting a sync word detection signal based on the detection result. A receiving state transition circuit for determining a transition of a frame synchronization state based on a detection signal from the synchronization word detector, and outputting a state signal in the determined state; A frame synchronization control device, comprising: a reception synchronization control circuit including an aperture gate control circuit for performing aperture control corresponding to a signal, and variably controlling an aperture gate width for the synchronization word detector in a synchronization state.
【請求項2】前記無線部に入力された電波の電界強度を
測定する電界強度測定回路を備え、前記受信状態遷移回
路から前記同期ワード検出器に出力するアパーチャゲー
トの制御を電界強度の値に基づいて制御することを特徴
とする請求項1に記載のフレーム同期制御装置。
2. An electric field intensity measuring circuit for measuring electric field intensity of a radio wave input to the radio section, wherein control of an aperture gate output from the reception state transition circuit to the synchronous word detector is controlled to a value of electric field intensity. 2. The frame synchronization control device according to claim 1, wherein control is performed based on the frame synchronization.
JP9173591A 1997-06-30 1997-06-30 Frame synchronizing control device Pending JPH1127251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9173591A JPH1127251A (en) 1997-06-30 1997-06-30 Frame synchronizing control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9173591A JPH1127251A (en) 1997-06-30 1997-06-30 Frame synchronizing control device

Publications (1)

Publication Number Publication Date
JPH1127251A true JPH1127251A (en) 1999-01-29

Family

ID=15963439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9173591A Pending JPH1127251A (en) 1997-06-30 1997-06-30 Frame synchronizing control device

Country Status (1)

Country Link
JP (1) JPH1127251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6757687B2 (en) 2001-05-31 2004-06-29 Nokia Corporation Storage of data entries in digital devices and methods

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6757687B2 (en) 2001-05-31 2004-06-29 Nokia Corporation Storage of data entries in digital devices and methods

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