JPH1127109A - Latch circuit, flip-flop and combination circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit area and a test time in the case of conducting a scanning test by latching input data synchronously with a prescribed clock signal and selecting a latch operation or a through-buffer operation of a through- buffer. SOLUTION: With a control signal S set to 0, when a value of a latch enable signal G received by a NAND circuit 11 is 0, a value D1 of a data signal received by a D input 13C is outputted to a Q output 17. When the value of the latch enable signal G changes to 1, even when the value of the data signal received by a D input 13C changes to D2, an output from the Q output 17 is not immediately changed but keeps the value D1. In this case, the value D2 at the D input 13C is outputted to the Q output 17 when the latch enable signal G changes to 0. Furthermore, the control signal S is set to 1, even when the latch enable signal G is at '1', when the D input changes to a value D3, the value is outputted to the output Q.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

BACKGROUND OF THE INVENTION Prior Art (FIGS. 6 to 8) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 5) (1) First Embodiment (2) Second Embodiment (3) Third Embodiment (4) Other Embodiment Effects of the Invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit, a flip-flop circuit, and a combination circuit, and more particularly, to a latch circuit, a flip-flop circuit, and a combination circuit for processing data input to a sequential circuit.

[0004]

2. Description of the Related Art In recent years, LSIs (Large Scale Integrated
It is becoming difficult to increase the failure detection rate with the increase in the scale and complexity of the circuit. The scan test method is one of the methods to increase the fault detection rate in a relatively short test time, and the full scan method that makes all flip-flops in a circuit scan-ready because of easy test pattern generation and control is often used. Have been.

On the other hand, in order to increase the speed of the LSI, for example, in an LSI such as a signal processor which operates a large amount of data in a sequential manner, a flip-flop is inserted in the middle of an arithmetic circuit such as an adder / multiplier. In addition, a device has been proposed in which the operation speed is increased by forming the operation circuit into a pipeline.

The combinational circuit 1 shown in FIG.
n input terminals, and a flip-flop F1
0 to F1n and F20 to F2m are connected to form a synchronous circuit. Actually, in a synchronous circuit, it is usual that a plurality of such combinational circuits are connected in a plurality of stages. However, for the sake of simplicity, a case where there is one combinational circuit block will be described as an example.

The clock signal frequency (operating speed) of the combinational circuit 1 is determined by the maximum propagation time of the data signal input to the circuit. To increase the operating speed of the circuit, for example, as shown in FIG. Has been proposed.

That is, the combinational circuit 2 is divided like combinational circuits 2A and 2B, and the combinational circuits 2A and 2B are connected by flip-flops F30 to F3P.

As a result, the maximum propagation time of the combinational circuits 2A and 2B is clearly smaller than that of the combinational circuit 1, so that the clock signal frequency can be increased.

[0010]

The combination circuit 1
In the case of (1), the processing can be performed in one cycle from the input terminals D1 to Dn of the flip-flop to the flip-flops F20 to F2m. Flip Flop F2
Two cycles are required to output 0 to F2m.

However, when a large amount of data is continuously processed as in signal processing, the combinational circuits 2A and 2B perform a pipeline operation. In this case, processing can be performed in q + 1 cycles.

Accordingly, in the case of the combinational circuit 1, since there are q cycles, only one cycle occurs between the combinational circuit 1 and the combinational circuit 2, and the combinational circuit takes into account the increase in the clock signal operating frequency. Obviously, No. 2 is more suitable for high-speed operation.

Next, a case where a scan test is applied to enhance the test efficiency of the combinational circuit 2 will be described.
In order to apply the scan test, all flip-flops (SFF) must be used as in the combinational circuit 3 shown in FIG.
F10 to F1n, F20 to F1m, and F30 to F3P must be scan test compatible, a scan control signal S must be supplied to all of them, and all flip-flops must be serially connected for serial shift.

Generally, a flip-flop compatible with a scan test has a scan control signal terminal, a serial shift input / output terminal, and a logic circuit corresponding thereto, and therefore has a larger cell area than a normal flip-flop. This increase in cell area is imposed on all flip-flops, causing a problem of increasing the area of the entire combinational circuit.

Further, even in the serial shift operation at the time of the scan test, a large number of flip-flops are required, so that many shift wirings are required. For example, in the combination circuit 3, since all flip-flops are serially connected in the path from the serial scan input SI to the serial scan output SO, (n + 1 + 1 + 1 + 1 + m + 1) cycles are required from the serial scan input SI to the serial scan output SO. As described above, there is a problem that the test time is increased by increasing the number of shift stages.

The present invention has been made in view of the above points, and proposes a latch circuit, a flip-flop circuit, and a combination circuit which can reduce a circuit area and a test time when performing a scan test with a simple configuration. It is.

[0017]

According to the present invention, there is provided a latch circuit for latching input data in synchronization with a predetermined clock signal, and a latch operation or a through buffer operation for through buffering according to a control signal. Control means for switching.

Thus, the latch operation or the through-buffer operation can be switched according to the control signal.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment In FIG. 1, reference numeral 10 denotes a latch circuit as a whole.
A control signal S is input to the ND circuit 11 via a latch enable signal G and an inverter circuit 12. NA
The output of the ND circuit 11 is branched, and one of the outputs OUT1
Is the N channel gate 1 of the transmission gate 13
3A, and the output OUT2 via the other inverter circuit 14 is connected to the P channel gate 13B of the transmission gate 13. Thus, the switching operation of the transmission gate 13 is controlled by the NAND output of the latch enable signal G and the control signal S, and the D input 13C of the transmission gate 13 is controlled.
The timing of the output of the input data signal D is controlled.

The output of the transmission gate 13 is
After being output through the inverter circuits 15 and 16 and passing through the inverter circuit 15, the inverter circuit 1
8 and a feedback circuit constituted by the transmission gate 19.

The transmission gate 19 has a P channel gate 19A and an output OUT1 of the NAND circuit 11 connected thereto.
Is input to the N-channel gate 19B via the inverter circuit 14, so that the transmission gate 19 is controlled to open and close.

In the above configuration, the latch circuit 10
The input and output are controlled according to the timing shown in FIG. That is, when the control signal S input to the NAND circuit 11 via the inverter circuit 12 is 0, the data signal input to the D input 13C when the value of the latch enable signal G input to the NAND circuit 11 is 0. Is output to the Q output 17.

Next, when the value of the latch enable signal G changes to 1, the output value from the Q output 17 does not change immediately even if the value of the data signal input to the D input 13C changes to D2. Holds the value D1. In this case, the value D2 of the D input 13C is output to the Q output 17 when the latch enable signal G changes to the value 0. Further, the control signal S
When the D input changes to the value D3 even when the latch enable signal G has the value 1, the value becomes the output Q.
Is output to

Therefore, according to the above configuration, by setting the value of the control signal S to 0, the latch circuit 10 can be operated as a mere through buffer, and the D input can be performed regardless of the value of the latch enable signal G. Can be output to the Q output.

(2) Second Embodiment The flip-flop 20 shown in FIG. 3 constitutes a master-slave type flip-flop circuit, and the master 20
A clocked inverter circuit 21 is provided at the input stage of A.
OS (Metal Oxied Semiconductor) Transistor Q21
And Q22 connected in series (Complementary Met
al Oxied Semiconductor) Structured inverter circuit 21A
Input data D is input from the D input 22 of the.

The inverter circuit 21A has a PMOS (P-type MOS) MOS transistor Q21 connected to the source of a PMOS transistor Q21.
The drains of the S MOS transistors Q23 and Q24 are connected to each other, and the MOS transistors Q23 and Q24 are connected.
24 connects the sources to the power supply VDD.

Further, each of the MOS transistors Q23 and Q23
Reference numeral 24 denotes an XS signal of an XS signal (FIG. 4A) obtained by inverting the control signal S by an inverter circuit 47 at each gate.
A clock CKB (FIG. 4) in which the clock signal CK is output via the input 23 and the inverter circuits 48A and 48B.
The (B)) CKB input 24 is provided, and the XS input 23 and the CKB input 24 are NAND-operated.

The inverter circuit 21A is an NMOS transistor.
The drains of NMOS transistors Q25 and Q26 are connected to the source of (N-type MOS) MOS transistor Q22, respectively. Further, the sources of the respective MOS transistors Q25 and Q26 are grounded. And each MOS transistor Q25 and Q26
Has an S input 25 of a control signal S and an XCK input 26 of an XCK signal (FIG. 4 (A)) obtained by inverting a clock signal CK by an inverter circuit 48A at the gate, and the S input 25 and the XCK are provided. A NAND operation is performed on the input 26.

The output 22B of the inverter circuit 21A is connected to the inverter circuit 27, and the output of the inverter circuit 27 is connected to the input 28A of the feedback circuit 28. The output 28B of the feedback circuit 28 is connected so as to return to the inverter circuit 27.

The feedback circuit 28 includes PMOS MOS transistors Q30, Q31 and Q32 and an NMOS MOS transistor.
Transistors Q33, Q34 and Q35 are connected in series,
The power supply VDD is supplied to the source of the MOS transistor Q30, and the source of the MOS transistor Q35 is grounded.

Further, an input 28A of the feedback circuit 28 is connected to the gates of MOS transistors Q32 and Q33 which are connected in series so as to form an inverter circuit.
Output 2 from the drains of OS transistors Q32 and Q33
8B.

Further, the feedback circuit 28 has S inputs 29 and X at the gates of the MOS transistors Q30 and Q31, respectively.
A CK input 30 is provided and a MOS transistor Q3
4 and Q35 gates CKB inputs 32 and X, respectively.
An S input 31 is provided, which constitutes a clocked inverter circuit as a whole.

The output from the inverter circuit 27 on the master side 20A is supplied via an input 33 to the inverter circuit 34 of the clocked inverter circuit 34 in the input stage on the slave side 20B.
A is input to A.

The inverter circuit 34A includes a PMOS MO.
The drains of the PMOS MOS transistors Q40 and Q41 are connected to the source of the S transistor Q42, and the sources of the MOS transistors Q40 and Q41 are respectively connected to the power supply VDD.

Further, MOS transistors Q40 and Q4
1 is a circuit in which a control signal S is supplied to an inverter circuit 5
The XS input 35 of the XS signal (FIG. 4 (A)) inverted by X1 and the XC of the inverted output clock XCK (FIG. 4 (B)) of the clock signal CK via the inverter circuit 52A.
A K input 36 is provided, and the XS input 35 and the XCK
A NAND operation is performed on the input 36.

The inverter circuit 34A has an NMOS MOS transistor Q43 connected to the source of the NMOS MOS transistor Q43.
The drains of the transistors Q44 and Q45 are connected respectively. And each MOS transistor Q44 and Q
Numeral 45 grounds the respective sources. And each M
The gates of the OS transistors Q44 and Q45 supply the S input 37 of the control signal S and the clock signal CK to the CKB signal (FIG. 4) via the inverter circuits 52A and 52B, respectively.
(B)) CKB input 38 is provided, and the S input 3
7 and the CKB input 38 perform NAND operation.

The output 39 of the inverter circuit 34A is connected to the input 40A of the feedback circuit 40 via the inverter circuit 41, and the output 39B is fed back to the inverter circuits 41 and 42 from the output 40B.

The feedback circuit 40 includes PMOS MOS transistors Q50, Q51 and Q52 and NMOS MOS transistors.
Transistors Q53, Q54 and Q55 are connected in series,
The power supply VDD is supplied to the source of the MOS transistor Q50, and the source of the MOS transistor Q55 is grounded.

Further, an input 40A of the feedback circuit 40 is connected to the gates of MOS transistors Q52 and Q53 which are connected in series so as to form an inverter circuit.
Outputs the drains of OS transistors Q52 and Q53 to 4
0B.

Further, the feedback circuit 40 has S inputs 44 and C at the gates of the MOS transistors Q50 and Q51, respectively.
A KB input 45 is provided, and a MOS transistor Q5
XCK inputs 46 and X to the gates of 4 and Q55, respectively.
S input 47 is provided so that the master
A clock inverter circuit which operates with a delay of one clock with respect to the feedback circuit 28 of A is constructed.

In the above configuration, when the control signal S has the value 0, the clocked inverter circuit 21 on the master side 20A
When the value 0 of the control signal S is input to the S input 25 of the control signal S, the value 1 of the control signal S inverted by the inverter circuit 51 is input to the XS input 23 at the same time. At this time, the value 0 of the control signal S is input to the S input 37 of the clocked inverter circuit 34 on the slave side 20B at the same time, and the value 1 of the control signal S inverted by the inverter circuit 51 is input to the XS input 35 at the same time. Is done.

As a result, the MOS transistors Q23 and Q2 of the clocked inverter circuit 21 on the master side 20A.
5 and the MOS transistors Q40 and Q44 of the clocked inverter circuit 34 on the slave side 20B are all turned off.

At the same time, the S input 29 of the feedback circuit 28 on the master side 20A has the value 0 of the control signal S, and the XS input 31 has the value 1 of the control signal S inverted by the inverter circuit 51. Is entered. Further, the value 0 of the control signal S is input to the S input 44 of the feedback circuit 40 on the slave side 20B, and the value 1 of the control signal S inverted by the inverter circuit 51 is input to the XS input 47.

Thus, the feedback circuit 28 on the master side 20A
The MOS transistors Q30 and Q35 of the slave side 20B and the MOS transistors Q50 and Q53 of the feedback circuit 40 on the slave side 20B are all turned on, and the flip-flop 2
The master side 20A and the slave side 20B of 0 operate as if the control signal S of the latch circuit 10 shown in FIG. Therefore, the flip-flop 20 operates as a master-slave flip-flop that takes in the data signal D at the rising edge of the clock signal CK when the control signal S has the value 0.

When the control signal S has the value 1, the master 2
The value 1 of the control signal S is input to the S input 25 of the clocked inverter circuit 21 of 0A, and the inverter circuit 51
The value 0 of the control signal S inverted by the above is input to the XS input 23. At this time, the value 1 of the control signal S is input to the S input 37 of the clocked inverter circuit 34 on the slave side 20B, and the value 0 of the control signal S inverted by the inverter circuit 51 is input to the XS input 35 at the same time. Is done.

As a result, the MOS transistors Q23 and Q2 of the clocked inverter circuit 21 on the master side 20A.
5 and the MOS transistors Q40 and Q44 of the clocked inverter circuit 34 on the slave side 20B are all turned on.

At the same time, the S input 29 of the feedback circuit 28 on the master side 20A has the value 1 of the control signal S at the S input 29, and the XS input 31 has the value 0 of the control signal S inverted by the inverter circuit 51. Is entered.

Further, the S input 43 of the feedback circuit 40 on the slave side 20B receives the value 1 of the control signal S and the XS input 47
The control signal S inverted by the inverter circuit 51.
Is input.

Thus, the feedback circuit 28 on the master side 20A
MOS transistors Q30 and Q35 and the MOS transistors Q50 and Q55 of the feedback circuit 40 on the slave side 20B are all turned off. Therefore, when the control signal S is 1, the feedback circuits 28 and 40 on the master side 20A and the slave side 20B simply operate as inverter circuits.
0 operates as a buffer circuit that passes through from the D input 22A to the Q output 43.

Therefore, according to the above configuration, when the value of the control signal S is 0, the flip-flop 20 operates as a master-slave type flip-flop.
Is 1, the switching can be controlled to operate as a buffer circuit that passes through from the D input 22A to the Q output 43.

(3) Third Embodiment A combination circuit 50 shown in FIG. 5 includes a plurality of multiplexer type flip-flops (SFF) F1 corresponding to a scan test.
0 to F1n and F20 to F2m are connected to two divided combination circuit blocks 51 and 52, and each of the combination circuit blocks 51 and 52 is constituted by the flip-flop 20 according to the above-described second embodiment. Are synchronized by a plurality of flip-flops (NFFs) F30 to F3L.

The combinational circuit 50 performs a serial shift of a scan test by serially connecting flip-flops F10 to F1m and F20 to F2m.

Thus, the combinational circuit 50 divides the two-partitioned combinational circuit blocks 51 and 52 by flip-flop F.
The circuit can be operated at high speed by connecting by 30 to F3L.

The flip-flops F10 to F1n have scan control terminals S10 to S1n, respectively, and the flip-flops F20 to F2m have scan control terminals S20 to S2m, respectively. Further, the flip-flops F30 to F3L supply the control signal S to the S inputs 25, 29, 37 and 43 of each flip-flop 20, respectively, and the inverted signal XS of the control signal S to the XS inputs 23, 31, 35 and 44, respectively. Scan control terminals S30 to S3L to be supplied are provided.

Thus, flip flops F10 to F1
n, a control signal S for controlling whether or not to execute a scan test on F20 to F2m and F30 to F3L is supplied via scan control terminals S10 to S1n and S20 to S2m and scan control terminals S30 to S3L. .

In the above configuration, when the combinational circuit 50 operates in a circuit, for example, as shown in FIG. 2, when the value of the control signal S is 0, each of the flip-flops is operated as described in the second embodiment. The flip-flops F30 to F3L constituted by 20 operate as a master-slave type flip-flop, thereby providing a combinational circuit 50.
The data input from each of the D inputs D0 to Dn of
The signals are input to the combinational circuit block 51 via the flip-flops F10 to F1n, and the combinational circuit blocks 51 and 5 are inputted.
After the processing by the predetermined circuit operation by 2 is performed, it is taken into flip-flops F20 to F2m after 2 clock signals.

At the time of the scan test, that is, when the value of the control signal S is 0 in FIG. 2, each of the flip-flops F30 to F30 is constituted by the flip-flop 20.
F3L operates as a simple through buffer regardless of the value of the clock signal CK. This allows the flip flop F
Combinational circuit block 5 connected by 30 to F3L
1 and 52 can be considered as one combinational circuit.

In this case, in the combination circuit 50, only the flip-flops F10 to F1n and F20 to F2m are used as flip-flops corresponding to the scan test. Therefore, the scan serial shift paths from the serial scan input SI to the serial scan output SO are different from each other. The number of shift path stages n + 1 and m + 1 of flip-flops F10 to F1n and F10 to F1m are summed (n + 1 + m +
1) The cycle is completed.

Here, at the time of the scan test, when the flip-flops F10 to F1L are used as through buffers and the combinational circuit blocks 51 and 52 are formed as one combinational circuit,
Even if a propagation delay of a data signal occurs, a scan test can generally be performed at an operating frequency lower than the circuit operation, so that the propagation delay time in this case does not matter in the scan test.

According to the above configuration, the combinational circuit 50 is
The combination circuit blocks 51 and 52 are connected by flip-flops F30 to F3L which can be switched to flip-flop operation or through-buffer operation. In accordance with the control signal S, the flip-flops F30 to F3L connecting the combinational circuit blocks 51 and 52 are switched to the flip-flop operation synchronized with the clock signal CK or the through buffer during circuit operation and scan test. The combination circuit 5
The speed of the predetermined circuit operation of 0 can be improved, and the shift time at the time of the scan test can be greatly reduced.

Further, each of the flip-flops F30 to F3L connecting the combination circuit blocks 51 and 52 of the two-part combination circuit 50 is constituted by the flip-flop 20, so that the flip-flop F30 is provided.
Since F3L does not include a selector or the like and omits scanning serial operation wiring, the circuit area can be reduced, and thus the circuit configuration of the entire combinational circuit 50 can be simplified.

(4) Other Embodiments In the above-described second embodiment, the master 20
Feedback circuits 28 and 40 are added to both A and the slave side 20B to provide a flip-flop circuit that performs a static operation during circuit operation. However, the present invention is not limited to this, and the feedback circuits 28 and 40 are deleted. A flip-flop circuit that operates dynamically may be used. Also M
The same effect as that of the above-described second embodiment can also be obtained in a ratio type circuit that realizes a latch operation by removing the OS transistors Q30, Q50, Q35, and Q55 and changing the size ratio of the transistors.

Further, in the above-described second embodiment, the case where the clocked inverter circuit and the feedback circuit are provided on both the master side 20A and the slave side 20B has been described. However, the present invention is not limited to this. Master side 2
A clocked inverter circuit and a feedback circuit controlled by a clock signal may be provided on at least one of the slave side 20A and the slave side 20B. As a result, the same effect as in the second embodiment can be obtained, and the test time and the circuit area of the scan test can be reduced.

In the above embodiment, the MOS
Although the case where a latch circuit is formed using transistors has been described, the present invention is not limited to this, and a latch circuit may be formed using bipolar transistors.

[0066]

As described above, according to the present invention, a latch operation for latching input data or a through buffer operation for through buffering in synchronization with a predetermined clock signal can be switched in accordance with a control signal. A latch circuit, a flip-flop circuit, and a combination circuit which can reduce a circuit area and a test time can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration of a latch circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the latch circuit.

FIG. 3 is a schematic block diagram showing a configuration of a flip-flop circuit according to a second embodiment of the present invention.

FIG. 4 is a schematic block diagram showing a configuration of a flip-flop circuit according to a second embodiment of the present invention.

FIG. 5 is a schematic block diagram showing a configuration of a combinational circuit according to a third embodiment of the present invention.

FIG. 6 is a schematic block diagram showing a conventional combination circuit.

FIG. 7 is a schematic block diagram showing a conventional combination circuit.

FIG. 8 is a schematic block diagram showing a conventional combination circuit.

[Explanation of symbols]

1, 2, 3, 50 ... combination circuit, 10 ... latch circuit, 13C, 22A ... D input, 12, 14, 15, 1
6, 18, 27, 41, 45 ... inverter circuit, 1
3, 19 ... Transmission gate, 11 ... NA
ND circuit, 21, 34 ... clocked inverter circuit,
28, 40 ... feedback circuit.

Claims (6)

[Claims] 1. A latch circuit comprising: latch means for latching input data in synchronization with a predetermined clock signal; and control means for switching between a latch operation and a through buffer operation for through buffering according to a control signal. A clock signal control section for controlling on / off of the output of the clock signal in accordance with a value of the control signal; and a control section for synchronizing the input data with the clock signal in accordance with the control signal. The latch circuit according to claim 1, further comprising a latch portion for latching. 3. An input data is read by a master side,
In a flip-flop circuit for delaying the input data in time and transferring it to the slave side, a latch means for latching the input data in synchronization with a predetermined clock signal and a through buffer operation for latching or through buffering according to a control signal. A flip-flop circuit comprising a latch circuit having control means for switching on at least one of the master side and the slave side. 4. The clock circuit according to claim 1, wherein said latch circuit controls the output of said clock signal on and off in accordance with a value of said control signal, and said input data is synchronized with said clock signal in accordance with said control signal. 4. The flip-flop circuit according to claim 3, further comprising control means having a latch portion for latching. 5. A combination circuit for performing a predetermined sequential operation on input data, wherein: a latch means for latching the input data in synchronization with a predetermined clock signal; and a through buffer operation for performing a latch operation or a through buffer according to a control signal. A combination circuit comprising a flip-flop circuit provided with a latch circuit having control means for switching. 6. A flip-flop circuit comprising: a clock signal control section for controlling on / off of the output of the clock signal according to the value of the control signal; and the input data in synchronization with the clock signal according to the control signal. 6. The combination circuit according to claim 5, further comprising control means having a latch portion for latching.