JPH1127071A - Waveform slicing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a waveform slicing circuit which can surely slice even a high frequency input signal waveform at its upper and lower limit levels. SOLUTION: This slicing circuit 110 consists of a 1st slicing circuit 120 which slices the lower limit side of an input signal waveform at a prescribed level, an inverter circuit 130 which inverts the signal waveform that is sliced by the circuit 120, and a 2nd slicing circuit 140 which has the same constitution as the circuit 120 and slices the lower limit side of the signal waveform inverted by the circuit 130 at a prescribed level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a waveform slicing circuit, and more particularly to a waveform slicing circuit for slicing a high-frequency input signal waveform at upper and lower limits.

[0002]

2. Description of the Related Art FIG. 3 shows a circuit diagram of a conventional wideband amplifier having a waveform slicing function. The conventional wideband amplifier 1 has a configuration in which a wideband amplifier circuit section 10, a slice circuit section 20, and an output circuit section 30 are formed on the same semiconductor substrate. The broadband amplifier circuit section 10 comprises a non-inverting amplifier circuit including NPN transistors Q11 and Q12, resistors R11 to R13, a reference voltage source 11, and constant current sources 12 and 13.
The input signal supplied to the input terminal Tin is non-inverted amplified from the connection point between the resistor R12 and the collector of the transistor Q12 and output. The input signal that has been non-inverted and amplified by the broadband amplifier circuit unit 10 is supplied to the slice circuit unit 20.

The slicing circuit section 20 comprises a lower limit slicing circuit 21 for slicing on the lower limit side of the input signal and an upper limit slicing circuit 22 for slicing on the upper limit side of the input signal. The lower limit slice circuit 21 includes an NPN transistor Q
21 and Q22, a resistor R21, and constant current sources 23 and 24. The slice on the lower limit side of the input signal is performed according to a slice level set by the resistor R21 and the constant current source 24.

The signal sliced on the lower limit side by the lower limit slice circuit 22 is supplied to an upper limit slice circuit 23. The upper limit slice circuit 22 includes a PNP transistor Q23, Q24 having a polarity opposite to the polarity of the transistor constituting the lower limit slice circuit 21, a resistor R22, and constant current sources 25, 26.
And slices the upper limit side of the input signal in accordance with the slice level set by the resistor R21 and the constant current source 26.

The lower limit slicing circuit 21 and the upper limit slicing circuit 22 are configured so that the polarities of the transistors are opposite to each other and are symmetrical with respect to the power supply voltage Vcc, thereby slicing the upper limit and lower limit. The signal on which the upper and lower limits have been sliced by the slice circuit 20 is supplied to the output circuit unit 30. The output circuit section 30 includes an NPN transistor Q31 and a constant current source 31, and outputs a sliced signal from an output terminal Tout.

FIG. 4 shows an operation waveform diagram of an example of the related art. FIG. 4A shows the output point of the broadband amplifier circuit section 10, that is,
4B is a waveform at the input point a of the lower limit slice circuit 21, FIG. 4B is an output point of the lower limit slice circuit 21, that is, a waveform at the input point b of the upper limit slice circuit 22, and FIG. The waveform diagram of a point, that is, an input point c of the output circuit unit 30 is shown.

[0007] from the broadband amplifier circuit 10 at time t1 as shown in FIG. 2 (A), when the signal S1 projecting downward from the slice level L _L is supplied, the lower limit slicing circuit 21
In signal S1 is sliced at the lower slice level L _L,
Figure 2 (B) is cut below the slice level L _L As shown in the signal S1 'is obtained. Also, at time t2
In the signal S ₂ that protrudes upward than the slice level L _H is supplied, the signal S2 at the upper slice circuit 22 is sliced at the upper limit slice level L _H, the slice level as shown in FIG. 2 (C) L _H The signal S2 'with the upper portion cut off is obtained.

[0008]

However, when the slice circuit 20 is formed into an IC, the PNP transistor generally has a lateral structure. A PNP transistor having a lateral structure has a wide base width due to its structure. In addition, since the emitter and collector regions are enlarged in order to increase the current amplification factor, the junction capacitance and the stray capacitance are increased, and the series resistance of the base and collector is large. Therefore, the high frequency characteristics are
Deterioration compared to transistors.

For this reason, the frequency characteristic is degraded in the upper limit slice circuit 22. Here, when a high-frequency signal is supplied as an input signal, the lower limit slice circuit 21
Although slicing can be performed reliably by following, the upper limit slicing circuit 22 cannot follow the input signal, resulting in incomplete slicing. FIG. 5 is a diagram for explaining a problem of an example of the related art. FIG. 5A shows an input waveform to the slice circuit 20, and FIG.
(B) shows the output waveform of the slice circuit 20.

When the input signal has a high frequency, FIG.
The signal S1 protruding below the slice level L _L as shown in FIG. 5 is surely sliced by the lower limit slice circuit 21 as shown by the signal S1 'in FIG.
Signal protruding upward from the slice level L _H as shown in (A) S2 can not follow the upper slice circuit 22 is an input signal, an overshoot as shown by the signal S2 'in FIG. 5 (B) has occurred It is a waveform and cannot be sliced reliably.

As described above, the conventional waveform slicing circuit is
The upper limit slice circuit 21 slices the upper limit of the input signal and the lower limit slice circuit 22 slices the lower limit of the input signal. The upper limit slice circuit 21 and the lower limit slice circuit 22 are composed of transistors having opposite polarities. When a semiconductor chip is formed, the PNP transistor is generally formed as a lateral PNP transistor.
Since the frequency characteristics of the lateral PNP transistor are lower than that of the NPN transistor, when the input signal has a high frequency, the frequency characteristics of the lower limit slice circuit 23 composed of the lateral NPN transistor deteriorate, and the slicing of the input signal becomes uncertain. And so on.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a waveform slicing circuit capable of reliably slicing even a high-frequency input signal.

[0013]

According to a first aspect of the present invention, there is provided a waveform slicing circuit for slicing the upper and lower limits of an input signal waveform. The slice circuit and the first
An inverting circuit for inverting the input signal sliced by the slicing circuit, and one of an upper limit and a lower limit of the inverted input signal which has the same configuration as the first slice circuit and is inverted by the inverting circuit And a second slicing circuit for slicing.

According to the first aspect, either the upper limit or the lower limit of the input signal is sliced by the first slice circuit, and the input signal having one of the upper limit or the lower limit of the signal sliced by the first slice circuit is processed. Invert by an inverting circuit,
The second slice circuit, which has the same configuration as that of the first slice circuit and slices the same side as the first slice circuit, slices the inverted input signal to obtain a side sliced by the first slice circuit. The opposite side can be sliced, so that both the upper and lower limits of the input signal can be sliced by the slice circuit having the same configuration.

According to a second aspect of the present invention, the first and second slice circuits include a first NPN transistor to which the input signal is supplied to a base and which outputs a current corresponding to the input signal from an emitter, and a slice level. A slice level setting unit to be set; and a second NPN that supplies the slice level set by the slice level setting unit to a base and outputs a current according to the slice level from an emitter.
It has a transistor and a constant current source that draws a constant current from the emitters of the first and second NPN transistors.

According to the second aspect, since the first and second slice circuits can be constituted by NPN transistors having relatively excellent frequency characteristics, even if a high-frequency input signal is supplied,
Slicing can be performed reliably. A third aspect of the present invention is characterized in that the first and second slice circuits and the inverting circuit are formed integrally on the same semiconductor chip.

According to the third aspect, when the first and second slice circuits and the inverting circuit are integrated and formed on the same semiconductor chip, they are constituted by NPN transistors having excellent frequency characteristics when formed into a semiconductor chip. Therefore, even when a high-frequency input signal is supplied, slicing can be performed reliably, and a wide-band input signal can be handled.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a case where the clamp circuit of the present invention is applied to a wide band amplifier will be described. FIG.
1 shows a circuit configuration diagram of an embodiment of the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted.

The wide-band amplifier 100 of this embodiment is formed on a one-chip semiconductor substrate, is provided between the wide-band amplifier circuit section 10 and the output circuit section 30, and converts input signals to both upper and lower sides. The configuration of the slicing circuit 110 for slicing is different from the conventional wideband amplifier 1 of FIG. The slicing circuit 110 of the present embodiment is supplied with the input signal amplified by the wideband amplification circuit unit 10 and slices the input signal at a preset lower limit level.
0, an inverting circuit 130 for inverting the signal sliced by the first slice circuit 120, and a second slice circuit for slicing the signal inverted by the inverting circuit 130 at a preset lower limit.

The first slice circuit 120 includes NPN transistors Q121 and Q122, a resistor R121, a constant current source 12
1,122. The transistor Q121 has a resistor R12 whose base is the output terminal of the broadband amplifier circuit 10.
And a collector of the transistor Q121, the power supply voltage Vcc is applied to the collector, and the emitter is grounded via the current source 121.

The resistor R121 and the constant current source 122 are connected in series between the power supply voltage and the ground, and generate a potential corresponding to the slice level at a connection point between the resistor R121 and the constant current source 122.
Supply to the base of transistor Q122. The transistor Q122 has a base connected to a connection point between the resistor R121 and the constant current source 122, a power supply voltage Vcc applied to the collector, and an emitter connected to a connection point between the transistor Q121 and the constant current source 121. A connection point between the emitters of the transistors Q121 and Q122 and the constant current source 121 is used as an output terminal of the first slice circuit 120 and is connected to the inversion circuit 130.

In the first slice circuit 120, the constant current source 121 draws a constant current I0 from the emitters of the transistors Q121 and Q122.
, Q122, the output is determined according to the emitter current.
The emitter current of the transistor Q122 is equal to the resistance of the resistor R12.
1 and a predetermined value by the constant current source 122.

For this reason, when the output signal of the broadband amplifier circuit 10 decreases and the transistor Q121 turns off, a constant current is supplied from the transistor Q122 to the constant current source 121, and the current between the emitter of the transistor Q122 and the constant current source 121 is reduced. The connection point is set to a constant potential. That is, a signal obtained by slicing the lower limit of the input signal at a predetermined level is obtained.

The signal whose lower limit has been sliced by the first slicing circuit 120 is supplied to an inverting circuit 130. The inverting circuit 130 includes NPN transistors Q131 and Q132, resistors R131 to R133, a reference voltage source 131, a constant current source 132,
133 to form a differential amplifier circuit. The transistor Q131 has a base connected to the first slice circuit 12
The output of the transistor Q121 is connected to a connection point between the emitters of the transistors Q121 and Q122 and the constant current source 121. The collector is supplied with the power supply voltage Vcc via the resistor R131, and the emitter is connected via the constant current source 132. Grounded.

On the other hand, the transistor Q132 has a base to which a reference voltage is applied from a reference voltage source 131, a collector to which a power supply voltage Vcc is applied via a resistor R132, and an emitter which is set via a constant current source 133. Transistor Q
131 and the connection point between the constant current source 132 and the transistor Q132
A resistor R133 is connected between the node and the connection point of the constant current source 133, and a voltage corresponding to the difference between the reference voltage and the first slice circuit is generated in the resistor R133.

It should be noted that the output is a resistor R131 and a transistor Q
131, the collector potential of the transistor Q131 becomes a potential obtained by inverting the base potential. Therefore, the output signal of the inverting circuit 130 is different from the signal obtained by inverting the output signal of the first slice circuit 120. Become. The output signal of the inverting circuit 130 is supplied to the second slice circuit 140.

The second slice circuit 140 has the same configuration as the first slice circuit 120, and includes NPN transistors Q141 and Q142, a resistor R141, and a constant current source 14.
1,142. The transistor Q141 has a base connected to a connection point between the resistor R141, which is an output terminal of the inverting circuit 140, and the collector of the transistor Q141. The power supply voltage Vcc is applied to the collector, and the emitter is grounded via the constant current source 141. You.

The resistor R141 and the constant current source 142 are connected in series between the power supply voltage Vcc and the ground, and generate a potential corresponding to the slice level at a connection point between the resistor R141 and the constant current source 142, and connect the base of the transistor Q142. To supply. The transistor Q142 has a base connected to the connection point between the resistor R141 and the constant current source 142, a power supply voltage Vcc applied to the collector, and an emitter connected to the transistor Q141 and the constant current source 141.
Is connected to the connection point. Transistors Q141, Q142
A connection point between the emitter and the constant current source 141 is used as an output terminal of the second slice circuit 140 and is connected to the output circuit unit 30.

In the first slice circuit 120, the constant current source 121 draws a constant current I0 from the emitters of the transistors Q121 and Q122.
, Q122, the output is determined according to the emitter current.
The emitter current of the transistor Q122 is equal to the resistance of the resistor R12.
1 and a predetermined value by the constant current source 122.

Therefore, when the output signal of the inverting circuit 130 decreases and the transistor Q141 turns off, a constant current is supplied from the transistor Q142 to the constant current source 141,
The connection point between the emitter of the transistor Q142 and the constant current source 141 is set at a constant potential. That is, a signal obtained by slicing the lower limit of the input signal at a predetermined level is obtained. The signal whose lower limit is sliced by the second slice circuit 140 is supplied to the output circuit unit 30.

Next, the operation of the slice circuit 110 will be described with reference to the drawings. FIG. 2 shows an operation waveform diagram of the slice circuit according to one embodiment of the present invention. FIG. 2A shows a broadband amplifier circuit unit 1.
0, that is, the waveform of the input signal a ′ of the first slice circuit 120, FIG. 2B shows the output signal of the first slice circuit 120, that is, the waveform of the input signal b ′ of the inversion circuit 130, 2C shows the output signal of the inverting circuit 130, that is, the waveform of the input signal c ′ of the second slice circuit 140, and FIG. 2D shows the output signal of the second slice circuit 140, that is, the output circuit section. 30 shows a waveform diagram of 30 input signals d ′.

As shown in FIG. 2A, at time t11, the signal S
11 falls from the reference voltage V0 below the slice level L1, and at time t12 the signal S21 rises above the reference voltage V0, the signal S11 is sliced by the first slice circuit 120 at the slice level L1. 2
This is the signal S12 shown in FIG. At this time, the signal S21 rising above the reference voltage V0 at time t12 is above the slice level L1 and is not affected at all.

As shown in FIG. 2B, a signal waveform c 'obtained by slicing the signal S11 at the slice level L1 is supplied to the inverting circuit 130, and as shown in FIG.
It is inverted around 0 and protrudes above the reference voltage V0 as in the signal S13. Further, the inverting circuit 130 shown in FIG.
In the inverted waveform c ', the sliced signal S21 is inverted around the reference voltage V0, and protrudes below the reference voltage V0, as shown in the signal S22.

The waveform c 'shown in FIG. 2C is sliced by the second slice circuit 140 at the slice level L2. At this time, since the signal S22 protrudes below the slice level L2, the slice level L2
The portion protruding further downward is sliced and used as a signal S23 shown in FIG. At this time, since the signal S13 protrudes above the reference voltage V0 and is above the slice level L2, it is not affected at all.

As shown in FIG. 2D, signals S11 and S21 projecting outside the slice level in the upper and lower limits around the reference voltage V0 are both sliced, and the signals S13 and S
It is supplied to the output circuit section 30 as 23. As described above, according to the present embodiment, the slice circuit 110 includes the NPN transistors Q121, Q122, Q131, Q132,
It can be composed of Q141 and Q142. The NPN transistor is
When a semiconductor chip is used, since the semiconductor chip has higher high-frequency characteristics than a lateral PNP transistor having a structure generally used as a PNP transistor, even if a high-frequency input signal is supplied, the operation can be sufficiently followed. . Therefore, overshooting as shown in FIG. 5B, which can reliably slice even a high-frequency input signal, can be prevented.

[0036]

As described above, according to the first aspect of the present invention, either the upper or lower limit of the input signal is sliced by the first slice circuit, and the upper or lower limit of the signal is sliced by the first slice circuit. One of the sliced input signals is inverted by an inverting circuit, and the inverted input signal is sliced by a second slice circuit having the same configuration as the first slice circuit and slicing the same side as the first slice circuit. By doing so, the side opposite to the side sliced by the first slice circuit can be sliced, and therefore, both the upper and lower limits of the input signal can be sliced by the slice circuit having the same configuration.

According to the second aspect, since the first and second slice circuits can be composed of NPN transistors having relatively excellent frequency characteristics, even if a high-frequency input signal is supplied,
It has features such as reliable slicing.
According to claim 3, when the first and second slice circuits and the inversion circuit are integrated and formed on the same semiconductor chip,
When a semiconductor chip is used, it can be composed of NPN transistors having excellent frequency characteristics. Therefore, even when a high-frequency input signal is supplied, slicing can be performed reliably, and a wide-band input signal can be handled.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of one embodiment of the present invention.

FIG. 3 is a block configuration diagram of an example of a related art.

FIG. 4 is an operation waveform diagram of a conventional example.

FIG. 5 is a diagram for explaining a problem of a conventional example.

[Explanation of symbols]

Reference Signs List 10 amplifier circuit section 11 reference voltage source 12, 13 constant current source 20 output circuit section 100 wideband amplifier 110 slice circuit section 120 first slice circuit 121, 122, 132, 133, 141, 142 constant current source 130 inverting circuit 131 reference Voltage source 140 Second slice circuit Q121, Q122, Q131, Q132, Q141, Q142N
PN transistor R121, R131, R132, R133, R141 Resistance

Claims (3)

[Claims] 1. A waveform slicing circuit for slicing upper and lower limits of an input signal waveform, a first slice circuit for slicing one side of the input signal waveform, and the input signal sliced by the first slice circuit. And a second slice circuit having the same configuration as that of the first slice circuit and slicing one side of the input signal inverted by the inversion circuit. Waveform slicing circuit. 2. The first and second slicing circuits include a first NPN transistor to which the input signal is supplied to a base and output a current according to the input signal from an emitter, and a slice for setting a slice level. Level setting means, a second NPN transistor which is supplied to the base with the slice level set by the slice level setting means, and outputs a current according to the slice level from an emitter, and the first and second NPN transistors 2. A waveform slicing circuit according to claim 1, further comprising: a constant current source for drawing a constant current from said emitter. 3. The waveform slice circuit according to claim 1, wherein the first and second slice circuits and the inversion circuit are formed integrally on a same semiconductor chip.