JPH1126635A - Bga type semiconductor device - Google Patents

Bga type semiconductor device

Info

Publication number
JPH1126635A
JPH1126635A JP18110797A JP18110797A JPH1126635A JP H1126635 A JPH1126635 A JP H1126635A JP 18110797 A JP18110797 A JP 18110797A JP 18110797 A JP18110797 A JP 18110797A JP H1126635 A JPH1126635 A JP H1126635A
Authority
JP
Japan
Prior art keywords
chip
recess
substrate
type semiconductor
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18110797A
Other languages
Japanese (ja)
Other versions
JP3816636B2 (en
Inventor
Toshiyuki Hashimoto
俊幸 橋本
Kenji Yoshida
賢司 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP18110797A priority Critical patent/JP3816636B2/en
Publication of JPH1126635A publication Critical patent/JPH1126635A/en
Application granted granted Critical
Publication of JP3816636B2 publication Critical patent/JP3816636B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Abstract

PROBLEM TO BE SOLVED: To providing a thin type package and avoid wire sagging by forming a recess into a substrate to put and settle a chip in the recess. SOLUTION: A recess 3 for housing a chip 2 is formed into a substrate 1 and has a rectangular lower layer recess 3-1 just for fitting the rectangular chip 2 at a depth half the thickness of the substrate 1 and upper recess 3-2 tapered to expand upwards from the recess. The chip 2 chucked to a bonding tool a of a metal or heat-resistive resin collet is fitted into the recess 3-1 of the recess 3 from above. This improves the radiation efficiency, never obstructs when mounting and allows the substrate 1 to be thin.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、BGA型半導体
装置に関する。
The present invention relates to a BGA type semiconductor device.

【0002】[0002]

【従来の技術】従来、BGA型半導体装置100 は図9に
示すように基板101 上にAg ペーストを塗布した後チッ
プ102 を固着し、ワイヤーボンディング103 をして樹脂
モールド104 をし、次いで基板裏面に半田ボール105 を
移載してリフローを行い、半田ボールの溶着を行うこと
によって製造している。
2. Description of the Related Art Conventionally, as shown in FIG. 9, a BGA type semiconductor device 100 is prepared by applying an Ag paste on a substrate 101, fixing a chip 102, performing wire bonding 103 to form a resin mold 104, and then forming a back surface of the substrate. Is manufactured by transferring a solder ball 105 to the substrate and performing reflow, and welding the solder ball.

【0003】[0003]

【発明が解決しようとする課題】このように、従来のB
GA型半導体装置100 は、基板101 上にチップ102 を固
着して、ワイヤーボンディング103 や樹脂モールド104
を行うものであるが、基板上に突設した状態にチップを
固着しているため、ワイヤーがチップ上面から基板上に
大きく弯曲して張設され、樹脂モールド時にワイヤー流
れが生起したり、チップの厚み分だけモールドの厚みが
大きくなり、薄型化できない欠点があった。
As described above, the conventional B
The GA type semiconductor device 100 has a chip 102 fixed on a substrate 101, and a wire bonding 103 or a resin mold 104.
However, since the chip is fixed in a state where it protrudes from the substrate, the wire is greatly bent and stretched from the top surface of the chip onto the substrate, causing wire flow during resin molding, The thickness of the mold is increased by the thickness of the mold, and there is a disadvantage that the thickness cannot be reduced.

【0004】[0004]

【課題を解決するための手段】この発明は、基板に凹部
を形成し、凹部内にチップを収納固着したことを特徴と
するBGA型半導体装置を提供せんとするものである。
SUMMARY OF THE INVENTION The present invention provides a BGA type semiconductor device in which a recess is formed in a substrate and a chip is housed and fixed in the recess.

【0005】また、凹部内のチップと基板に設けたイン
ナーリードとを、チップ下面に突設したバンプを介して
導通したことにも特徴を有する。
Another feature is that the chip in the recess and the inner lead provided on the substrate are electrically connected to each other through bumps projecting from the lower surface of the chip.

【0006】また、凹部内のチップの上方に放熱用メタ
ルを配設してモールドしたことにも特徴を有する。
Another feature is that a heat-dissipating metal is disposed above the chip in the recess and molded.

【0007】[0007]

【発明の実施の形態】この発明では、基板の凹部内にチ
ップを固着しているため、パッケージの薄型化が可能と
なり、しかもチップとインナーリードとの間を、チップ
下面に突設したバンプを介して導通することにより、従
来のワイヤーボンディング工程が省略できる共に、ワイ
ヤー結線後のモールド時のワイヤー流れも防止できるも
のであり、また、チップが凹部内に埋設されているた
め、チップ上方に放熱用メタルを配設しても、パッケー
ジの嵩が大きくならず、しかも銅等の放熱用のメタルに
よって帯熱を防止し放熱効率を向上しうるものである。
According to the present invention, the chip is fixed in the concave portion of the substrate, so that the package can be reduced in thickness. In addition, a bump protruding from the lower surface of the chip is provided between the chip and the inner lead. By conducting through, the conventional wire bonding process can be omitted, the wire flow during molding after wire connection can be prevented, and since the chip is embedded in the recess, heat is radiated above the chip. Even if metal is provided, the bulk of the package does not increase, and heat radiation such as copper can prevent heat buildup and improve heat radiation efficiency.

【0008】[0008]

【実施例】この発明の実施例を図面にもとづき詳説する
と、図1は、本発明のBGA型半導体装置Mに使用する
基板1の平面図を示しており、図2は、その断面側面図
を示している。
FIG. 1 is a plan view of a substrate 1 used in a BGA type semiconductor device M according to the present invention, and FIG. 2 is a sectional side view thereof. Is shown.

【0009】基板1にはチップ2を収納するための凹部
3を形成している。
The substrate 1 has a recess 3 for accommodating the chip 2.

【0010】凹部3の形状は、基板1の厚みの中程に矩
形状のチップ2が嵌入するだけの矩形状の下層凹部3-1
と、その凹部から上方へ拡開したテーパー状の上層凹部
3−2とよりなる。
The shape of the concave portion 3 is such that the rectangular lower layer concave portion 3-1 in which the rectangular chip 2 only fits in the middle of the thickness of the substrate 1.
And a tapered upper concave portion 3-2 which is expanded upward from the concave portion.

【0011】基板1に形成された凹部3には、図2、図
3に示すように、金属製又は耐熱樹脂コレットのボンデ
ィングツールaに吸着されたチップ2が上方から凹部3
の下層凹部3−1 中に嵌入される。
As shown in FIGS. 2 and 3, a chip 2 adsorbed by a bonding tool a made of a metal or heat-resistant resin collet is provided in the recess 3 formed in the substrate 1 from above.
In the lower recess 3-1.

【0012】なお、ボンディングツールaを可動式にし
ておけば、ボンディングの位置ずれを生起してもテーパ
ー状の上層凹部3-2 により位置修正が行え、最終的に下
層凹部3-1 に正確に嵌入できる。
If the bonding tool a is made movable, the position can be corrected by the tapered upper concave portion 3-2 even if the bonding position shifts, and finally the lower concave portion 3-1 can be accurately positioned. Can be inserted.

【0013】下層凹部3-1 に嵌入されたチップ2は基板
下面より加熱して接着面を介し圧着固定する。
The chip 2 fitted in the lower recess 3-1 is heated from the lower surface of the substrate and fixed by pressure through an adhesive surface.

【0014】基板1の凹部3内底面には、図1に示すよ
うに、インナーリード4が多数配線されており、かかる
インナーリード4は、図4に示すように基板1内の導通
体5を介して、基板1裏面の半田ボール6と導通してい
る。
As shown in FIG. 1, a large number of inner leads 4 are wired on the bottom surface of the concave portion 3 of the substrate 1, and the inner leads 4 connect the conductors 5 in the substrate 1 as shown in FIG. Thus, it is electrically connected to the solder ball 6 on the back surface of the substrate 1.

【0015】ここで、具体的に、凹部3中にチップ2を
嵌入収納した状態でチップ2と半田ボール6との導通構
造を詳説する。
Here, the conduction structure between the chip 2 and the solder ball 6 in a state where the chip 2 is fitted and stored in the recess 3 will be described in detail.

【0016】すなわち、チップ2の下底面には、ボンデ
ィングパッド8の位置に、金素材のバンプ7を突設して
おり、バンプ7の下方には異方導電フィルム9を敷設
し、異方導電フィルム9を、インナーリード4と導通さ
せている。
That is, a bump 7 made of a gold material protrudes from the lower bottom surface of the chip 2 at the position of the bonding pad 8, and an anisotropic conductive film 9 is laid below the bump 7 to form an anisotropic conductive film 9. The film 9 is electrically connected to the inner lead 4.

【0017】異方導電フィルム9はシート状のフィルム
組成中に、導電粒子9-1 が多数埋蔵されており、一定の
圧力がかかった部分のみ導電粒子9-1 が相互に接して導
通される性質を有する。
In the anisotropic conductive film 9, a large number of conductive particles 9-1 are buried in a sheet-like film composition, and the conductive particles 9-1 are brought into contact with each other only in a portion where a certain pressure is applied to conduct. Has properties.

【0018】異方導電フィルム9の下面はインナーリー
ド4に接し、インナーリード4から導通体5を介して基
板1裏面の半田ボール6に導通している。
The lower surface of the anisotropic conductive film 9 is in contact with the inner lead 4, and is electrically connected from the inner lead 4 to the solder ball 6 on the back surface of the substrate 1 via the conductor 5.

【0019】従って、図9に示す従来のBGA型半導体
100 に比し、従来のチップ102 からのワイヤーボンディ
ング103 がなく、チップ2のバンプ7及び異方導電フィ
ルム9を介して直接にインナーリード4に導通されてい
ることになる。
Therefore, the conventional BGA type semiconductor shown in FIG.
Compared to 100, there is no wire bonding 103 from the conventional chip 102, and it is directly connected to the inner lead 4 via the bump 7 of the chip 2 and the anisotropic conductive film 9.

【0020】凹部3中にチップ2を嵌入固着した後に
は、図6に示すように液状封止樹脂10をディペンスノズ
ルbより凹部3中に注入してチップの封止を行う。
After the chip 2 is fitted and fixed in the recess 3, the liquid sealing resin 10 is injected into the recess 3 from the dispensing nozzle b to seal the chip, as shown in FIG.

【0021】上層凹部3-2 のテーパー形状により樹脂の
注入位置づれが生起しても樹脂は下層凹部3-1 の方向に
流入していき、正確な封止作業が行える。
Even if the injection position of the resin is shifted due to the tapered shape of the upper concave portion 3-2, the resin flows in the direction of the lower concave portion 3-1 and accurate sealing work can be performed.

【0022】かかる樹脂封止作業の前工程として図5に
示すように、チップ2の上面に銅素材の放熱プレート11
を載置し、放熱プレート11もチップ2と共に封止する。
As a pre-process of the resin sealing operation, as shown in FIG.
And the heat radiation plate 11 is also sealed together with the chip 2.

【0023】しかも、放熱プレート11は、厚みをチップ
2上面と基板1の上面との間の間隙に位置する厚みとし
ておく。すなわち、上層凹部3-2 と略同一、或は、上層
凹部3-2 の高さの略2分の1の厚みとしておき、樹脂封
止した場合、放熱プレート11の上面は基板1上面に露出
して、チップ2からの発熱を直接の熱伝導より基板1外
の大気に放熱するようにしている。
Further, the thickness of the heat radiation plate 11 is set to a thickness located in a gap between the upper surface of the chip 2 and the upper surface of the substrate 1. That is, the upper surface of the heat radiation plate 11 is exposed to the upper surface of the substrate 1 when substantially the same as the upper concave portion 3-2 or approximately half the height of the upper concave portion 3-2 and sealed with resin. Thus, heat generated from the chip 2 is radiated to the atmosphere outside the substrate 1 by direct heat conduction.

【0024】このように放熱プレート11下面が直接にチ
ップ2に接し、かつ上面が大気に露出することにより、
放熱効率を向上できると共に、チップ2と共に凹部3内
に埋設してしまうため、外観上突部が形成されず、実装
時に支障とならず、かつ基板1も薄型となる効果を有す
る。
As described above, the lower surface of the heat radiation plate 11 is in direct contact with the chip 2 and the upper surface is exposed to the atmosphere.
Since the heat radiation efficiency can be improved and the chip 2 is buried in the recess 3 together with the chip 2, no projection is formed in appearance, so that there is no hindrance at the time of mounting, and the substrate 1 is also made thin.

【0025】図7は、基板1に半田ボール6を突設し、
チップ2及び放熱プレート11を凹部3内に収納して樹脂
封止した状態を示す本発明のBGA型半導体装置Mの断
面図を示している。
FIG. 7 shows a state in which solder balls 6 are protruded from the substrate 1.
FIG. 2 is a cross-sectional view of the BGA type semiconductor device M of the present invention showing a state in which the chip 2 and the heat radiation plate 11 are housed in the recess 3 and sealed with a resin.

【0026】図8に示すのは放熱プレート11の他の変形
であり、該プレート11の側端面を上層凹部3-2 のテーパ
ー形状に合致したテーパー側端面に形成しており、凹部
3を収納時に上層凹部3-2 に嵌着するように構成してい
る。
FIG. 8 shows another modification of the heat radiating plate 11, in which the side end surface of the plate 11 is formed on the tapered side end surface conforming to the tapered shape of the upper layer concave portion 3-2. At times, it is configured to fit into the upper layer concave portion 3-2.

【0027】すなわち、放熱プレート11はチップ2を収
納した凹部3の蓋としての機能を果すような形状に構成
しているものであり、従って、モールド工程は、チップ
2の収納固着後に行い、次いで放熱プレート11をチップ
2の上面に重合しながら上層凹部3-2 を閉蓋することに
なる。
That is, the heat radiation plate 11 is formed in such a shape as to function as a lid of the concave portion 3 in which the chip 2 is stored. Therefore, the molding process is performed after the chip 2 is stored and fixed. The upper concave portion 3-2 is closed while the heat radiating plate 11 is superposed on the upper surface of the chip 2.

【0028】このように、放熱プレート11の形状を構成
することにより、放熱面積を大きくとることができると
共に、テーパー形状により該プレート11の装着作業が容
易に行えるものであり、更にはモールドも凹部3とチッ
プ2との間隙部分のみでよく、封入樹脂も少くてよく、
その分モールド工程も作業が簡便となり、かつモールド
樹脂が少い分、基板への熱変性も少く、更には放熱プレ
ート11はテーパー形状を介して接着剤により固着できる
ため、固着位置のずれもなく、確実な固定作業が行える
効果を有する。
By arranging the shape of the heat radiating plate 11 in this manner, a large heat radiating area can be obtained, and the mounting work of the plate 11 can be easily performed by the tapered shape. Only the gap between the chip 3 and the chip 2 is sufficient, and the amount of sealing resin may be small.
As a result, the molding process becomes simpler and the molding resin is smaller, the heat denaturation to the substrate is less, and the heat radiation plate 11 can be fixed with an adhesive through a tapered shape, so that there is no displacement of the fixing position. This has the effect that reliable fixing work can be performed.

【0029】以上のように、放熱プレート11の固着及び
モールド工程が終了すると、基板1の裏面に半田ボール
6の移載を行い、リフローして半田ボール6の固定を行
う。
As described above, when the fixing of the heat radiation plate 11 and the molding process are completed, the solder balls 6 are transferred to the back surface of the substrate 1 and reflowed to fix the solder balls 6.

【0030】[0030]

【発明の効果】この発明の請求項1によれば、凹部内に
チップを固着したために、チップが基板上に突出しない
ためパッケージを薄型に構成できる効果があり、ワイヤ
ーボンディングも低位置に張設でき、モールド樹脂によ
るワイヤー垂れも防止できる効果がある。
According to the first aspect of the present invention, since the chip is fixed in the concave portion, the chip does not protrude above the substrate, so that the package can be made thinner. This has the effect of preventing wire drooping due to the molding resin.

【0031】また、請求項2によれば、凹部内のチップ
と基板に設けたインナーリードとをチップ下面に突設し
たバンプを介して導通するために、ワイヤーボンディン
グ工程がなく、モールド時のワイヤー垂れも解消し構造
も簡単に構成でき、コストも安価となる効果を有する。
According to the second aspect of the present invention, since the chip in the concave portion and the inner lead provided on the substrate are electrically connected to each other through the bumps projecting from the lower surface of the chip, there is no wire bonding step, and the wire during molding is eliminated. This has the effect of eliminating drooping, simplifying the structure, and reducing the cost.

【0032】また、請求項3によれば、凹部内のチップ
上方に放熱用メタルを配設してモールドしたために、放
熱用メタルが介在するにもかかわらず、パッケージの厚
みが大きくならず、また放熱効率も向上し、放熱機能を
有するにもかかわらず、全体的にパッケージを薄型に形
成できる効果がある。
According to the third aspect of the present invention, since the heat-dissipating metal is disposed above the chip in the recess and molded, the thickness of the package does not increase despite the heat-dissipating metal being interposed. The heat dissipation efficiency is improved, and the package can be formed to be thin as a whole despite having a heat dissipation function.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明装置の基板を示す平面図。FIG. 1 is a plan view showing a substrate of an apparatus of the present invention.

【図2】同断面側面図。FIG. 2 is a sectional side view of the same.

【図3】本発明装置の基板にチップを装着する状態の説
明図。
FIG. 3 is an explanatory view showing a state in which a chip is mounted on a substrate of the device of the present invention.

【図4】本発明装置の基板にチップを嵌入して基板裏面
端子とチップ用バンプとが導通した状態を示す拡大説明
図。
FIG. 4 is an enlarged explanatory view showing a state in which a chip is fitted into a substrate of the device of the present invention and a terminal on the back surface of the substrate is electrically connected to a chip bump;

【図5】本発明の実施例を示す放熱板装着時の断面説明
図。
FIG. 5 is an explanatory cross-sectional view of the embodiment of the present invention when a heat sink is mounted.

【図6】図5において、凹部を封止する状態を示す説明
図。
FIG. 6 is an explanatory diagram showing a state in which a concave portion is sealed in FIG. 5;

【図7】本発明の実施例の完成状態を示す断面図。FIG. 7 is a sectional view showing a completed state of the embodiment of the present invention.

【図8】放熱板の変形を示す他の実施例の断面図。FIG. 8 is a cross-sectional view of another embodiment showing deformation of a heat sink.

【図9】従来のBGA型半導体装置の断面説明図。FIG. 9 is an explanatory sectional view of a conventional BGA type semiconductor device.

【符号の説明】[Explanation of symbols]

a ボンディングツール 1 基板 2 チップ 3 凹部 3-1 上層凹部 3-2 下層凹部 4 インナーリード 5 導通体 6 半田ボール 7 バンプ 8 ボンディングパッド 9 異方導電フィルム 10 液状封止樹脂 11 放熱プレート a bonding tool 1 substrate 2 chip 3 recess 3-1 upper layer recess 3-2 lower layer recess 4 inner lead 5 conductor 6 solder ball 7 bump 8 bonding pad 9 anisotropic conductive film 10 liquid sealing resin 11 heat dissipation plate

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板に凹部を形成し、凹部内にチップを
収納固着したことを特徴とするBGA型半導体装置。
1. A BGA type semiconductor device wherein a recess is formed in a substrate and a chip is housed and fixed in the recess.
【請求項2】 凹部内のチップと基板に設けたインナー
リードとを、チップ下面に突設したバンプを介して導通
したBGA型半導体装置。
2. A BGA type semiconductor device in which a chip in a recess and an inner lead provided on a substrate are electrically connected to each other via a bump protruding from a lower surface of the chip.
【請求項3】 凹部内のチップの上方に放熱用メタルを
配設してモールドしたBGA型半導体装置。
3. A BGA type semiconductor device in which a heat-dissipating metal is arranged above a chip in a recess and molded.
JP18110797A 1997-07-07 1997-07-07 BGA type semiconductor device Expired - Fee Related JP3816636B2 (en)

Priority Applications (1)

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JP18110797A JP3816636B2 (en) 1997-07-07 1997-07-07 BGA type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18110797A JP3816636B2 (en) 1997-07-07 1997-07-07 BGA type semiconductor device

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JPH1126635A true JPH1126635A (en) 1999-01-29
JP3816636B2 JP3816636B2 (en) 2006-08-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002101827A2 (en) * 2001-06-11 2002-12-19 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002101827A2 (en) * 2001-06-11 2002-12-19 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
WO2002101827A3 (en) * 2001-06-11 2003-12-04 Xilinx Inc High performance flipchip package that incorporates heat removal with minimal thermal mismatch
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch

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