JPH11265944A - Static type semiconductor memory device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily manufacture an SRAM memory cell, having improved soft error resistance, which can be microscopically formed in size and can be operated at high speed. SOLUTION: In an SRAM memory cell having driver transistors T2 and T3 and transfer transistors T1 and T4, the first conductive type first ion implantation layer 12a, which increases the junction capacitance between memory nodes ST1 and ST2 and a substrate 1, and the first conductive type second ion implantation layer 12b, which is provided on the end part of each source layer of the transistors T1, T2, T3 and T4, are provided. The first ion implantation layer 12a is formed extending from the end part of the drain layer to the other region of the drain layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static type semiconductor memory device (hereinafter referred to as SRAM) having improved soft error resistance due to .alpha.-rays, and in particular, it is possible to reduce a memory cell size. And an SRAM which is easy to manufacture and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the 0.35 μm rule has changed to 0.25 μm.
Although an SRAM employing the μm rule has been developed, the problem of a malfunction due to a soft error due to α rays has become more and more evident with the progress of miniaturization. That is, as the memory cell of the SRAM becomes finer, the amount of charge held in the storage node also becomes smaller, and particularly in a high resistance load type memory cell, the current supplied to the cell is very small. For this reason, α rays are incident on the semiconductor substrate in the memory cell from a package or the like, and electron-hole pairs are generated in the substrate, which move to the substrate surface and destroy the information stored in the storage node, and the memory It will cause a malfunction.

Conventionally, various measures have been proposed to improve the soft error resistance. For example, in order to increase the capacity of a storage node of a memory cell, a capacity obtained by adding a capacity by a gate insulating film in addition to a PN junction capacity (Japanese Unexamined Patent Application Publication No.
No. 161843) and a TFT type SRAM in which a high resistance portion is provided at a predetermined position of a wiring layer (Japanese Patent Laid-Open No. 5-235).
No. 301).

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the problem of a malfunction due to a soft error which has been remarkably generated in a miniaturized SRAM as described above, and has been made particularly in comparison with the prior art. It is an object of the present invention to provide an SRAM which is easy to manufacture, and which can reduce the size of a memory cell and increase the speed of a memory operation.

[0005]

SUMMARY OF THE INVENTION SRAM according to the present invention
Is an SRAM memory cell having driver transistors T2, T3 and transfer transistors T1, T4, a first conductivity type first ion implantation layer for increasing a junction capacitance between the storage nodes ST1, ST2 and the substrate; A first conductivity type second ion implantation layer provided at an end of each source layer of each of the transistors T1, T2, T3, and T4, and the first ion implantation layer is formed from an end of a drain layer. It is characterized in that it is formed so as to extend to another region of the drain layer. According to the present invention, since the capacity added to the storage nodes ST1 and ST2 by the first ion implantation layer is increased, the amount of charge stored in the storage nodes ST1 and ST2 is also increased, and electrons generated by α rays are increased. As a result, the resistance to soft errors can be improved. Further, the punch-through resistance of each of the transistors T1, T2, T3, and T4 can be simultaneously improved by the first and second ion implantation layers, and as a result, the memory cell can be further reduced. Conventionally, in order to improve punch-through resistance, there has been proposed a technique of forming an ion-implanted layer called pocket implantation at an end portion of a source / drain layer. By extending the drain layer constituting the storage node from the end to another region of the drain layer, the punch-through resistance and the soft error resistance are simultaneously improved. Further, in the method of manufacturing the SRAM according to the present invention, after forming the gate electrodes and the source / drain layers of the transistors T1, T2, T3, T4, only the drain layer (storage nodes ST1, ST2) and the end of the source layer are connected. A first ion-implanted layer and a second ion-implanted layer are formed by forming an opened photoresist film and ion-implanting a first conductivity type impurity from the opening to reach the junction depth of the source / drain layer. And According to this manufacturing method, each implantation layer can be formed in one ion implantation step. In a process in which pocket implantation for preventing punch-through has already been introduced, only a partial design change of the mask is required. And the manufacturing process is easy.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 3, an SRAM memory cell comprises transfer transistors T1 and T4, driver transistors T2 and T3, and high resistance load elements R1 and R2. Transfer transistors T1, T4
When the word line W goes high, the transfer transistors T1 and T4 turn on, and the memory cell and a pair of data lines D and * D (* D is inverted data). A data read operation or a write operation is performed.

[0007] This type of SRAM memory cell is called a high resistance load type, and is a type of memory cell that particularly requires measures against soft errors. As shown in FIG. 4, one of the driver transistors T2 and T3 forms a flip-flop.
Buried contact B is connected to the drain layer (N-type layer) of the other driver transistor T2 or T3, respectively.
Connected using C. The buried contact BC directly connects the diffusion layer and the polysilicon layer without a metal electrode such as an Al electrode.

Hereinafter, a method of manufacturing the SRAM according to the present embodiment will be described with reference to FIGS. 1 and 2, and the structure thereof will be described with reference to FIG.
FIGS. 1A to 1C and 2A to 2C are cross-sectional views taken along line AA in FIG. 1 (a) to 1 (c) and FIG.
(a)-(c) are also sectional views corresponding to the line BB and the line CC in FIG.

First, as shown in FIG. 1A, a LOCOS film 2 having a thickness of about 5000 ° is formed on a P-type silicon substrate 1 by selective oxidation.
(Element isolation film) A gate insulating film 3 having a thickness of about 150 ° is formed by thermal oxidation. Then, the contact hole 4 is formed by selectively removing the gate insulating film 3 in a region where the buried contact BC is to be formed by a photoetching process. Next, FIG.
As shown in FIG. 2B, a polysilicon film 5 having a thickness of about 1000 形成 is formed on the entire surface by the LPCVD method. The polysilicon film 5
A CVD oxide film (SiO2 film) having a thickness of about 1000 to 2000 mm may be formed thereon. Then, phosphorus is doped (deposited) in the polysilicon film 6 at a temperature of 800 ° C. and a deposition time of about 15 minutes. At this time, phosphorus diffuses from the contact hole 5 into the substrate 1 to form an N + type diffusion layer 6.

Next, as shown in FIG.
The polysilicon layers 4 and 5 are selectively etched to form the gate electrode 7a of the transfer transistor T1 and the gate electrode 7b of the driver transistor T3. At this time, the gate electrodes 7c and 7d (shown in FIG. 4) of the transfer transistor T4 and the driver transistor T3 are also formed at the same time. Further, the gate electrode 7a of the transfer transistor T1 is etched so as to extend on the silicon substrate 1, and contacts the N + type diffusion layer 6. And
Using the gate electrodes 7a and 7b as a mask, phosphorus ions (31P +)
For example, an acceleration energy of 50 KeV and an injection amount of 1 × 10 13 /
Ions are implanted into the silicon substrate 1 under the condition of cm2 to form N-type source / drain layers 8. Next, as shown in FIG. 2A, sidewall spacers 9 are formed on the side walls of the gate electrodes 7a and 7b. This sidewall spacer 9
Is formed by forming a CVD oxide film (SiO2 film) on the entire surface and etching back the entire surface. Then, FIG.
As shown in FIG. 1B, arsenic ions (75As +) are implanted into the silicon substrate 1 under the conditions of an acceleration energy of 60 KeV and an implantation amount of 1.times.10@15 / cm @ 2 to form an N + type source / drain layer 10. Thus, the drain layers (storage nodes ST1 and ST2) are formed by integrating the N− type drain layer 8, the N + type drain layer 10 and the N + type diffusion layer 6, and the N− type source layer 8 and the N + type -Source layer 10 is integrated to form a source layer. In this way, each transistor T1, T2, T3, T4
After the formation of the gate electrode and the source / drain layer, a drain layer (storage nodes ST1 and ST2) and a photoresist film 11 having an opening only at the end of the source layer are formed. The first ion implantation layer 12a and the second ion implantation layer 12b are formed by ion implantation of boron ions (11B +) so as to reach. Specific implantation conditions include the junction depth of the source / drain layers,
The thickness is determined in consideration of the thickness of the gate electrodes 7a and 7b. When the junction depth is 0.3 μm, the acceleration voltage is 130 KeV and the implantation amount is 1 ×
About 1014 / cm2 is suitable. In the figure, the right end of the photoresist film 11 is located near the end of the sidewall spacer 9, and boron ions (11B +) penetrate the sidewall spacer 9 and are locally located at the end of the source layer immediately below. It is implanted to become the second injection layer 12b (P-type layer). On the other hand, the left end of the photoresist film 11 is located at a position recessed from the sidewall spacer 9 so as to expose substantially the entire region of the drain layer. For this reason, the first ion-implanted layer 12a (P-type layer) is formed not only at the end of the drain layer (immediately below the sidewall spacer 9) but also in other regions. Here, in the region of the buried contact BC, since the gate electrode 7a extends on the drain layer, this serves as a mask for ion implantation. Under this portion of the gate electrode 7, the first ion implantation layer 12b is formed. Is not formed. However, in FIG.
As is clear from the plan view of the AM memory cell, the embedded contact B in the drain layer (storage nodes ST1 and ST2)
Since the area occupied by C is relatively small, the first ion-implanted layer 12a is large enough to increase the capacitance of the storage nodes ST1 and ST2. From the viewpoint of the operation of the N-channel transistors T1, T2, T3, T4, the source
Since there is a P-type layer at the end of the drain layer, a leak current between the source and the drain is suppressed at this portion, and a so-called punch-through breakdown voltage (source-drain breakdown voltage) is improved.

After the ion implantation, the photoresist film 1
In order to remove 1 and activate the source / drain layer and the injection layer, an appropriate annealing treatment may be added.

[0012]

According to the present invention, the first ion-implanted layer formed in the region extended from the end of the drain layer,
Since the capacitance (junction capacitance) added to the storage nodes ST1 and ST2 is increased, the resistance to the electron-hole pairs generated by the α-rays is less likely to occur, so that the soft error resistance can be improved.
Further, the second ion-implanted layer is formed at an end of the source layer, and the first and second ion-implanted layers can improve the punch-through resistance of each of the transistors T1, T2, T3, and T4. As a result, the size of the memory cell can be further reduced, and since the junction capacitance of the source layers of the transistors T1, T2, T3, T4 is made as small as possible, the operation speed of these transistors can be increased. Furthermore, the first and second ion-implanted layers 12a and 12b can be formed in one ion-implantation step. In a process in which pocket implantation for preventing punch-through has already been introduced, one There is also an advantage that it can be dealt with only by changing the design of the part and the manufacturing process is easy.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention and a method for manufacturing the same.

FIG. 2 is a cross-sectional view illustrating a semiconductor device of the present invention and a method for manufacturing the same.

FIG. 3 is a circuit diagram illustrating an SRAM cell.

FIG. 4 is a plan view illustrating an SRAM cell.

Claims (2)

[Claims] 1. A pair of driver transistors T2 and T3 having a gate electrode and a drain layer cross-connected to each other;
A pair of transfer transistors T1, T4 provided between the paired data lines D, * D and the respective drain layers, wherein the respective transistors T1, T2, T3, T4 are provided on the surface of the semiconductor substrate of the first conductivity type. A static semiconductor memory device in which a source layer and a drain layer of each of the transistors T1, T2, T3, T4 are formed of a second conductivity type diffusion layer, and each drain layer constitutes a storage node ST1, ST2. Wherein said storage node
First to increase the junction capacitance between ST1, ST2 and the substrate
A first ion implantation layer of conductivity type, and transistors T1, T2, T
3, the second of the first conductivity type provided at the end of each source layer of T4.
A static semiconductor memory device comprising: an ion implantation layer, wherein the first ion implantation layer is formed to extend from an end of the drain layer to another drain layer region. 2. A step of forming gate electrodes of the transistors T1, T2, T3, T4 on a surface of a semiconductor substrate of a first conductivity type, and forming a source layer and a drain layer on a surface of the substrate adjacent to the gate electrode. Forming a photoresist film having openings only at the ends of the drain layer (storage nodes ST1 and ST2) and the source layer; and forming a first photoresist film so as to reach the junction depth of the source / drain layer from the opening. 2. The method according to claim 1, wherein the first and second ion-implanted layers are formed by ion-implanting conductive impurities.