JPH11265888A - Planarizing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method that eliminate the need for coating and forming a photoresist in multiple layers and at the same time prevents the photoresist from being carbonized and remaining from the heat of dry etching in the resist etchback method for planarizing. SOLUTION: A photosensitive polyimide film 5 is formed on a CVD insulating film 4, where the photosensitive polyimide film 5 can be formed in a single coating process so that is can be as thick as 3 μm or more. Only a part 5a with a specific film thickness of the photosensitive polyimide film 5 is exposed by an exposure energy that is the minimum exposure energy required for completely exposing the photosensitive polyimide film 5 or less for eliminating only the exposed part 5a by development processing. Or after having the photosensitive polyimide film 5 exposed completely, the development treatment time is controlled for eliminating only the part corresponding to the specific film thickness. After the first etchback process, a second etchback process due to dry etching is made. Thus by doing so photosensitive polyimide is prevented from being carbonized by heat at dry etching, and hence facilitating the elimination of the remaining photosensitive polyimide film 5 after the etchback.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for planarizing a semiconductor device, which is particularly important in, for example, a multilayer wiring structure.

[0002]

2. Description of the Related Art As a method for planarizing an interlayer film of a semiconductor device, an etch back method using a photoresist (resist etch back method) is well known. This is because a photoresist is applied and formed on an interlayer insulating film such as a silicon oxide film on which an uneven surface is formed by a step structure of a lower layer, and the photoresist and the interlayer insulating film are entirely etched under the same etching rate. This is a method of performing etching. Since the photoresist, which is a coating film, has relatively good surface flatness, planarization reflecting the surface flatness is performed on the interlayer insulating film.

[0003]

However, when the aspect ratio of a step is increased due to recent miniaturization and high integration of a semiconductor device, a single-layer coating of a photoresist requires
Since a certain level of step is formed also on the surface of the photoresist, there has been a problem that sufficient planarization cannot be performed.

For example, Japanese Patent Application Laid-Open No. 7-230992 discloses
As disclosed in Japanese Patent Application Laid-Open Publication No. H10-157, photoresist is applied to two or more layers. However, this method requires a plurality of times of application of the photoresist, so that the process is not performed. Had the problem of increasing numbers.

Further, when a new resist film is applied on the resist film, the surface of the already formed resist film is dissolved by the organic solvent in the application liquid, thereby causing unevenness in application to the subsequent resist film. There was also a problem that occurred.

[0006] Further, the etchback method using a normal photoresist has the following problems. That is, during the etch-back process by dry etching, the wafer (substrate) surface temperature rises to around 200 ° C. due to the plasma in the etching chamber. For this reason, the photoresist applied for planarization is partially carbonized and remains,
They could not be removed by commonly used oxygen ashing or a chemical mixture of sulfuric acid and hydrogen peroxide solution.

Accordingly, an object of the present invention is to provide a method of planarizing a semiconductor device which does not necessarily need to form a multi-layered photoresist when performing planarization by an etch-back method and which does not cause the problem of photoresist carbonization. It is to provide.

[0008]

According to the present invention, there is provided a method for planarizing a semiconductor device, comprising the steps of: forming a lower layer structure of a semiconductor device; and forming an insulating film thereon so as to bury the lower layer structure. Forming a photosensitive polyimide film on the insulating film, exposing the entire surface of the photosensitive polyimide film, and developing the photosensitive polyimide film by a predetermined thickness. And a second etch-back step in which the photosensitive polyimide film and the insulating film are entirely etched by etching at substantially the same etching rate.

In one embodiment of the present invention, the photosensitive polyimide film is formed to a thickness of 3 μm or more.

In one embodiment of the present invention, the insulating film is formed by a chemical vapor deposition method.

In one embodiment of the present invention, a lower wiring layer in a multilayer wiring is formed as the lower layer structure.

In one embodiment of the present invention, when exposing the photosensitive polyimide film, only a predetermined thickness of the photosensitive polyimide film is exposed with energy equal to or less than the minimum exposure energy required for complete exposure, and then developed. In the processing, only the exposed film thickness is removed.

In one embodiment of the present invention, after the photosensitive polyimide film is substantially completely exposed, only a predetermined thickness of the photosensitive polyimide film is removed by controlling the development processing time.

In one embodiment of the present invention, after the second etch back step, any one selected from the group consisting of oxygen ashing, an amine-based organic solvent, a mixed chemical solution of sulfuric acid and hydrogen peroxide, and concentrated sulfuric acid. Is performed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to preferred embodiments.

[First Embodiment] First, a first embodiment of the present invention will be described with reference to FIGS.

FIGS. 1 and 2 are schematic sectional views showing a method of manufacturing a multilayer wiring structure according to the first embodiment in the order of steps, and FIG. 3 corresponds to the steps of FIGS. 1 (a) to 1 (d). It is a flowchart.

First, as shown in FIG. 1A, a lower wiring layer 3 is formed in a predetermined pattern on a silicon semiconductor substrate 1 via a base insulating film 2 such as a silicon oxide film or a silicon nitride film. (Step S1 in FIG. 3). The lower wiring layer 3 is made of, for example, aluminum (Al), tungsten silicide (WSi), a polysilicon film, or the like.

When a MOS transistor structure is formed as a lower layer structure of a semiconductor device instead of a lower wiring layer of a multilayer wiring structure as in this example, for example, FIG.
(A) A gate insulating film of a MOS transistor is formed instead of the base insulating film 2 and a gate electrode wiring of the MOS transistor is formed instead of the lower wiring layer 3.

Next, a silicon oxide film, a silicon nitride film and the like are formed on the entire surface by a chemical vapor deposition (CVD) method to form a first interlayer insulating film 4 (step S2 in FIG. 3). The first interlayer insulating film 4 formed by the CVD method has poor step coverage, and irregularities corresponding to the base step structure are formed on the surface as shown in the figure.

Then, next, a photosensitive polyimide film 5 having a thickness of, for example, 3 μm or more is formed on the first interlayer insulating film 4.
More preferably, a thick film having a thickness of 5 μm or more is formed by coating (Step S3 in FIG. 3). The photosensitive polyimide has a characteristic that, unlike an ordinary photoresist, it is easy to apply a thick film in a single step. Therefore, even in a single application step, a thick film having a thickness of 3 μm or more can be formed, and a flat surface which is not affected by the underlying step structure can be obtained because of the thick film. If the increase in the number of steps does not matter, it is of course possible to apply the solution in a plurality of times.

Next, as shown in FIG. 1B, after baking for removing the solvent, for example, a single-wavelength g-line with an exposure wavelength λ ≒ 436 nm or a single-wavelength i-line with an exposure wavelength λ ≒ 365 nm is used. Using any one of the exposure devices, the photosensitive polyimide film 5
Is performed (step S4 in FIG. 3).

At this time, in the first embodiment, the minimum energy E _th (exposure threshol) required to substantially completely expose the entire thickness of the photosensitive polyimide film 5 is obtained.
d) Exposure is performed with the following energy, and the exposure time is controlled to expose only the predetermined thickness portion 5a of the photosensitive polyimide film 5 as shown in the figure.

Next, as shown in FIG. 1C, a developing process is performed using a developing solution composed of an alkaline aqueous solution to remove only the photosensitive portion 5a of the photosensitive polyimide film 5 (Step S5 in FIG. 3).

Next, as shown in FIG. 1D, the entire surface is dry-etched under such etching conditions that the photosensitive polyimide film 5 and the first interlayer insulating film 4 have substantially the same etching rate. (Step S6 in FIG. 3).

For example, when the first interlayer insulating film 4 is a silicon oxide film, if dry etching is performed under the following conditions,
The etching rates of the photosensitive polyimide film 5 and the first interlayer insulating film 4 are both about 500 ° / min. Reaction gas: HCl / HBr = 200 [SCCM] / 20 [SCCM] Pressure: 600 mTorr Power: 300 W

As described above, the photosensitive polyimide film 5 is formed into a thick film and a flat surface thereof is obtained. Then, the photosensitive polyimide film 5 is thinned in a first etch-back step by exposure and development. Thereafter, final planarization is performed in a second etch-back step by dry etching. Therefore, even if the photosensitive polyimide film 5 is formed in a thick film, the processing time of dry etching does not need to be lengthened, and as a result, compared to the case where the entire photosensitive polyimide film 5 having a thick film is removed by dry etching. Thus, the overall processing time can be shortened.

The photosensitive polyimide generally has a high glass transition temperature of about 280 ° C., and therefore, even if the surface temperature of the wafer (substrate) rises during dry etching,
It does not carbonize unlike ordinary photoresist. For this reason, the photosensitive polyimide film 5 remaining after the second etch-back step is replaced with, for example, the lower wiring layer 3 made of Al or WS.
In the case of a metal film such as i, it can be easily removed by oxygen ashing or an organic amine organic solvent such as alkylpyrrolidone. When the lower wiring layer 3 is not made of a metal film, the lower wiring layer 3 is removed by, for example, a mixed solution of sulfuric acid and hydrogen peroxide heated to about 140 ° C. or concentrated sulfuric acid heated to about 80 ° C. be able to. Therefore, if necessary, after the second etch-back step, these processes are performed in accordance with the material of the lower wiring layer 3 for the purpose of removing the remaining polyimide film and cleaning.

Next, as shown in FIG.
A second interlayer insulating film 7 such as a silicon oxide film is formed.

Next, as shown in FIG. 2B, a via hole 7a reaching the lower wiring layer 3 is formed at a predetermined position of the second interlayer insulating film 7 by photolithography and dry etching.

Next, for example, as shown in FIG.
After the via hole 7a is filled with a tungsten (W) plug 8 or the like, an upper wiring layer 9 is pattern-formed thereon.

In the first embodiment described above, the photosensitive polyimide film 5 is used in the etch-back process for planarization.
Is used, for example, the photosensitive polyimide film 5 having a thickness of 3 μm or more can be formed in one application step. Therefore, a plurality of application steps are not particularly required, and simplification of the steps can be achieved.

Further, since the thick photosensitive polyimide film 5 is thinned in a first etch-back process by a development process after exposure, a second etch-back process by dry etching is performed. The second etch-back step, and thus the entire etch-back step, can be shortened.

Further, since the photosensitive polyimide film 5 does not carbonize even when the substrate surface temperature rises during dry etching, the photosensitive polyimide film 5 remaining after the etch back is removed.
For example, oxygen ashing, an organic amine organic solvent such as alkylpyrrolidone, a mixed chemical solution of sulfuric acid and hydrogen peroxide heated to about 140 ° C., or concentrated sulfuric acid heated to about 80 ° C. Can be removed.

Further, in the first embodiment, the photosensitive polyimide film 5 is made thinner by controlling the exposure energy and the exposure time, respectively, so that only the predetermined thickness portion 5a of the photosensitive polyimide film 5 is exposed. Thereafter, since the development is carried out by removing only the photosensitive portion 5a, the thickness of the photosensitive polyimide film 5 can be easily and relatively accurately controlled.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG.

In the second embodiment, parts corresponding to those in the above-described first embodiment are denoted by the same reference numerals as those in the above-described first embodiment.

First, as shown in FIG.
Also in the embodiment, similar to the above-described first embodiment,
A lower wiring layer 3 is formed in a predetermined pattern on a silicon semiconductor substrate 1 via a base insulating film 2 such as a silicon oxide film or a silicon nitride film. When a MOS transistor structure is formed as a lower layer structure of the semiconductor device, for example, a gate insulating film of the MOS transistor is used instead of the base insulating film 2 and a gate electrode wiring of the MOS transistor is used instead of the lower wiring layer 3. Form each.

Next, a silicon oxide film, a silicon nitride film or the like is formed on the entire surface by a CVD method to form a first interlayer insulating film 4.
After that, a photosensitive polyimide film 5 is formed thereon.

Next, for example, as shown in FIG.
The entire surface exposure 6 of the photosensitive polyimide film 5 is performed using a single wavelength of the g-line or a single wavelength of the i-line. In the second embodiment, as shown in FIG. The photosensitive portion 5a is completely exposed to light.

Then, as shown in FIG.
The developing process is performed using a developing solution composed of an alkaline aqueous solution. At this time, the developing time is controlled to remove only a predetermined thickness of the completely exposed photosensitive polyimide film 5a.

Next, as shown in FIG. 4D, the etching conditions (for example, the first etching rate) are set such that the exposed photosensitive polyimide film 5a and the first interlayer insulating film 4 have substantially the same etching rate. Dry etching is performed on the entire surface under the same conditions as those exemplified in the first embodiment.

Thereafter, although not shown, the first
2 (a) to 2 (c) of the embodiment are performed to form a multilayer wiring structure.

Also in the second embodiment, since the photosensitive polyimide film 5 is used in the etch-back step for flattening, for example, the photosensitive polyimide film having a thickness of 3 μm or more can be formed in one coating step. 5 can be formed. Therefore, a plurality of application steps are not particularly required, and simplification of the steps can be achieved.

After the thick photosensitive polyimide film 5 is thinned in a first etch-back process by a development process after exposure, a second etch-back process by dry etching is performed. The second etch-back step, and thus the entire etch-back step, can be shortened.

Furthermore, since the photosensitive polyimide film 5 does not carbonize even when the substrate surface temperature rises during dry etching, the photosensitive polyimide film 5 remaining after the etch back is removed.
For example, oxygen ashing, an organic amine organic solvent such as alkylpyrrolidone, a mixed chemical solution of sulfuric acid and hydrogen peroxide heated to about 140 ° C., or concentrated sulfuric acid heated to about 80 ° C. Can be removed.

Further, in the second embodiment, after the photosensitive polyimide film 5 is substantially completely exposed to light, the film is thinned by control in the developing process, so that special control in the exposure process is performed. Is not required, so that the exposure step can be simplified.

The first and second embodiments described above can be used in combination with each other.

[0049]

According to the present invention, flatness is excellent, and
A flattening etch-back step that does not cause a problem such as residual carbonized resist can be easily performed without increasing the number of steps and the processing time.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a planarization method according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a planarization method according to a first embodiment of the present invention in the order of steps.

FIG. 3 is a flowchart of a main part of the flattening method according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a planarization method according to a second embodiment of the present invention in the order of steps.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon semiconductor substrate 2 base insulating film 3 lower wiring layer 4 first interlayer insulating film 5 photosensitive polyimide film 5 a photosensitive portion 6 overall exposure 7 second interlayer insulating film 7 a via hole 8 tungsten (W) plug 9 upper wiring layer

Claims (7)

[Claims] A step of forming a lower layer structure of the semiconductor device; a step of forming an insulating film thereon so as to bury the lower layer structure; and a step of forming a photosensitive polyimide film on the insulating film. A step of exposing the entire surface of the photosensitive polyimide film, a first etch-back step of developing the photosensitive polyimide film and removing only a predetermined thickness thereof, and the photosensitive polyimide film and the insulating film. And a second etch-back step of etching the entire surface by etching having substantially the same etching rate. 2. The method according to claim 1, wherein the photosensitive polyimide film is formed to a thickness of 3 μm or more. 3. The method according to claim 1, wherein the insulating film is formed by a chemical vapor deposition method. 4. The multi-layer wiring according to claim 1, wherein a lower wiring layer is formed as the lower layer structure.
4. The method for planarizing a semiconductor device according to claim 1. 5. When exposing the photosensitive polyimide film,
After exposing only a predetermined thickness of the photosensitive polyimide film with energy equal to or less than the minimum exposure energy required for complete exposure, a developing process removes only the exposed thickness. Item 5. The method for planarizing a semiconductor device according to any one of Items 1 to 4. 6. The method according to claim 1, wherein after the photosensitive polyimide film is substantially completely exposed, only a predetermined thickness of the photosensitive polyimide film is removed by controlling a development processing time. 2. The method for planarizing a semiconductor device according to claim 1. 7. After the second etch-back step, a treatment is performed by any one selected from the group consisting of oxygen ashing, an amine organic solvent, a mixed chemical solution of sulfuric acid and hydrogen peroxide, and concentrated sulfuric acid. 7. The method for planarizing a semiconductor device according to claim 1, wherein: