JPH11262011A - Device for decoding animation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To selectively obtain two kinds of compounding with different image qualities by generating first reproduction picture data compressed in a horizontal direction, second reproduction image data compressed in the horizontal and vertical directions and respective kinds of compounding data based on first and second data and changing-over first and second compounding data generating means. SOLUTION: A first vertical interpolation circuit 9 interpolates a horizontal line, thinned by a vertical thinning circuit 6 with respect to reference image data which is read from a first reference image memory 7 and generates reference image data by macro-block unit, when a compounding mode is of low image quality. The second vertical interpolation circuit 10 executes interpolation in the vertical direction with respect to reference picture data by macro-block unit, which is read from a second reference picture memory 8 and generates reference picture data by macro-block unit, when the compounding mode is of low picture quality. A CPU 20 controls switches 31-39, based on a control signal and corresponds to the selection of the image quality.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture decoding apparatus suitable for decoding a signal which has been compression-encoded by the MPEG system to obtain a reproduced picture having a resolution lower than that of an original picture.

[0002]

2. Description of the Related Art A moving picture expert group (MPEG) method has been conventionally known as an image coding method for compressing and coding image data in the field of digital TV and the like.

A typical MPEG system is MPEG.
1 and MPEG2. In MPEG1, only progressively scanned (non-interlaced) images were handled.
In PEG2, not only images of progressive scanning but also images of interlaced scanning have been handled.

[0004] Motion-compensated prediction (temporal compression), DCT (spatial compression), and entropy coding (variable-length coding) are employed for encoding these MPEGs. MP
In EG encoding, first, 16 (the number of pixels in the horizontal direction) × 1
For each macroblock having a size of 6 (the number of pixels in the vertical direction), prediction coding in the time axis direction (frame prediction coding in MPEG1 and frame prediction coding or field prediction coding in MPEG2) is performed. 3 pictures of I picture, P picture and B picture corresponding to the predictive coding method
There are different image types. In the following, a description will be given of frame predictive coding as an example.

(1) I picture: A picture coded from only the information in the frame and generated without performing inter-frame prediction. All macroblock types in the I picture are Intra-frame predictive coding in which coding is performed using only information.

(2) P picture: A picture formed by performing prediction from an I or P picture. In general, the macroblock type in a P picture is an intra-frame code which is encoded only with intra-frame information. And forward inter-frame prediction coding predicted from a past reproduced image.

(3) B picture: a picture made by bidirectional prediction, which generally includes the following macroblock types. a. Intra-frame predictive coding using only intra-frame information b. Forward inter-frame predictive coding predicted from past reproduced images c. Reverse interframe predictive coding predicting from the future d. Interpolative inter-frame prediction coding by both forward and backward prediction Here, the interpolative inter-frame prediction refers to averaging two predictions, forward prediction and backward prediction, between corresponding pixels.

[0008] In the MPEG encoder, the image data of the original image is 16 (the number of pixels in the horizontal direction) x 16 (the number of pixels in the vertical direction).
Is divided into macroblock units of size. For a macroblock whose macroblock type is not intra-frame predictive coding, inter-frame prediction according to the macroblock type is performed, and prediction error data is generated.

The image data for each macroblock unit (when the macroblock type is intra-frame predictive coding) or prediction error data (when the macroblock type is inter-frame predictive coding) is 8 × 8 The image data of each sub-block is divided into four sub-blocks, and a two-dimensional discrete cosine transform (DCT), which is a type of orthogonal transform, is performed on the image data of each sub-block based on Equation 1. That is, as shown in FIG.
Each DCT (orthogonal transform) coefficient F (u, v) in the uv space (u: horizontal frequency, v: vertical frequency) is obtained based on each data f (i, j) in a block of size.

[0010]

(Equation 1)

In MPEG1, the DCT contains a frame D
Although only the CT mode is used, the MPEG2 frame structure allows switching between the frame DCT mode and the field DCT mode in macroblock units. However, in the field structure of MPEG2, the field DC
Only T mode.

In the frame DCT mode, a 16 × 16 macro block is divided into four and divided into upper left 8 × 8 blocks, upper right 8 × 8 blocks, lower left 8 × 8 blocks, and lower right 8 × 8 blocks. DCT is performed for each block.

On the other hand, in the field DCT mode, 16
An 8 × 8 data group consisting of only odd lines in the left half 8 (the number of pixels in the horizontal direction) × 16 (the number of pixels in the vertical direction) of the left half of the × 16 macroblock, and in the 8 × 16 block of the left half An 8 × 8 data group consisting of only even-numbered lines, an 8 × 8 data group consisting only of odd-numbered lines in a right half of 8 (number of horizontal pixels) × 16 (number of vertical pixels) blocks, and a right half of 8 For each data group of an 8 × 8 data group consisting only of even lines in a × 16 block, D
CT is performed.

[0014] The DCT coefficients obtained as described above are quantized to generate quantized DCT coefficients. The quantized DCT coefficients are zigzag-scanned or alternate-scanned, arranged one-dimensionally, and encoded by a variable-length encoder. The MPEG encoder outputs control information including information indicating a macroblock type and a variable length code of a motion vector together with a variable length code of a transform coefficient obtained by the variable length encoder.

FIG. 4 is a block diagram showing the configuration of the MPEG decoder.

The variable-length code of the transform coefficient is sent to a variable-length decoder 101. Control signals including the macroblock type are sent to CPU 110. The variable length code of the motion vector is sent to the variable length decoder 109 and decoded. The motion vector obtained by the variable length decoder 109 is sent to the first reference image memory 106 and the second reference image memory 107 as a control signal for controlling the cutout position of the reference image.

The variable length decoder 101 decodes a variable length code of a transform coefficient. The inverse quantizer 102 converts the transform coefficients (quantized DCTs) obtained from the variable-length decoder 101
) Is inversely quantized and converted into DCT coefficients.

The inverse DCT circuit 103 includes an inverse quantizer 102
The DCT coefficient sequence generated in step (1) is returned to DCT coefficients in units of 8 × 8 sub-blocks, and 8 × 8 inverse DCT is performed based on the inverse transform equation shown in Expression 2. That is, as shown in FIG. 5, based on an 8 × 8 DCT coefficient F (u, v),
Data f (i, j) in units of 8 × 8 sub-blocks is obtained. Further, data f (i, i,
Based on j), reproduced image data or prediction error data in one macroblock unit is generated.

[0019]

(Equation 2)

The prediction error data generated in the macroblock unit by the inverse DCT circuit 103 is added with reference image data corresponding to the macroblock type by the adder 104.
And reproduced image data is generated. The reference image data is added to the adder 104 via the switch 112.
Sent to However, if the data output from the inverse DCT circuit 103 is reproduced image data for the intra-frame prediction code, the reference image data is not added.

The image data in macroblock units obtained by the inverse DCT circuit 103 or the adder 104 is
If the image data is reproduction image data for a picture, the reproduction image data is sent to the switch 113.

If the reproduced image data in macroblock units obtained by the inverse DCT circuit 103 or the adder 104 is reproduced image data for an I picture or a P picture, the reproduced image data is set to the switch 11.
1 is stored in the first reference image memory 106 or the second reference image memory 107. The switch 111
It is controlled by the CPU 110.

The averaging unit 108 includes memories 106 and 107
The reference image data used in the interpolative inter-frame predictive encoding is generated by averaging the reproduced image data read from.

The switch 112 is controlled by the CPU 110 as follows. If the data output from the inverse DCT circuit 103 is reproduced image data for the intra-frame prediction code, the common terminal of the switch 112 is switched to the ground terminal.

When the data output from the inverse DCT circuit 103 is prediction error data for a forward inter-frame prediction code or prediction error data for a reverse inter-frame prediction code, the common terminal of the switch 112 Switching is performed so as to select either the terminal to which the output of the first reference image memory 106 is sent or the terminal to which the output of the second reference image memory 107 is sent. When the reference images are read from the reference image memories 106 and 107, the cut-out position of the reference image is controlled based on the motion vector from the variable length decoder 109.

When the data output from the inverse DCT circuit 103 is prediction error data for an interpolative inter-frame prediction code, the common terminal of the switch 112 is connected to the averaging unit 1
It is switched to select the terminal to which the output of 08 is sent.

The switch 113 reproduces the reproduced picture data for the B picture sent from the adder 104, the reproduced picture data for the I picture or P picture stored in the reference picture memory 106, and the reproduced picture data stored in the reference picture memory 107. The CPU 110 controls the reproduced image data for the I picture or the P picture so as to be output in the same order as the order of the original images. The image data output from the decoder is provided to the monitor device, and the original image is displayed on the display screen of the monitor device.

[0028]

By the way, when obtaining a reproduced image having a lower resolution than the resolution of the original image, the present applicant uses only a part of the DCT coefficients to perform inverse DCT.
A method (hereinafter, referred to as a first method) of generating a reproduced image having a lower resolution than the original image by generating a reproduced image based on the image obtained by performing the above is developed.

Further, the present applicant generates a first reproduced image based on an image obtained by performing inverse DCT using only a part of the DCT coefficients, and generates a first reproduced image based on the first reproduced image. A method for generating a second reproduced image having a lower resolution than the original image by performing at least the vertical direction thinning out of the horizontal direction thinning and the vertical direction thinning has been developed. Neither the first method nor the second method is a known technique (prior art).

When comparing the first method and the second method,
Although the image quality obtained by the reproduced image is higher in the first method, the capacity of the reference image memory can be smaller in the first method. Therefore, it is convenient to have a decoder that can select any of the methods according to the application.

An object of the present invention is to provide a moving picture reproducing apparatus which can select two kinds of decoding in which the picture quality of a decoded picture is different.

[0032]

According to a first aspect of the present invention, there is provided a moving picture decoding apparatus comprising: a picture obtained by performing an inverse orthogonal transform using only coefficients in a low frequency band portion of an orthogonal transform coefficient; A first reproduced image data generating means for generating first reproduced image data in which the horizontal direction is compressed to 基 づ い based on the first direction, thinning out the first reproduced image data to 垂直 in the vertical direction, And second reproduction image data generating means for generating second reproduction image data in which the vertical direction is compressed to １ ／, respectively, based on the first reproduction image generated by the first reproduction image data generation means. First decoded data generating means for generating decoded data, second decoded data generating means for generating decoded data based on the second reproduced image generated by the second reproduced image data generating means, And the first Characterized in that it comprises a switching means for switching the issue data generation means and the second decoded data generating means.

A second moving picture decoding apparatus according to the present invention removes a coefficient in a high frequency part of a horizontal frequency from orthogonal transform coefficients of a block of a predetermined size obtained from an input signal, thereby obtaining a transform coefficient. By performing a reverse orthogonal transform using the coefficient reduced by the coefficient reducing circuit and the coefficient reduced by the coefficient reducing circuit, the horizontal direction is reduced by 1 / block for each block unit.
(2) an inverse orthogonal transform circuit for obtaining reproduced image data or time axis prediction error data compressed to 2; a horizontal direction of 1/1/2 based on time axis prediction error data obtained by the inverse orthogonal transform circuit and predetermined reference image data; The reproduction image data (hereinafter, referred to as the first reproduction image data) obtained by the adder, the inverse orthogonal transform circuit, or the adder that generates the reproduction image data compressed to 2 is thinned in the vertical direction by 、, A vertical thinning circuit for generating the second reproduced image data in which the horizontal direction and the vertical direction are each compressed to そ れ ぞ れ, and the decoding mode is set to the first reproduced image data and the second reproduced image data. A first switching unit that outputs first reproduced image data when the first decoding mode is set, and outputs second reproduced image data when the decoding mode is the second decoding mode; Switch for sending image data output from the first reference image memory to the first reference image memory or the second reference image memory, and a vertical thinning circuit for the image data output from the first reference image memory A first vertical interpolation circuit for interpolating the drawn horizontal line,
A second vertical interpolation circuit for interpolating horizontal lines thinned out by the vertical thinning circuit with respect to image data output from the second reference image memory, and an image output from the first reference image memory When the decoding mode is the first decoding mode among the data and the image data output from the first vertical interpolation circuit, the image data output from the first reference image memory is selected, and the decoding mode is set to the second decoding mode. In the case of the decoding mode, second switching means for selecting image data output from the first vertical interpolation circuit, image data output from the second reference image memory, and output from the second vertical interpolation circuit. If the decoding mode is the first decoding mode, the image data output from the second reference image memory is selected, and if the decoding mode is the second decoding mode, the second vertical A third switching unit for selecting image data output from the circuit, an averaging circuit for averaging the image data output from the second switching unit and the image data output from the third switching unit, Switching between the image data output from the switching means, the image data output from the third switching means, the image data output from the averaging circuit, and the ground voltage, and sending the reference image data to the adder as reference image data. A switch, and an output image data switch for switching and outputting image data output from the first switching unit, image data output from the first reference image memory, and image data output from the second reference image memory It is characterized by having.

A third moving picture decoding apparatus according to the present invention removes coefficients in a high frequency portion of a horizontal frequency from orthogonal transform coefficients of a predetermined size obtained from an input signal in block units. By performing a reverse orthogonal transform using the coefficient reduced by the coefficient reducing circuit and the coefficient reduced by the coefficient reducing circuit, the horizontal direction is reduced by 1 / block for each block unit.
(2) an inverse orthogonal transform circuit for obtaining reproduced image data or time axis prediction error data compressed to 2; a horizontal direction of 1/1/2 based on time axis prediction error data obtained by the inverse orthogonal transform circuit and predetermined reference image data; The reproduction image data (hereinafter, referred to as the first reproduction image data) obtained by the adder, the inverse orthogonal transform circuit, or the adder that generates the reproduction image data compressed to 2 is thinned in the vertical direction by 、, A vertical thinning circuit for generating the second reproduced image data in which the horizontal direction and the vertical direction are each compressed to そ れ ぞ れ, and the decoding mode is set to the first reproduced image data and the second reproduced image data. A first switching unit that outputs first reproduced image data when the first decoding mode is set, and outputs second reproduced image data when the decoding mode is the second decoding mode; Memory connection input terminal and first memory connection output terminal for connecting a memory for storage, second memory connection input terminal and second memory connection output terminal for connecting a second reference image memory A memory selection switch for sending image data output from the first switching means to the first memory connection input terminal or the second memory connection input terminal, and image data output from the first memory connection output terminal A first vertical interpolation circuit for interpolating a horizontal line thinned by a vertical thinning circuit with respect to
A second vertical interpolation circuit for interpolating horizontal lines thinned out by the vertical thinning circuit with respect to image data output from the second memory connection output terminal, and output from the first memory connection output terminal. When the decoding mode is the first decoding mode, the image data output from the first memory connection output terminal is selected from the image data output from the first vertical interpolation circuit and the image data output from the first vertical interpolation circuit. Is the second decoding mode, the second switching means for selecting the image data output from the first vertical interpolation circuit, the image data output from the second memory connection output terminal, and the second vertical interpolation When the decoding mode is the first decoding mode among the image data output from the circuit, the image data output from the second memory connection output terminal is selected, and the decoding mode is the second decoding mode. In this case, the third switching means for selecting the image data output from the second vertical interpolation circuit, the average of the image data output from the second switching means and the image data output from the third switching means. Averaging circuit, the second
Switching between the image data output from the switching means, the image data output from the third switching means, the image data output from the averaging circuit, and the ground voltage, and sending the reference image data to the adder as reference image data. Switch, image data output from the first switching means, image data output from the first memory connection output terminal, and output image data output by switching between image data output from the second memory connection output terminal A changeover switch is provided.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an MPEG decoder will be described below with reference to the drawings.

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows the configuration of the MPEG decoder.

In the MPEG decoder, there are a high image quality mode and a low image quality mode as decoding modes. The decoding mode is set by the user or the manufacturer.

The MPEG decoder includes an integrated circuit 50, and a first reference image memory 7 and a second reference image memory 8 connected to the integrated circuit 50. The integrated circuit 50 is provided with an input terminal 61 and an output terminal 62 for connecting a first reference image memory, and an input terminal 91 and an output terminal 92 for connecting a second reference image memory.

Input terminal 6 for connection of memory for first reference image
The first main memory 71 is connected to 1 and the output terminal 62. A second main memory 81 is connected to the input terminal 91 and the output terminal 92 for connecting the second reference image memory.

When the high image quality mode is set as the decoding mode, a first additional memory 72 is connected to a first main memory 71 and a second main memory 81 as shown in FIG.
Is connected to the second additional memory 82. When the low image quality mode is set as the decoding mode, there is no need to connect these additional memories 72 and 82.

That is, when the high image quality mode is set as the decoding mode, the first reference image memory 7 is composed of the first main memory 71 and the first additional memory 72, and the second reference image memory 8 comprises a second main memory 81 and a second additional memory 82. When the low image quality mode is set as the decoding mode, the first reference image memory 7 includes only the first main memory 71, and the second reference image memory 8 includes only the second main memory 81. Is done.

The integrated circuit 50 includes a variable length decoder 1, an inverse quantizer 2, a horizontal high frequency coefficient removing circuit 3, an inverse DCT circuit 4,
Adder 5, first switch 31, vertical thinning circuit 6, second switch 32, third switch 33, input terminal 61 and output terminal 62 for connecting a first reference image memory, for connecting a second reference image memory Input terminal 91 and output terminal 92,
Fourth switch 34, first vertical interpolation circuit 9, fifth switch 35, sixth switch 36, second vertical interpolation circuit 10, seventh switch
Switch 37, averaging unit 11, eighth switch 38, ninth
It includes a switch 39, a variable length decoder 12, a vector value conversion circuit 13, a format conversion circuit 14, and a CPU 20.

The variable length code of the transform coefficient is sent to the variable length decoder 1. The control signal including the macroblock type is sent to the CPU 20. Further, a signal indicating the decoding mode set by the user or the manufacturer is set to the CPU 2 at the time of initial setting.
Sent to 0.

The variable length code of the motion vector is sent to the variable length decoder 12 and decoded. Variable length decoder 12
The motion vector obtained by the above is sent to the vector value conversion circuit 13. The vector value conversion circuit 13 includes a CPU
From 20, a signal indicating the decoding mode is sent as a control signal.

When the decoding mode is the high image quality mode, the vector value conversion circuit 13 converts the input motion vector so that its horizontal size becomes １ ／. When the decoding mode is the low image quality mode, the vector value conversion circuit 13 converts the input motion vector so that its horizontal and vertical sizes are １ ／ each.

The motion vector obtained by the vector value conversion circuit 13 is sent to the first reference image memory 7 and the second reference image memory 8 as a control signal for controlling the cut-out position of the reference image.

The variable length decoder 1 decodes a variable length code of a transform coefficient. The inverse quantizer 2 inversely quantizes the transform coefficients (quantized DCT coefficients) obtained from the variable length decoder 1 and converts them into DCT coefficients. As shown in FIG. 2A, the horizontal high-frequency coefficient removal circuit (coefficient reduction circuit) 3 converts the DCT coefficient sequence generated by the inverse quantizer 2 into 8 (number of pixels in the horizontal direction) × 8 (pixels in the vertical direction). ) Of 8 × 8 DCT coefficients F (u, v) (where u =
0, 1,... 7, v = 0, 1,... 7), and the DCT coefficient of the high frequency portion of the horizontal frequency of each sub-block is removed, and as shown in FIG. DCT coefficients F in the number of frequency directions u) × 8 (vertical frequency direction v)
(U, v) (where u = 0, 1,... 3, v = 0, 1,
... 7) is converted.

The inverse DCT circuit 4 applies 4 × 8 inverse DCT as shown in Expression 3 to the 4 × 8 DCT coefficients generated by the horizontal high-frequency coefficient removal circuit 3, and obtains the result shown in FIG. ), The original data in units of sub-blocks is 1 /
Data f (i, j) consisting of 4 (the number of pixels in the horizontal direction) × 8 (the number of pixels in the vertical direction) compressed into 2 (where i = 0, 1,... 3, j = 0, 1, 1) .. 7) are generated.

[0050]

(Equation 3)

Further, one 8 × 16 macroblock in which the horizontal direction is compressed to て based on the image data corresponding to the four sub-block units constituting one macroblock obtained in this way. Generate reproduced image data or prediction error data in units. Therefore, the inverse DC
The amount of data in macroblock units obtained by the T circuit 4 is half the amount of image data in macroblock units of the original image.

The prediction error data generated by the inverse DCT circuit 4 in units of 8 × 16 macroblocks in which the horizontal direction is compressed to １ ／ is provided with reference image data (in the horizontal direction, corresponding to the macroblock type). The adder 5 adds the half-compressed 8 × 16 macroblock-unit reference image data) to generate reproduced image data. The reference image data is sent to the adder 5 via the eighth switch 38. However, if the image data output from the inverse DCT circuit 4 is reproduced image data for the intra-frame prediction code, the reference image data is not added.

First switch 31 and second switch 32
When the decoding mode is the high image quality mode, the first reproduced image data is transmitted to the third switch 33 and the ninth switch 3
9, when the decoding mode is the low image quality mode, the first reproduced image data is sent to the vertical thinning circuit 6 and the second reproduced image data obtained by the vertical thinning circuit 6 is sent to the third thinning circuit. It is controlled by the CPU 20 so that it is sent to the switch 33 and the ninth switch 39.

The vertical thinning circuit 6 receives the received 8 × 16
Is converted into second reproduced image data in macroblock units of 8 × 8 by thinning out the first reproduced image data in macroblock units by 1/2 in the vertical direction. Therefore, the amount of image data in macroblock units obtained by the vertical thinning circuit 6 is １ ／ of the amount of image data in macroblock units of the original image.

The vertical thinning by the vertical thinning circuit 6 is as follows.
As shown in FIG. 3, this is performed by thinning out the horizontal lines of the first reproduced image data every two lines. 8 obtained by the inverse DCT circuit 4 or the adder 5
In the first reproduced image data of × 16 macroblock units, as shown in FIG. 3A, a horizontal line of an odd field (shown by a solid line) and a horizontal line of an even field (shown by a broken line) extend in the vertical direction. Appear alternately. Therefore, in order to uniformly include the horizontal lines of the odd-numbered fields and the horizontal lines of the even-numbered fields in the decimated image, the horizontal lines of the first reproduced image data are changed as shown in FIG. In other words, every two lines are thinned out.

When the reproduced image data sent from the second switch 32 to the ninth switch 39 is reproduced image data for a B picture, the reproduced image data for the B picture is converted by the ninth switch 39 into the format conversion circuit 14. Is output to

When the reproduced image data sent to the third switch 33 is the reproduced image data for an I picture or a P picture, the third reference image memory 7 or the second reference image memory 8 The reproduced image data is stored in the memory selected by the switch 33.

When the decoding mode is the low image quality mode, the second reproduced image data is stored in the first reference image memory 7 (main memory 71) or the second reference image memory 8 (main memory 8).
1), the first reference image memory 7 (main memory 71) and the second reference image memory 8 (main memory 8)
As 1), a memory having a capacity 1/4 that of the conventional memory can be used.

When the decoding mode is the high image quality mode, the first reproduced image data is stored in the first reference image memory 7 (main memory 71 + additional memory 72) or the second reference image memory 8 (main memory 81 + additional memory). 82), the first reference image memory 7 (main memory 71 + additional memory 72) and the second reference image memory 8 (main memory 81)
As the + additional memory 82), a memory having half the capacity of the conventional memory can be used.

Fourth switch 34 and fifth switch 35
When the decoding mode is the high quality mode, the 8 × 16 macroblock unit image data read from the first reference image memory 7 is read by the eighth switch 38 and the averaging unit 1.
1, when the decoding mode is the low image quality mode, the image data in 8 × 8 macroblock units read from the first reference image memory 7 is sent to the first vertical interpolation circuit 9 and The CPU 20 transmits the image data in units of 8 × 16 macroblocks obtained by the first vertical interpolation circuit 9 to the eighth switch 38 and the averaging unit 11.
Is controlled by

Similarly, when the decoding mode is the high image quality mode, the sixth switch 36 and the seventh switch 37
When the decoding mode is the low image quality mode, the second reference image data is transmitted so that the 8 × 16 macroblock unit image data read from the reference image memory 8 is sent to the eighth switch 38 and the averaging unit 11. 8 × read from memory 8
The image data in units of 8 macroblocks is sent to the second vertical interpolation circuit 10, and the image data in units of 8 × 16 macroblocks obtained by the second vertical interpolation circuit 10 is sent to the eighth switch 38 and averaged. It is controlled by the CPU 20 so as to send it to the conversion unit 11.

When the decoding mode is the low image quality mode, the first vertical interpolation circuit 9 performs vertical interpolation on the reference image data of 8 × 8 macroblock units read from the first reference image memory 7. Direction interpolation, that is, by interpolating the horizontal line thinned out by the vertical thinning circuit 6 to obtain 8 × 16
Is generated for each macroblock.

When the decoding mode is the low image quality mode, the second vertical interpolation circuit 10 applies the vertical image processing to the 8 × 8 macroblock unit reference image data read from the second reference image memory 8. Direction interpolation, that is, by interpolating the horizontal line thinned out by the vertical thinning circuit 6 to obtain 8 × 1
6 is generated for each macroblock.

When the decoding mode is the high image quality mode, the averaging unit 11 averages the image data read from the first reference image memory 7 and the second reference image memory 8, and
Reference image data of 8 × 16 macroblock units used for the interpolative inter-frame prediction coding is generated.

When the decoding mode is the low image quality mode, the averaging section 11 averages the image data read out from the first vertical interpolation circuit 9 and the second vertical interpolation circuit 10 to obtain an interpolation frame. Reference image data of 8 × 16 macroblock units used for inter prediction coding is generated.

The eighth switch 38 is controlled by the CPU 20 as follows. If the data output from the inverse DCT circuit 4 is reproduced image data for intra-frame predictive coding, the common terminal of the switch 38 is switched to the ground terminal.

When the data output from the inverse DCT circuit 4 is prediction error data for a forward inter-frame prediction code or prediction error data for a reverse inter-frame prediction code, the common terminal of the eighth switch 38 Are switched to select either a terminal to which reference image data from the first vertical interpolation circuit 9 is sent or a terminal to which reference image data from the second vertical interpolation circuit 10 is sent.

If the data output from the inverse DCT circuit 4 is prediction error data for an interpolative inter-frame prediction code, the common terminal of the eighth switch 38
Is switched to select the terminal to which the output of is sent.

When a reference image is read from the reference image memories 7 and 8, the cutout position is controlled based on the motion vector from the vector value conversion circuit 13. When the decoding mode is the high image quality mode, the horizontal value of the motion vector is converted to に よ っ て by the vector value conversion circuit 13 when the decoding mode is the high image quality mode. This is because the image data (first reproduced image data) in units of macro blocks sent to the image memories 7 and 8 is compressed in half in the horizontal direction.

When the decoding mode is the low image quality mode,
The reason why the horizontal and vertical magnitudes of the motion vector are converted to に よ っ て by the vector value conversion circuit 13 is that the motion vector is transmitted to the reference image memories 7 and 8 when the decoding mode is the low image quality mode. This is because the image data (second reproduced image data) in units of macroblocks are compressed to 水平 each in the horizontal and vertical directions.

The ninth switch 39 is used for reproducing picture data for a B picture sent from the second switch 32 to the ninth switch 39, reproducing picture data for an I picture or a P picture stored in the reference picture memory 7, The CPU 20 controls the playback image data for the I picture or P picture stored in the image memory 8 so as to be output in the same order as the order of the original images. Ninth
The first or second reproduced image data output from the switch 39 is format-converted by the format conversion circuit 14 so as to correspond to the number of horizontal and vertical scanning lines of the monitor device, and then sent to the monitor device.

The vertical resolution in the low image quality mode and the vertical resolution in the high image quality mode will be specifically described. For example, the number of vertical pixels is 1080 × the number of horizontal pixels is 19
From 20 HDTV signals, one field is 240 pixels x
Assume that an interlaced signal of 60 fields / second is generated with 720 pixels.

When the decoding mode is the low image quality mode, H
From the DTV signal, a video image of 30 frames / sec is obtained with one frame being 540 pixels × 960 pixels. When this video signal is converted into an interlace signal of 60 fields / second,
One field is a video signal of 270 pixels × 960 pixels. Therefore, the format conversion circuit 14
When an interlaced signal of 60 fields / second is created with a field of 240 pixels × 720 pixels, a video having a relatively high image quality can be obtained.

Therefore, from an HDTV signal having 1080 vertical pixels × 1920 horizontal pixels, one field is composed of 24 fields.
When an interlaced signal of 60 fields / second is created by 0 pixels × 720 pixels, the capacity of the reference image memory can be reduced by setting the decoding mode to the low image quality mode.

Next, the number of vertical pixels 1080 × the number of horizontal pixels 1
It is assumed that a progressive signal of 60 frames per second is generated from 920 HDTV signals in which one field is 480 pixels × 720 pixels.

When the decoding mode is the low image quality mode, H
From the DTV signal, a video image of 30 frames / sec is obtained with one frame being 540 pixels × 960 pixels. When this video signal is converted into a progressive image of 60 frames / second, 1
The frame becomes a video signal of 270 pixels × 960 pixels.
Therefore, if the format conversion circuit 14 attempts to create a pre-gressive signal of 480 pixels × 720 pixels and 60 frames / sec, it is necessary to interpolate a horizontal line, so that the image quality deteriorates.

When the decoding mode is the high image quality mode, H
From the DTV signal, one frame is 1080 pixels × 960 pixels, and a video image of 30 frames / sec is obtained. If this video signal is converted into a progressive image of 60 frames / second,
One frame is a video signal of 540 pixels × 960 pixels. Therefore, by the format conversion circuit 14,
One frame is 480 pixels x 720 pixels and 60 frames /
In the case where a second progressive signal is generated, a video having a relatively high image quality can be obtained.

In other words, when a pre-gressive signal of 480 pixels × 720 pixels and 60 frames / sec is generated from one HDTV signal having 1080 vertical pixels × 1920 horizontal pixels, the high image quality mode is suitable. .

In the above embodiment, one integrated circuit can support both the low image quality mode and the high image quality mode. Therefore, one integrated circuit can be selectively used for a low-grade device and a high-grade device. Will be able to Further, when the low-image-quality mode is mounted on a sufficient device, only the main memory is sufficient for the reference image memory, so that the cost can be reduced.

When the low image quality mode is mounted on a sufficient device, the reference image memory is constituted by the main memory and the additional memory, so that the additional memory is used as a memory for other uses such as graphics. It is also possible to do.

[0081]

According to the present invention, a moving picture reproducing apparatus which can select two kinds of decoding with different picture quality of the decoded picture is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an MPEG decoder.

FIG. 2 is a schematic diagram showing DCT coefficients after a high-frequency portion of a horizontal spatial frequency has been removed by a horizontal high-frequency coefficient removal circuit, and data after being inversely transformed by an inverse DCT circuit;

FIG. 3 is a schematic diagram illustrating a thinning process performed by a vertical thinning circuit.

FIG. 4 is a block diagram showing a configuration of a conventional MPEG decoder.

FIG. 5 is a schematic diagram for explaining DCT performed by an MPEG encoder and inverse DCT performed by a conventional MPEG decoder.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 variable length decoder 2 inverse quantizer 3 horizontal high frequency coefficient removing circuit 4 inverse DCT circuit 5 adder 6 vertical thinning circuit 7 first reference image memory 8 second reference image memory 9 first vertical interpolation Circuit 10 Second vertical interpolation circuit 11 Averaging unit 12 Variable length decoder 13 Vector value conversion circuit 14 Format conversion circuit 20 CPU 31 to 39 Switch

Continuation of front page (72) Inventor Akihiko Yamashita 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (3)

[Claims] 1. A first reproduction in which a horizontal direction is compressed to １ ／ based on an image obtained by performing an inverse orthogonal transform by using only a coefficient of a low frequency part of a horizontal frequency among orthogonal transform coefficients. A first reproduced image data generating means for generating image data, wherein the first reproduced image data is thinned out in a vertical direction by half,
A second reproduced image data generating means for generating second reproduced image data in which the horizontal direction and the vertical direction are each reduced to 、, a first reproduced image data generated by the first reproduced image data generating means;
A first decoded data generating means for generating decoded data based on the reproduced image of the first and second reproduced image data generated by the second reproduced image data generating means
Moving image comprising second decoded data generating means for generating decoded data based on the reproduced image, and switching means for switching between the first decoded data generating means and the second decoded data generating means Decryption device. 2. A coefficient reduction circuit for removing a coefficient in a high-frequency portion of a horizontal frequency from orthogonal transform coefficients in a block unit of a predetermined size obtained from an input signal to reduce a transform coefficient in half, and a coefficient reduction. An inverse orthogonal transform circuit that performs inverse orthogonal transform using the transform coefficient reduced by the circuit to obtain reproduced image data or time-axis prediction error data in which the horizontal direction is compressed to に for each block unit; Based on the time axis prediction error data obtained by the conversion circuit and predetermined reference image data, the horizontal direction
The reproduction image data (hereinafter, referred to as the first reproduction image data) obtained by the adder, the inverse orthogonal transform circuit, or the adder that generates the reproduction image data compressed to 2 is decimated by half in the vertical direction. A vertical thinning circuit for generating second reproduced image data in which the horizontal direction and the vertical direction are each compressed to １ ／, and among the first reproduced image data and the second reproduced image data, the decoding mode is First switching means for outputting the first reproduced image data when the first decoding mode is set, and outputting the second reproduced image data when the decoding mode is the second decoding mode; Switch for sending the image data output from the first reference image memory or the second reference image memory to the vertical reference thinning circuit for the image data output from the first reference image memory Therefore, a first vertical interpolation circuit for interpolating the thinned horizontal lines, and a horizontal line thinned by the vertical thinning circuit for the image data output from the second reference image memory. Vertical interpolation circuit for decoding, among image data output from the first reference image memory and image data output from the first vertical interpolation circuit, when the decoding mode is the first decoding mode, (2) second switching means for selecting image data output from the reference image memory and selecting image data output from the first vertical interpolation circuit when the decoding mode is the second decoding mode; Among the image data output from the reference image memory and the image data output from the second vertical interpolation circuit, when the decoding mode is the first decoding mode, the image data output from the second reference image memory is used. Is selected, and when the decoding mode is the second decoding mode, the third switching means for selecting the image data output from the second vertical interpolation circuit, the image data output from the second switching means and the third switching means An averaging circuit for averaging with the image data output from the third switching means, image data output from the second switching means, image data output from the third switching means, and output from the averaging circuit A reference image switch for switching image data and ground voltage and sending the image data and reference image data to the adder;
An image data output from the first switching means, an image data output from the first reference image memory, and an output image data switch for switching and outputting image data output from the second reference image memory. A moving picture decoding device provided. 3. A coefficient reduction circuit for removing a coefficient in a high frequency portion of a horizontal frequency from orthogonal transform coefficients in a block unit of a predetermined size obtained from an input signal to reduce a transform coefficient in half, and a coefficient reduction. An inverse orthogonal transform circuit that performs inverse orthogonal transform using the transform coefficient reduced by the circuit to obtain reproduced image data or time-axis prediction error data in which the horizontal direction is compressed to に for each block unit; Based on the time axis prediction error data obtained by the conversion circuit and predetermined reference image data, the horizontal direction
The reproduction image data (hereinafter, referred to as the first reproduction image data) obtained by the adder, the inverse orthogonal transform circuit, or the adder that generates the reproduction image data compressed to 2 is decimated by half in the vertical direction. A vertical thinning circuit for generating second reproduced image data in which the horizontal direction and the vertical direction are each compressed to １ ／, and among the first reproduced image data and the second reproduced image data, the decoding mode is A first switching unit that outputs first reproduced image data when the first decoding mode is set, and outputs second reproduced image data when the decoding mode is the second decoding mode; Memory connection input terminal and first memory connection output terminal for connecting a memory for memory, second memory connection input terminal and second memory connection output terminal for connecting a second reference image memory A memory selection switch for sending image data output from the first switching means to the first memory connection input terminal or the second memory connection input terminal; image data output from the first memory connection output terminal A first vertical interpolation circuit for interpolating horizontal lines thinned out by a vertical thinning circuit, and a vertical thinning circuit for image data output from a second memory connection output terminal. The second vertical interpolation circuit for interpolating the inserted horizontal line, the decoding mode of the image data output from the first memory connection output terminal and the image data output from the first vertical interpolation circuit If the decoding mode is the first decoding mode, the image data output from the first memory connection output terminal is selected. If the decoding mode is the second decoding mode, the image data output from the first vertical interpolation circuit is selected. A second switching unit for selecting data, when the decoding mode is the first decoding mode among the image data output from the second memory connection output terminal and the image data output from the second vertical interpolation circuit. Means for selecting image data output from the second memory connection output terminal, and selecting image data output from the second vertical interpolation circuit when the decoding mode is the second decoding mode. An averaging circuit for averaging the image data output from the second switching means and the image data output from the third switching means, the image data output from the second switching means, the third switching means A reference image changeover switch that switches image data output from the image data and image data output from the averaging circuit and ground voltage, and sends the image data as reference image data to the adder;
An output image data switch for switching and outputting image data output from the first switching means, image data output from the first memory connection output terminal, and image data output from the second memory connection output terminal. A video decoding device comprising: