JPH11261871A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device which can reduce its power consumption and also can perform the proper image processing by supplying the power to a display processing circuit and a digital image signal processing circuit and also cutting the supply of power to an image pickup element, and analog image signal processing circuit, an A/D converter and a 1st clock pulse generation means respectively when an image is displayed based on the image signals stored in a storage means. SOLUTION: When a dial switch 117 is switched to a reproduction mode, a switch 118 is switched to the (b) side. Thus, the power is supplied only to the blocks E2 and E0 which are necessary for the display of still images stored in an external storage 116. Then a switch 104 is switched to the (b) side to supply the pixel CLK which is generated by a frequency divider 102 to a still image display circuit 112. In the reproduction mode, the switches 118 and 104 are switched to the (a) sides to supply the power only to the blocks E1 and E0 which are necessary for the image pickup. Then the image CLK which is generated by a timing generator 103 is supplied to a digital image signal processing circuit 110, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus suitable for use in, for example, a digital still camera.

[0002]

2. Description of the Related Art FIG. 4 is a system block diagram of a conventional digital still camera. In FIG. 4, 907 is C
An analog image signal processing circuit 908 includes a sample and hold circuit, a low-pass filter, a gain control circuit, and the like, and optimizes an output signal from the image sensor. The A / D converter 909 converts the image signal processed by the analog image signal processing circuit 908 into a digital image signal. The digital image signal processing circuit 910 converts the digital image signal output from the A / D converter 909 into standardized luminance / chrominance image data. RAM 913
Is configured by a semiconductor or the like, and stores a digital image signal (still image signal) processed by the digital image signal processing circuit 910 at an instruction timing from a user.

[0005] A display unit 914 is constituted by an LCD or the like, and displays a moving image currently being captured by the image sensor 907 or a still image stored by the RAM 913. The moving image display circuit 911 performs a process of continuously displaying a moving image on the display unit 914 of an image signal currently being captured by the imaging element 907. Further, the still image display circuit 912
The still image stored in the RAM 913 is displayed on the display unit 91.
In step 4, the display is performed.

[0004] A crystal oscillator 901 generates a clock signal that serves as an operation reference for the entire system. The timing generator 903 is configured by a gate circuit using a flip-flop, a read clock such as a horizontal transfer pulse and a vertical transfer pulse signal necessary for reading image data from the image sensor 907, a digital image signal processing circuit 910, and a moving image display. A pixel clock serving as a reference when capturing and outputting image data in the circuit 911 and the still image display circuit 912, a sample / hold timing signal of a sample / hold circuit included in the analog image signal processing circuit 908, and a sample of the A / D converter 909 An A / D clock serving as a timing is generated, and the phase relationship of each clock signal is uniquely determined. In the configuration of FIG. 4, the pixel clock and the A / D clock are shared.

In the configuration of the conventional image pickup apparatus shown in FIG. 4 described above, even when a still image stored in the RAM 913 is displayed, the image pickup device 907 and the analog image signal which do not actually need to execute the operation are displayed. Power is also supplied to the processing circuit 908 and the A / D converter 909, and the power is wasted. In addition, the timing generator 903 controls the image sensor 903 and the analog image signal processing circuit 90 even when reproducing the stored image.
8, and a clock for each processing block of the A / D converter 909 must be generated, which also results in waste of power.

In order to solve such a problem of the system configuration of the imaging apparatus shown in FIG. 4, a system configuration of the imaging apparatus shown in FIG. 5 has been proposed. In the configuration of the imaging device in FIG. 5, the frequency divider 903a generates a pixel clock and outputs the pixel clock to a display system for performing image display, such as a digital image signal processing circuit 910, a moving image display circuit 911, and a still image display circuit 912. I do. The timing generator 903 generates a clock for an imaging system such as the imaging device 907, the analog image signal processing circuit 908, and the A / D converter 909. When the still image stored in the memory is displayed by the system configuration of FIG. 5, the supply of power to the imaging system such as the timing generator 903, the imaging device 907, the analog image signal processing circuit 908, and the A / D converter 909 is stopped. To save power.

Here, a timing generator 903,
The phase of the clock generated by the frequency divider 903a is
Each is determined according to the timing when power is supplied. That is, the power supply timings of the imaging system and the display system of the system in FIG. 5 are controlled independently of each other according to the operation mode of the imaging device such as imaging or display, and are different from each clock output from the timing generator 903. Since the pixel clock output from the frequency divider 903a is determined according to the pulse output of the crystal oscillator 901 at the time of power supply, the phase relationship between them is not uniquely determined.
As the phase relationship between the output clocks of the timing generators 903 and 903a, for example, two types of clock timing as shown in FIGS. 7A and 7B can be considered.

In FIGS. 7A and 7B, A is an output signal of the crystal oscillator 901, and B is a read clock at which the timing generator 903 instructs the image sensor 907 to read pixel data. . Also, C
Is pixel data output from the A / D converter 909 to the digital image signal processing circuit 910, and the phase relationship between B and C is uniquely determined by the timing generator 903. Since D is a pixel clock generated by the frequency divider 903a, the phase relationship between B and C is not uniquely determined.

Here, it is assumed that the digital image signal processing circuit 910 in FIG. 5 is designed to sample pixel data at the moment when the pixel clock D falls.

In the case of FIG. 7A, pixel data is taken into the digital image signal processing circuit 910 at the moment of falling of the pixel clock D indicated by an arrow.
Pixel data can be appropriately sampled. On the other hand, in the case of FIG. 7B, at the moment of falling of the pixel clock D indicated by the arrow, the pixel data cannot be sampled properly because the pixel data is changing.

As described above, in the system shown in FIG.
Although the power supply of the imaging system and the power supply of the display system were separately supplied, depending on the power supply timing, there was a possibility that the pixel data could not be properly sampled.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide an imaging apparatus capable of performing power saving and performing appropriate image processing.

[0013]

According to the first aspect of the present invention, an image sensor and an image signal from the image sensor are subjected to analog signal processing by predetermined processing. An analog image signal processing circuit to perform;
An A / D converter for A / D converting an image signal processed by the analog signal processing circuit; a digital image signal processing circuit for performing digital signal processing on the image signal output from the A / D converter by predetermined processing; A display processing circuit that performs display processing of an image signal having undergone predetermined processing by the digital signal processing circuit; a storage unit that stores an image signal processed by the digital signal processing circuit; and at least the image sensor and First clock pulse generating means for generating a predetermined clock pulse for each of the analog image signal processing circuit, the A / D converter, and the digital image signal processing circuit; and at least the display processing unit and the digital signal Generates predetermined clock pulses for each processing circuit When displaying an image based on the image signal stored by the storage unit using the second clock pulse generating unit, the digital image signal processing circuit, and the display processing circuit, the display processing circuit and the digital image Power supply means for supplying power to a signal processing circuit and interrupting supply of power to the image sensor, the analog image signal processing circuit, the A / D converter, and the first clock pulse generating means. Features.

According to a second aspect of the present invention, in the first aspect, when the subject is imaged by the image sensor, the power supply means includes the image sensor, the analog image signal processing circuit, and the analog image signal processing circuit. / D converter and the digital image signal processing circuit and the first clock pulse generating means are configured to supply power to the display processing circuit and the second clock generating means. It is characterized by the following.

According to a third aspect of the present invention, in the first or second aspect, the phase relationship between the clock pulses generated by the first clock pulse generating means is uniquely determined. And

According to a fourth aspect of the present invention, in any one of the first to third aspects,
An oscillator that oscillates a clock pulse having a predetermined cycle; and a frequency-divided phase adjusting unit that divides the clock pulse oscillated by the oscillator and performs phase adjustment, wherein the first clock pulse generating unit includes: A predetermined clock pulse is generated for each of the image sensor, the analog image signal processing circuit, the A / D converter, and the digital image signal processing circuit based on the clock pulse output by the frequency division phase adjusting unit. It is characterized by being constituted.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of an image pickup apparatus according to the present embodiment. Note that the operation processing of the imaging apparatus according to the present embodiment is performed by a system control circuit (not shown). Although the imaging apparatus according to the present embodiment is described using a digital still camera as an example, the present embodiment can be applied to an imaging apparatus that records a moving image.

In FIG. 1, reference numeral 107 denotes an image sensor such as a CCD, and an analog image signal processing circuit 108 includes a sample hold circuit, a low-pass filter, a gain control circuit, and the like, and optimizes an output signal from the image sensor. . The A / D converter 109 converts the image signal processed by the analog image signal processing circuit 108 into a digital image signal. The digital image signal processing circuit 110 converts the digital image signal output from the A / D converter 109 into standardized luminance and color difference image data. The RAM 113 is for temporarily storing a digital image signal (still image signal) processed by the digital image signal processing circuit 110, and the external storage device 1 to be described later is operated at an instruction timing from a user.
The image file is written in 16.

Here, the configuration of the digital signal processing circuit 110 is shown in FIG. The flip-flop 201 is a multi-bit flip-flop circuit, and samples pixel data in synchronization with a pixel clock input timing described later.
The luminance / color difference conversion processing block 202 converts the pixel data sampled by the flip-flop 201 into predetermined standardized luminance / chrominance data.

Here, in the imaging mode, the luminance and chrominance data generated by the luminance and chrominance conversion processing block 202 is output to the moving picture display circuit. In particular, when recording a still image, the luminance / color difference data is input to the RAM control circuit 203. RAM
The control circuit 203 stores the received data in the RAM 113. The modulation circuit 204 includes the moving image processing circuit 111
Alternatively, the luminance and chrominance conversion data processed by the still image display circuit 112 is generated into a standardized carrier color signal such as NTSC or PAL and output to the display unit 114.

The external storage device 116 is a non-volatile memory for storing image files stored in the RAM 113, and is constituted by a semiconductor memory or a hard disk. It is also possible to read out the image file stored by the external storage device 116 and display a still image on the display unit 114. The external storage device 1
No. 16, power is supplied at an arbitrary timing at which reading and writing of image data is executed regardless of the imaging mode and the reproduction mode.

The display unit 114 is constituted by an LCD or the like, and displays a moving image currently being captured by the image sensor 107 or a still image stored by the RAM 113. The moving image display circuit 111 performs a process of continuously displaying a moving image on the display unit 114 of an image signal currently being captured by the image sensor 107. Further, the still image display circuit 112
The still image stored in the RAM 113 is displayed on the display unit 11.
In step 4, the display is performed.

The crystal oscillator 101 generates a clock signal serving as an operation reference of the entire system. The timing generator 103 includes a plurality of gate circuits using flip-flops, a read clock such as a horizontal transfer pulse and a vertical transfer pulse signal necessary for reading image data from the image sensor 107, a digital image signal processing circuit 110, A pixel clock serving as a reference when capturing and outputting image data in the moving image display circuit 111 and the still image display circuit 112, a sample / hold timing signal of a sample / hold circuit included in the analog image signal processing circuit 108, and the A / D converter 10.
Each of the A / D clocks corresponding to the nine sample timings is generated based on the clock oscillated from the crystal oscillator 101. Since each generated clock signal is generated by the same timing generator,
The phase relationship of each clock signal is uniquely determined.

The frequency divider 102 generates a pixel clock and outputs it to a display system for displaying images, such as a digital image signal processing circuit 110, a moving image display circuit 111, and a still image display circuit 112. The switch 104 switches the output of the pixel clock from the frequency divider 102 and the timing generator 103.

The battery 115 supplies power to each operation processing block of the imaging apparatus according to the present embodiment. The dial switch 117 is a switch for switching between an imaging mode and an image reproduction mode.
4. A predetermined switching is performed according to the mode such as the switch 118.

FIG. 9 is a flowchart showing the operation of the power supply timing of each section of the image pickup apparatus according to the present embodiment and the switching of clock signal output.

In s101, the dial switch 11
If the mode is switched to the imaging mode by operating the switch 7, the process proceeds to s102, the switch 118 is switched to the a side, and power is supplied only to each of the blocks E1 and E0 necessary for performing imaging (FIG. In FIG. 11, a block to which power is supplied includes a crystal oscillator 101, a timing generator 103, an analog image signal processing circuit 108,
/ D converter 109, digital image signal processing circuit 11
0, frequency divider 105, RAM 113, display unit 114, etc.). Further, the switch 104 is switched to the a side, and the pixel clock generated by the timing generator 103 is supplied to the digital image signal processing circuit 110 and the like.

When the imaging mode is set, the output timing of the pixel data from the A / D converter 109 and the output timing of the pixel clock are uniquely determined. This is because pixel data is output by a clock generated by the same timing generator 103 as the pixel clock. For example, FIG. 6 shows a clock signal output from the timing generator 103 at this time. As shown in FIG. 6, if the timing of sampling the pixel data by the digital signal processing circuit 110 is set at the moment when the pixel clock falls, the pixel data can always be appropriately sampled.

When the image pickup mode is set, the image data converted by the luminance / color difference conversion processing block 202 is displayed on the display unit 11 by the moving image display circuit 111.
4 displays the image currently being captured.

In step s103, when a still image recording command is output by operating a release switch (not shown), the pixel clock output by the timing generator 103 to which power is currently supplied is converted to a digital image signal processing circuit 110. Output to etc. The image data subjected to the luminance / chrominance conversion processing and the data compression processing in the luminance / chrominance conversion processing block 202 is converted into a one-frame image file via the RAM 113 via the external storage device 1.
16 is stored.

On the other hand, when the image reproduction mode is selected in s101, the process proceeds to s105, the switch 118 is switched to b, and E2 and E0 necessary for displaying the still image stored in the external storage device 116 are displayed. (In FIG. 1, the blocks to which power is supplied include a crystal oscillator 101, a frequency divider 102, a digital image signal processing circuit 110, and a still image display circuit 11).
2, RAM 113, display panel 114, etc.). further,
The switch 104 is switched to the b side, and the pixel data generated from the frequency divider 102 to which power is currently supplied is output to the still image display circuit 112. Then, the image data read in advance from the external storage device 116 to the RAM 113 is expanded in the luminance / color difference conversion processing block 207, and a still image is displayed on the display unit 114. The processing of the image data is performed according to the output timing of the pixel clock generated by the frequency divider 102.

As described above, the pixel clock is generated by the frequency divider 102 having a small circuit scale in the image reproduction mode.
Since power is not supplied to the timing generator 103 and clock pulses corresponding to the image sensor 107, the analog image signal processing circuit 108, and the A / D converter which do not need to operate are not generated, power consumption is reduced. Can be.

As described above, according to the present embodiment, in both the imaging mode and the image reproduction mode, power is not supplied to the unnecessary components of the imaging apparatus, so that power consumption is reduced. Can be saved. Furthermore, in the case of the imaging mode, since one timing generator generates a clock pulse for each block of the imaging device, the output timing of the clock pulse uniquely generated for each block of the imaging device ( Phase) is determined, and appropriate sampling of image data can be performed.

(Second Embodiment) FIG. 2 is a block diagram showing the configuration of an imaging apparatus according to the second embodiment. Note that the operation processing of the imaging apparatus according to the present embodiment is performed by a system control circuit (not shown). Although the imaging apparatus according to the present embodiment is described using a digital still camera as an example, the present embodiment can be applied to an imaging apparatus that records a moving image. In FIG. 2, the same reference numerals as those in FIG. 1 denote the same processes, and a description thereof will be omitted.

The frequency divider 119 with a phase adjusting function shown in FIG. 2 comprises a frequency divider 301, phase adjusting circuits 302, 303, 304 and a switch 305 as shown in FIG.

In FIG. 3, the frequency divider 11 with a phase adjusting function
9, a clock signal generated by the crystal oscillator 101 is input as an input signal CLK. The frequency divider 301 lengthens the cycle of the input signal from the crystal oscillator 101. When storing a still image, the switch 305 is switched to the side a while performing processing for generating a luminance and color difference signal, and is switched to the side b in other states.

Further, the output of the switch 305 is input to the phase adjustment circuit 302. The phase adjustment circuit 302
It is composed of a T gate, a delay element, a selector circuit, and the like, and can arbitrarily set a delay amount between an input signal and an output signal. The output signal TGCLK of the phase adjustment circuit 302 is input to the timing generator 103.

The timing generator 103 outputs a signal to the image pickup device 10 based on the input clock signal TGCLK.
7, a vertical transfer pulse and a horizontal transfer pulse are generated to read and execute pixel data, and the analog image signal processing circuit 108 generates a sample hold timing signal to execute signal processing. further,
The clock signal in which the phase relationship between the vertical transfer pulse, the horizontal transfer pulse, and the sample hold timing signal is uniquely determined by the timing generator 103 is input again to the TGMKO terminal of the frequency divider 119 with a phase adjustment function.

The signal input from TGMKO is input to phase adjustment circuits 303 and 304. Phase adjustment circuit 3
Reference numerals 03 and 304 include a NOT gate, a delay element, a selector circuit, and the like, like the phase adjustment circuit 302.

The clock signal output from the phase adjustment circuit 303 is supplied to the A / D converter 109 from the ADCLK terminal.
Is supplied as a sampling clock. The clock signal output from the phase adjustment circuit 304 is supplied to the digital image signal processing circuit 110 and the moving image display circuit 111 as a pixel clock.

With the above configuration, the phase of the clock signal output to each block of the imaging apparatus of the present embodiment is uniquely determined, so that an appropriate imaging operation and image display operation can be executed.

FIG. 10 is a flow chart of the operation relating to the timing of power supply of each section of the imaging apparatus according to the present embodiment and the switching of clock signal output.

In s201, the dial switch 11
When the mode is switched to the imaging mode by operating the switch 7, the process proceeds to s202, the switch 118 is switched to the a side, and power is supplied to each of the blocks E1 and E0 necessary for performing imaging (FIG. 11). , A block to which power is supplied includes a crystal oscillator 101, a timing generator 103, an analog image signal processing circuit 108, and an A / D
Converter 109, digital image signal processing circuit 110,
Frequency divider 105, RAM 113, display unit 114, etc.). Further, the switch 104 is switched to the a side and the switch 305 is switched to the a side, and the pixel clock generated by the frequency divider 119 with the phase adjustment function is applied to the digital image signal processing circuit 11.
0 and so on.

When the imaging mode is set, the output timing of the pixel data from the A / D converter 109 and the output timing of the pixel clock are uniquely determined. As shown in FIG. 6, similarly to the first embodiment, if the timing of sampling the pixel data by the digital signal processing circuit 110 is set at the moment when the pixel clock falls, the pixel data can always be appropriately sampled. .

Further, when the image pickup mode is set, the image data converted by the luminance / color difference conversion processing block 202 is displayed on the display unit 11 by the moving image display circuit 111.
4 displays the image currently being captured.

The display process of the image currently being picked up will be described.
9 is sampled inside the circuit at the timing of the input pixel clock,
This is temporarily stored in the RAM 113 by the M control circuit 203 (s202a). Next, the RAM control circuit 203
A process called a vertical addition mixing process is performed on the image data on the AM 113 (s202b). The vertical addition / mixing process is a process of adapting the format of image data to the method of the luminance / color difference conversion process, and is achieved by adding the image data in the vertical direction and writing back the addition result on the RAM 113 again. Further, the RAM control circuit 203
Reads the image data from the RAM 113, inputs the image data to the luminance / color difference conversion processing block 202, and further stores the output of the luminance / color difference conversion processing block 202 in the RAM 113.

In step S203, when a still image recording command is output by operating a release switch (not shown), the process proceeds to step S204 to check whether the above-described luminance / color difference conversion can be started. Luminance / chrominance conversion is block 20
2, the RAM control circuit 203 performs one read operation and one write operation on the RAM 113 each time the luminance and chrominance data of one pixel is generated. Therefore, the time for generating the luminance and chrominance data of one pixel, that is, the cycle of the pixel clock needs to be set to be equal to or longer than the time from one reading to one writing of the RAM 113. Therefore s205 switch 3
05 is switched to the a side, and the frequency of the above-described pixel clock is set by the frequency divider 301 to be equal to or longer than the time from one reading to one writing of the RAM 113.

Then, the luminance and chrominance conversion is performed in s205a, and the luminance and chrominance data for one screen stored in the memory 113 is compressed in the above-described processing in s205b. , And the still image storage operation ends.

On the other hand, when the reproduction mode is selected in s101, the process proceeds to s105, and the switch 118 is set to b,
The switch 305 is switched to the b side, and the external storage device 1
Power is supplied to each of the blocks E2 and E0 necessary for displaying the still image stored in the memory 16 (blocks to which power is supplied in FIG.
Frequency divider 102, digital image signal processing circuit 110, still image display circuit 112, RAM 113, display panel 114, etc.). Further, the switch 104 is switched to the b side, and outputs pixel data generated from the frequency divider 102 to which power is currently supplied to the still image display circuit 112. The image data read in advance from the external storage device 116 to the RAM 113 is fetched in accordance with the output of the pixel clock generated from the frequency divider 102, and a still image is displayed on the display unit 114.

As described above, according to the present embodiment, in both the imaging mode and the reproduction mode, power is not supplied to the unnecessary components of the imaging apparatus, so that power consumption is reduced. You can save money.
Further, in the case of the imaging mode, since the phase of the clock pulse can be adjusted for each block of the imaging device, the output timing of the clock pulse uniquely generated for each block of the imaging device ( Phase) is determined, and appropriate sampling of image data can be performed.

[0052]

As described above, according to the imaging apparatus of the present invention, power is not supplied to unnecessary configurations of the imaging apparatus both when capturing and reproducing the subject. Therefore, power consumption can be reduced. Furthermore, when capturing an image of a subject, the output timing (phase) of the clock pulse generated uniquely for each block of the image capturing apparatus is determined, and appropriate image data can be sampled. Is possible.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an imaging device according to a first embodiment.

FIG. 2 is a configuration block diagram of an imaging device according to the first embodiment.

FIG. 3 is a configuration diagram of a frequency divider with a phase adjustment function.

FIG. 4 is a configuration block diagram of a conventional imaging device.

FIG. 5 is a configuration block diagram of a conventional imaging device.

FIG. 6 is a diagram illustrating an example of a phase relationship such as a clock pulse output to each block in the first and second embodiments.

FIG. 7 is a diagram illustrating an example of a phase relationship such as a clock pulse output to each block in a configuration of a conventional imaging apparatus.

FIG. 8 is a diagram illustrating a configuration of a digital image signal processing circuit.

FIG. 9 is an operation processing flowchart relating to power supply timing and clock signal output switching of each unit of the imaging apparatus according to the first embodiment;

FIG. 10 is an operation processing flowchart relating to power supply timing and clock signal output switching of each unit of the imaging apparatus according to the second embodiment;

[Explanation of symbols]

 Reference Signs List 101 crystal oscillator 102 frequency divider 103 timing generator 104 switch 106 switch 107 image sensor 108 analog image signal processing circuit 109 A / D converter 110 digital image signal processing circuit 111 moving image display circuit 112 still image display circuit 113 RAM 114 display unit 115 battery 116 External storage device 117 Dial switch 118 Switch 119 Divider with phase adjustment function 301 Divider 302 Divider 303 Divider 304 Divider 305 Switch

Claims (4)

[Claims] 1. An image sensor, an analog image signal processing circuit that performs analog signal processing on an image signal from the image sensor by predetermined processing, and A / D-converts an image signal processed by the analog signal processing circuit. An A / D converter, a digital image signal processing circuit that performs digital signal processing on the image signal output from the A / D converter by predetermined processing, and an image signal that has been subjected to predetermined processing by the digital signal processing circuit. A display processing circuit that performs display processing; a storage unit that stores an image signal processed by the digital signal processing circuit; at least the image sensor, the analog image signal processing circuit, the A / D converter, and the digital image signal A first clock for generating a predetermined clock pulse for each of the processing circuits; A lock pulse generation unit, a second clock pulse generation unit that generates a predetermined clock pulse for at least each of the display processing unit and the digital signal processing circuit, and the digital image signal processing circuit and the display processing circuit. When performing display of an image based on the image signal stored by the storage means, the power is supplied to the display processing circuit and the digital image signal processing circuit, and the imaging device and the analog image signal processing circuit and An imaging apparatus comprising: an A / D converter; and a power supply unit that cuts off supply of power to the first clock pulse generation unit. 2. The imaging device according to claim 1, wherein when the imaging device captures an image of a subject, the power supply unit includes the imaging device, the analog image signal processing circuit, the A / D converter, and the digital image signal processing circuit. An imaging device configured to supply power to the first clock pulse generation unit and cut off the supply of power to the display processing circuit and the second clock generation unit. 3. The imaging apparatus according to claim 1, wherein a phase relationship between clock pulses generated by the first clock pulse generation means is uniquely determined. 4. An oscillator according to claim 1, further comprising: an oscillator for oscillating a clock pulse having a predetermined cycle; and dividing the clock pulse oscillated by said oscillator and adjusting a phase. Frequency dividing phase adjusting means for executing the first clock pulse generating means,
A predetermined clock pulse is generated for each of the image sensor, the analog image signal processing circuit, the A / D converter, and the digital image signal processing circuit based on the clock pulse output by the frequency division phase adjusting unit. An imaging apparatus characterized in that it is configured to perform