JPH11261461A - Data demodulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an operation processing time and reduce the amount of hardware by reducing the amount of operation of a filter coefficient. SOLUTION: The device is provided with a selection reference level generation part 7 and a delay element detection part 8 which detect a delay element within range of a predetermined level and time from both leading element and delay element of a synchronizing signal obtained by performing correlation processing of a known synchronizing signal KSY with regard to transmitted reception data RD. A tap selection part 9 is provided for selecting a tap TP of a feedback part 22 corresponding to a generation position of the detected delay element. Thus, calculation and output of the second filter coefficient CSb to the feedback part 22 in a coefficient operation part 6 is performed only for the selected tap.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data demodulation device, and more particularly to a data demodulation device provided with an equalization filter of a decision feedback equalization system.

[0002]

2. Description of the Related Art In the propagation path of radio waves in wireless data communication, there are several paths that arrive with a delay due to reflection on a reflector or the like, in addition to a path directly reaching the radio waves. In received data obtained by receiving a radio wave transmitted through a path, interference occurs between data symbols and the like, and errors occur in data demodulated by the data demodulator.
In order to reduce errors in demodulated data due to the multipath, a replica signal corresponding to a delay component is created from the data after the data determination processing, and the replica signal is calculated from the data after the waveform equalization to remove the delay component. In many cases, a decision feedback equalization method is adopted.

FIG. 3 shows an example of a conventional data demodulation device employing this decision feedback system. This data demodulator is
Sequentially reading the received memory 1 in accordance with the timing signal TM _a synchronizing signal and for sequentially sent advance sequentially stored by over-sampling the received data RD come reading frames containing the data units, the first transversal filter feedforward module 21 for performing waveform equalization processing based on the received data RRD read from the receive memory 1 comprises a first filter coefficient CS _a, second
Based on the demodulated data DMD and the second filter coefficient CS _b of include transversal filter after data determination process, to produce a corresponding delay component included in the received data RRD replica signal having a negative level (FBDD) Feedback section 22 and feedforward section 21
Data FFED from the feedback unit 22 and the replica signal (FBDD) from the feedback unit 22 are added to obtain the equalized data F
An equalizing filter 2 including an adding circuit 23 for removing a delay component from the FED, and output data (E
QD) to perform data determination processing and output as demodulated data DMD, and at the same time to output an error signal ER, and a known signal generation section 41 that generates a known synchronization signal KSY corresponding to a synchronization signal portion of received data. A correlation processing unit 42 for performing a correlation process between the known synchronization signal KSY and the received data RD to extract a correlation processing signal CRS, and comparing the correlation processing signal CRS with a reference level _Vr, and determining the maximum level (leading component) thereof the timing signal TM _b of the synchronization signal detection unit 4x having a level detecting unit 43 for generating a sync signal SYN to the synchronization detection position location, timing signal TM _a and processing for reading based on the synchronization signal SYN Signal generator 5x for generating
When the received data RRD from the reception memory 1, the demodulated data DMD and the error signal on the basis of the ER and first and second filter coefficient CS _a accordance with a timing signal TM _b for processing, CS _b calculates the equalizing filter 2 And a coefficient calculation unit 6x that supplies the coefficient calculation unit 6x.

In this data demodulation device, the first and second transversal filters of the feedforward section 21 and the feedback section 22 in the equalization filter 2 are:
A delay circuit DL in which a plurality of delay elements are sequentially arranged and connected;
A plurality of taps TP for extracting the outputs of these delay elements;
A configuration including a tap output operation unit TOC that performs operation processing such as multiplying filter signals CS _a and CS _b corresponding to output signals from these taps TP, and an adder AD that adds processing results of each tap. Is done. The number of delay elements and the number of taps TP of the delay circuit DL are determined by the symbol (data) due to the delay component of the received data RRD (RD).
The interference between them is determined by the delay component to be removed, and it is necessary to make the first and second transversal filters equal.

The calculation of the first and second filter coefficients CS _a and CS _b in the coefficient calculation section 6 x is performed simultaneously because they are related to each other, so that the number of taps of the feed forward section 21 is N 1, Assuming that it is N2, calculation is performed based on the determinant of (N1 + N2) rows and (N1 + N2) columns, and the calculation amount is 2 of (N1 + N2).
It is proportional to the power. FIG. 4 shows how interference between symbols (data) due to delay components in the data demodulator is removed. FIG. 4 shows the reception data RRD (RD)
And one symbol (data) of the data (FFED etc.) after each processing.

The data (FFED) that has been equalized by the feedforward unit 21 in the equalization filter 2 includes a directly transmitted preceding component (earliest data, time t0).
In addition to the above, a delay component due to reflection from a reflector (time t
1, t2, etc.) (FIG. 4, upper row).

[0007] The feedback section 22 performs delay processing and coefficient calculation processing of each tap output on the demodulated data DMD determined by the data determination section 3 and, therefore, the preceding component, thereby obtaining the delay component (t1, t2) and generates a feedback delay component signal FBDD of a replica signal having a negative level (middle stage in FIG. 4).

The delay circuit can be removed from the equalized data FFED by adding the equalized data FFED from the feedforward section 21 and the feedback delay component signal FBDD by the adding circuit 23 (FIG. 4). Bottom).

[0009]

In the above-mentioned conventional data demodulating apparatus, the first and second signals supplied to the equalizing filter 2 are provided.
Of the filter coefficients CS _a and CS _b of the equalization filter 2
Feed-forward section 21 and feedback section 2
Since the configuration is performed based on the determinant of the row and column of the sum of the number of taps of 2 (N1 + N2), if it is attempted to remove even a delay component having a larger delay amount, the amount of calculation by the coefficient calculation unit 6x And the amount of hardware for the arithmetic processing increases, and the amount of arithmetic is 2 times the sum of the number of taps.
There is a problem that the processing time becomes longer because it increases in proportion to the power, and if the delay amount of the delay component to be removed is limited by limiting the amount of hardware and the processing time, interference due to delay components not to be removed is reduced. And the number of data errors increases.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to reduce the amount of hardware and arithmetic processing time while suppressing data errors, and to remove delay components having a larger delay amount. Accordingly, it is an object of the present invention to provide a data demodulator capable of suppressing data errors to a lower level.

[0011]

A data demodulator according to the present invention is characterized by having the following components in order to achieve the above object. (B) Receive memory sequentially storing received data including a synchronization signal and data and sequentially reading the received data according to a read timing signal. (B) Receive data read from the receive memory at a data input end. And a transversal filter-type feed-forward section for multiplying and adding a first filter coefficient corresponding to the tap to each of a plurality of tap outputs to perform waveform equalization processing; A tap output of the transversal filter which multiplies each tap output by a second filter coefficient corresponding to the tap and adds the resultant to output a delay component signal of a negative level; output data of the feedforward section; And an adder circuit for adding the delayed component signal of (C) a data determination unit that performs a data determination process on the equalized data from the equalization filter and outputs the same as the determination data, and simultaneously outputs an error signal of the determination data. (D) the sequentially received data A synchronization signal detecting section for performing a correlation process between the synchronization signal and the known synchronization signal to detect a synchronization signal including a preceding component and a delay component thereof. (E) From a synchronization signal including the preceding component and the delay component from the synchronization signal detecting section, A delay component detection unit that detects a delay component in a predetermined level range and a time range; and (f) a generation position of a delay component detected by the delay component detection unit among a plurality of taps in a feedback unit of the equalization filter. A tap selection unit for selecting a corresponding tap; (g) reception data read from the reception memory and determination data from the data determination unit A first filter coefficient of each of a plurality of taps in a feedforward section of the equalization filter, and a tap selected by the tap selection section among a plurality of taps in a feedback section of the equalization filter, based on the error signal and the error signal. A coefficient calculator for calculating a second filter coefficient of only taps (h) a timing signal generator for generating the readout timing signal based on a synchronization signal of a preceding component from the synchronization signal detector;

Further, the timing signal generating section generates a timing signal for coefficient calculation in accordance with the number and position of the taps selected by the tap selecting section, and the coefficient calculating section generates the timing signal for the coefficient calculation. The first filter coefficient and the second filter coefficient are calculated in accordance with the signal, and the delay component detection unit further includes a synchronization signal including a leading component from the synchronization signal detection unit and a delay component thereof in advance. It is configured to detect a delay component that exceeds the selected reference level and that is within the time to be subjected to waveform equalization processing in the feedforward section of the equalization filter by comparing with the set selection reference level.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS If the level of a delay component of one symbol (data) is low, interference between symbols due to this delay component is small, and the rate of occurrence of data errors is extremely low. The tap output of the feedback section is
The tap output corresponding to the peak position due to the delay component or the like is high, and the tap outputs corresponding to other low components are low. Therefore, in the embodiment of the present invention, first, the received reception data is subjected to correlation processing with a known synchronization signal, and the synchronization signal in the reception data detected is converted into a leading component by a direct wave, a reflected wave, and the like. The delay component in the predetermined level range and time range is detected by the delay component detection unit from these synchronization signals.

Subsequently, a tap corresponding to the delay component occurrence position detected by the delay component detection unit among the plurality of taps in the feedback unit is selected by the tap selection unit, and the second tap to the feedback unit in the coefficient calculation unit is selected. Is calculated only for the selected tap. Of course, the values of the filter coefficients of the taps not selected are zero. With such a configuration, the amount of coefficient calculation in the coefficient calculation unit can be significantly reduced and the calculation processing time can be reduced as compared with the conventional example in which calculation is performed for all taps while suppressing data errors. And the amount of hardware required for the operation can be reduced. In addition, since a delay component having a larger delay amount can be easily removed, data errors can be further reduced.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment is different from the conventional data demodulation device shown in FIG. 3 in that the output signal CRS of the correlation processing unit 42 is extracted from the conventional synchronization signal detection unit 4x to form the synchronization signal detection unit 4. The correlation processing signal CRS from the correlation processing unit 42 of the synchronization signal detection unit 4 and the equalized data FFE from the feedforward unit 21 of the equalization filter 2
A selection reference level V _sr predetermined with reference to the level of D, etc.
, A synchronizing signal SYN (preceding component) from the synchronizing signal detecting unit 4 and a correlation processing unit 4
After extracting the delay components of the synchronization signal from the correlation processing signal CRS from
A delay component detection unit 8 that detects a delay component having a level larger than _sr and having a delay amount within a waveform equalization processing range by the feedforward unit 21, and a plurality of taps in a plurality of taps in a feedback unit 22 of the equalization filter 2. A tap selector 9 for selecting a tap corresponding to a position where the delay component detected by the delay component detector 8 is generated, and the received data RRD read from the reception memory 1 instead of the conventional coefficient calculator 6x. and on the basis of the determination data (DMD) and the error signal ER from the data determination unit 3, and in accordance with the timing signal TM _b for processing, the equalizing filter 2 of the plurality of feedforward module 21 taps TP first respective The filter coefficient CS _a and the tap selection unit 9 of the plurality of taps TP in the feedback unit 22
In the coefficient calculator 6 for a coefficient value 0 provided for calculating a second filter coefficient CS _b of only selected Tap Tap not selected, the conventional timing signal generating section 5x, tap selection lies in that the timing signal generator 5 in accordance with the number and location of the selected taps in part 9 by adding a function of generating a timing signal TM _b for coefficient calculation.

FIG. 2 is a view for explaining the operation of this embodiment, showing the relationship between the position of a selected tap and the timing waveform of each section signal for one symbol. The equalized data FFED from the feed-forward unit 21 of the equalizing filter 2 is output to the filter coefficients CS _a ,
Although the total number of taps of the operation target CS _b is reduced, because the coefficient value of the data out of calculation object of taps is small, it becomes substantially the same waveform as the conventional example. The feedback delay component signal FBDD output from the feedback unit 22 is such that only the output of the selected tap has its second filter coefficient CS
_It is determined by _b and appears at the position of the delay component (t1, t2, etc.) in the equalized data FFED with the level of the sign opposite to the level of the delay component.

The equalization data FFED and the feedback delay component signal FBDD are added by the addition circuit 23, and the delay components (t1, t2) of the equalization data FFED are added.
, Etc.) are removed (equalization processing data EQD) and supplied to the data determination unit 3. Therefore, even if the number of taps for coefficient subtraction is reduced, the interference removal effect and the occurrence rate of data errors are almost the same as in the conventional example.

In this embodiment, the calculation of the filter coefficient in the coefficient calculator 6 is performed by selecting all of the plurality of taps (the number of taps N1) in the feedforward section 21 and the plurality of taps (the number of taps N2) in the feedback section 22. This is performed for the selected tap (the number of taps n2).

Normally, taps in the feedforward section 21 and the feedback section 22 are provided at symbol intervals and in a number corresponding to the maximum delay time of the delay component to be subjected to interference removal. On the other hand, the number (n2) of delay components exceeding the selection reference level V _sr among the delay components due to reflection or the like is extremely small, so that the determinant of the filter coefficients CS _a and CS _b to be calculated by the coefficient calculator 6 is calculated. Number of rows and columns (N
1 + n2) is much smaller than (N1 + N2) of the conventional example, and the coefficient operation amount can be significantly reduced. Therefore, the operation processing time can be shortened and the hardware amount can be reduced. .

In addition, the reduction of the arithmetic processing time and the reduction in the amount of hardware facilitates the elimination of interference of delay components having a larger delay amount, so that data errors due to these delay components can be further reduced. The coefficient calculator 6
The reason _why the calculation processing time of the filter coefficients CS _a and CS _b is shortened is that the timing signal generator 5 generates a timing signal TM _b for calculation processing in accordance with the number and position of the selected taps. Timing signal TM _b
Since performing arithmetic processing in accordance with, it is because it is processing by the timing signal TM _b commensurate with the coefficient computation amount.

[0021]

As described above, according to the present invention, a predetermined level is obtained from a leading component and a delay component of a synchronization signal obtained by performing a correlation process on a received reception data with a known synchronization signal. Range and time range delay components,
The tap of the feedback unit corresponding to the detected delay component occurrence position is selected, and the calculation of the second filter coefficient to the feedback unit in the coefficient calculation unit is performed only for the selected tap. Thus, while suppressing data errors, the amount of coefficient operation in the coefficient operation unit can be significantly reduced, the operation processing time can be shortened, the hardware amount can be reduced, and a delay having a larger delay amount can be achieved. It is also possible to easily remove the components, which has the effect of further reducing data errors.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG. 1 and showing the relationship between the position of a selected tap and the timing waveform of each section signal for one symbol.

FIG. 3 is a block diagram illustrating an example of a conventional data demodulation device.

FIG. 4 is a timing waveform chart of signals of respective units for explaining the operation of the data demodulation device shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving memory 2 Equalization filter 3 Data determination unit 4, 4x Synchronization signal detection unit 5, 5x Timing signal generation unit 6, 6x Coefficient operation unit 7 Selection reference level generation unit 8 Delay component detection unit 9 Tap selection unit 21 Feed forward unit Reference Signs List 22 feedback section 23 addition circuit 41 known signal generation section 42 correlation processing section 43 level detection section AD adder DL delay circuit TOC tap output calculation section TP tap

Claims (3)

[Claims] 1. A data demodulation device having the following components. (B) Receive memory sequentially storing received data including a synchronization signal and data and sequentially reading the received data according to a read timing signal. (B) Receive data read from the receive memory at a data input end. And a transversal filter-type feed-forward section for multiplying and adding a first filter coefficient corresponding to the tap to each of a plurality of tap outputs to perform waveform equalization processing; A tap output of the transversal filter which multiplies each tap output by a second filter coefficient corresponding to the tap and adds the resultant to output a delay component signal of a negative level; output data of the feedforward section; And an adder circuit for adding the delayed component signal of (C) a data determination unit that performs a data determination process on the equalized data from the equalization filter and outputs the same as the determination data, and simultaneously outputs an error signal of the determination data. (D) the sequentially received data A synchronization signal detecting section for performing a correlation process between the synchronization signal and the known synchronization signal to detect a synchronization signal including a preceding component and a delay component thereof. (E) From a synchronization signal including the preceding component and the delay component from the synchronization signal detecting section, A delay component detection unit that detects a delay component in a predetermined level range and a time range; and (f) a generation position of a delay component detected by the delay component detection unit among a plurality of taps in a feedback unit of the equalization filter. A tap selection unit for selecting a corresponding tap; (g) reception data read from the reception memory and determination data from the data determination unit A first filter coefficient of each of a plurality of taps in a feedforward section of the equalization filter, and a tap selected by the tap selection section among a plurality of taps in a feedback section of the equalization filter, based on the error signal and the error signal. A coefficient calculator for calculating a second filter coefficient of only taps (h) a timing signal generator for generating the readout timing signal based on a synchronization signal of a preceding component from the synchronization signal detector; 2. The timing signal generating section generates a timing signal for calculating a coefficient in accordance with the number and position of taps selected by the tap selecting section, and the coefficient calculating section generates a timing signal for calculating the coefficient. The first according to the signal
The data demodulation device according to claim 1, wherein the filter coefficient and the second filter coefficient are calculated. 3. The delay component detection section compares a synchronization signal including the preceding component and the delay component from the synchronization signal detection section with a preset selection reference level, and exceeds the selection reference level, and 2. The data demodulation device according to claim 1, wherein a delay component within a waveform equalization processing target time in a feedforward section of the equalization filter is detected.