JP3971048B2 - Clock phase error detection circuit and clock phase error detection method - Google Patents

Description

[Technical Field]
The present invention relates to a clock phase error detection circuit and a clock phase for obtaining a clock phase error signal used for phase correction of a clock recovery circuit used in a receiving apparatus in a system for transmitting a digital signal using a band-limited pulse signal. The present invention relates to an error detection method.
[0001]
[Prior art]
In a system that transmits a digital signal using a band-limited pulse wave, code transmission is generally performed using a roll-off spectrum shaped pulse. For this reason, a slight shift in the sample timing on the receiving side causes the characteristics to deteriorate rapidly.
[0002]
Conventionally, simple sample timing, that is, clock recovery, rectifies an input signal, extracts a clock component, and passes the extracted clock component through a narrow-band castle pass filter to recover the clock. . However, in recent years, in order to save more transmission bandwidth, spectrum shaping characteristics with a small roll-off factor have been used, so that higher performance of clock recovery has been required.
[0003]
For example, a control method as shown in FIG. 11A has been proposed as a clock recovery circuit that meets such requirements. This is to detect the clock phase control signal before and after the zero cross point, and this control method will be referred to as the zero cross control method here.
[0004]
The zero cross control method will be described. FIG. 11A is a simplified illustration of an eye pattern of a binary digital signal. On average, there is no problem with the signal state itself. When this binary digital signal is sampled, the transmission code can be correctly fetched if the sample timing matches the signal phase as in S1 and S2, so that the data can be reproduced correctly.
[0005]
Next, as shown in FIG. 11A (b), let us consider what happens when the sample timing is delayed by Te seconds and shifted to the positions S1 ′ and S2 ′. In this case, the shift of the eye pattern of the binary digital signal is narrowed from W0 to W1 due to the shift from S1 to S1 ′, while the timing at which sampling should be performed at S2 which is the zero cross point position is also shifted by Te seconds. The input signal is sampled at the timing position of S2 'in (c) of FIG. 11A. If the sampled value (sample value) at this sampling timing is e, this e is essentially near zero. It takes a larger value than the expected value.
[0006]
In this case, if the transmission code changes from “−1” to “+1” before and after the zero cross point, the sample value takes a positive value e (− +), and conversely from “+1” to “−” When it changes to 1 ″, the sample value takes a negative value e (+ −). Therefore, by knowing the transmission code before and after the zero cross point, it is possible to know the difference in sample timing. This is the principle of zero cross control.
[0007]
Thus, the zero cross control method uses a value in the vicinity of the zero cross point, and thus has a feature that operates regardless of the eye pattern amplitude. However, the eye pattern actually has a waveform as shown in FIG. 12, and e (− +) and e (+ −) may not become zero even when the clock phase is synchronized. Since the control signal is generated, the problem that the jitter is large remains.
[0008]
On the other hand, a control method as shown in FIG. 11B has also been developed. This is a method of detecting a clock phase control signal before and after the eye pattern convergence point, and here it is referred to as an eye convergence point control method. That is, the eye convergence point control method is the following control method. FIG. 11B shows an eye pattern of a binary digital signal, and T-1, T0, and T1 of FIG. 11B show optimum clock phases. In this example, sampling is performed at the reference levels L1, L2, and L3 by a 2-bit A / D converter, but an example using a multilevel A / D converter is considered. When the transmission code changes to a-1, B0, and C1, if the clock phase is shifted by + Δt, the sample value becomes larger than the reference level L1, and if it is shifted by −Δt, the sample value is smaller than the reference level L1. Value.
[0009]
Therefore, it is possible to detect a sample timing shift based on the difference value between the transmission code before and after the control point and the reference level at the control point.
[0010]
As described above, since the eye convergence point control method uses values near the eye convergence point, the jitter at the time of phase synchronization can be reduced. However, when the amplitude of the eye pattern changes, there is a problem that the clock phase cannot be controlled because the difference value from the reference level does not accurately indicate a sample timing shift.
[0011]
Therefore, as a clock recovery circuit that solves these problems and improves the performance of clock recovery, a technique as shown in Japanese Patent Application No. 4-126041 (see Japanese Patent Application Laid-Open No. 5-327681) has been developed. .
[0012]
This is as shown in FIG. 13 and is called a clock phase error detection control method. This clock phase error detection control method will be described. FIG. 13A shows an eye pattern, in which the sample values of the eye convergence point are “L0” and “−L0”. Consider a case where the clock phase is shifted by “+ Δt”. If the transmission code changes to “A1” and “B2” in this state,
The sample value of “A1” is “− (L0−Δl)”, and the sample value of “B2” is “(L0 + Δl)”. Here, comparing the absolute values of the sample values,
| L0 + Δl | − | − (L0−Δl) | = 2Δl> 0
The sample value “B2” is larger in absolute value.
[0013]
When the transmission code changes to “B1” and “A2”, the sample value of “B1” is “(L0−Δl)”, and the sample value of “A2” is “− (L0 + Δl)”. Here, comparing the absolute values of the sample values,
| − (L0 + Δl) | − | (L0−Δl) | = 2Δl> 0
It can be seen that the sample value of “A2” is larger in absolute value.
[0014]
That is, when the clock phase is delayed (clock phase “+ Δt”), the absolute value of the two consecutive samples is larger in the latter value, and the clock phase is similarly advanced (clock phase “−Δt”). ), It can be seen that the absolute value of two consecutive samples is smaller in the latter value.
[0015]
Thereby, a phase difference can be obtained if an amplitude difference between two consecutive samples is obtained.
[0016]
That is, when the phase error in the clock phase error detection control method can be detected, as shown in FIG. 14, which is a diagram schematically showing the principle described in FIG. 13, four consecutive symbols of the input pulse code When the input pattern, which is the generation pattern, takes the positions of the symbols “A0”, “A1”, “B2”, “B3”, if the sample point is shifted by Δt, the phase error can be obtained as “2Δl”. I can do it.
[0017]
On the other hand, FIG. 15 shows an example in which the phase error cannot be detected. In this example, the input pattern of the input signal, which is the generation pattern of four consecutive symbols of the input pulse code, is the symbol “ If the sample point is shifted by Δt when taking the positions of B0, “A1,” “B2,” and “A3”, the phase error becomes “O” and cannot be obtained.
[0018]
Therefore, the phase error can be detected by the clock phase error detection control method disclosed in Japanese Patent Application No. 4-126041 between the time immediately before the sample timing T1 and the time immediately after the next sample timing T2. Only when it is decreasing.
[0019]
This is the case where the signal is as shown in FIG. 14, and the input pattern of four consecutive symbols takes positions “A0”, “A1”, “B2”, “B3”, and “B0”, “B1”. "," A2 ", and" A3 ". Since there are 16 input pattern variations of 4 consecutive symbols, the phase error can be detected by the clock phase error detection control method only with a probability of “1/8” with respect to the input data. The phase error can be obtained only with a low probability of "".
[0020]
As described above, since the probability that the phase error can be detected is low, clock regeneration at a low C / N is insufficient.
[0021]
[Problems to be solved by the invention]
In systems that transmit digital signals using band-limited pulse waves, spectrum shaping characteristics with a small roll-off factor are used to save transmission bandwidth, and thus higher performance of clock recovery is achieved. Has come to be required. As a clock recovery circuit that meets such requirements, a technique as shown in Japanese Patent Application No. 4-126041 (see Japanese Patent Application Laid-Open No. 5-327681) has been developed.
[0022]
However, the phase error can be detected by this technique only when the input signal is monotonously increasing or monotonically decreasing between immediately before the sample timing and immediately after the next sample timing.
[0023]
This is because there are only two input patterns, but there are 16 consecutive 4-symbol input patterns. Therefore, the phase error can be detected by the input data in the clock phase error detection control method. On the other hand, there is only a probability of “1/8”, and the phase error can be obtained only with a low probability of “1/8”.
[0024]
As described above, the conventional method has a low probability of detecting the phase error, so that there is a problem that the clock reproduction performance at a low C / N is insufficient.
[0025]
Therefore, an object of the present invention is to be able to detect a phase error with a high probability and obtain a clock phase error signal used for phase correction of a clock recovery circuit and satisfy a clock recovery performance at a low C / N. An object of the present invention is to provide a clock phase error detection circuit and a clock phase error detection method which can be performed.
[0026]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows. That is, in a clock phase error detection circuit that obtains a clock phase error signal for correction of a recovered clock phase used in a circuit that recovers a clock synchronized with a predetermined phase from a pulse code signal subjected to band limitation, the pulse code signal is converted into the clock signal. A phase error calculation that obtains a clock phase error signal by a predetermined phase error calculation from the determined code pattern and the signal obtained by sampling. Means. In particular, the phase error calculation means is configured by an FIR filter, and the phase error calculation is configured to switch the coefficient of the FIR filter in accordance with the detected code pattern.
[0027]
The present invention detects a code pattern of a signal obtained by sampling the pulse code signal with the clock to reproduce a clock synchronized with a predetermined phase from a band-limited pulse code signal, and determines a pattern. A phase error is obtained by a predetermined calculation from the determined code pattern and the signal obtained by sampling. The obtained phase error is used for phase correction for clock recovery.
[0028]
Further, when an FIR filter is used, the phase error calculation means can be easily configured, and the error calculation can detect the phase error in all the continuous code patterns by changing the filter coefficient to correspond to the input pattern. Thus, when a clock phase shift occurs during clock reproduction, the phase shift can be corrected quickly.
[0029]
In particular, the present invention detects a code pattern of a signal sampled by the clock in a circuit that regenerates a clock synchronized with a predetermined phase from a pulse code signal subjected to band limitation, and according to the detected code pattern. By calculating the phase error, it becomes possible to detect the phase error in all the continuous code patterns, so it is possible to detect the phase error in many cases, and therefore the probability that the phase error can be detected from the input signal. The clock reproduction performance at a low C / N (carrier noise ratio) can be improved.
[0030]
Therefore, according to the present invention, it is possible to perform clock recovery that satisfies the clock recovery performance at low C / N.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0032]
Example 1
A block diagram of an embodiment of the clock phase error detection circuit according to the present invention is shown in FIG. In the figure, 1 is a phase error calculation circuit, 2 is a pattern determination circuit, 3 is a level determination circuit, 4 is a validity determination circuit, 5 is a hold circuit, 6 is an input terminal, 7 is a threshold input terminal, and 8 is an output terminal. It is.
[0033]
Of these, the input terminal 6 receives an input signal obtained by sampling the received pulse code signal at the reproduction clock timing. The pulse code signal here is a pulse code signal subjected to band limitation. The phase error calculation circuit 1 performs an error calculation according to the sign pattern of the input signal, and gives error data as a calculation result to the hold circuit 5.
[0034]
The pattern determination circuit 2 is for determining the code pattern of the input signal input from the input terminal 6, and the level determination circuit 3 is for determining the level of the input signal input from the input terminal 6. In this case, it is detected that the level of the input signal is higher than the threshold value supplied from the threshold value input terminal 7.
[0035]
The validity determination circuit 4 determines whether the pattern determination result by the pattern determination circuit 2 and the level determination result by the level determination circuit 3 are satisfied at the same time, and is “valid” if satisfied, “invalid” otherwise. When the determination result of the validity determination circuit 4 is “valid”, the hold circuit 5 passes the error data output from the phase error calculation circuit 1 as it is, and uses this as the clock phase error signal. If the determination result of the validity determination circuit 4 is “invalid”, this is used as a hold signal, and the error signal of the phase error calculation circuit 1 immediately before is held and output as a clock phase error signal. A clock phase error signal from the hold circuit 5 is output to the output terminal 8.
[0036]
In this apparatus having such a configuration, an input signal obtained by sampling the pulse code signal at the reproduction clock timing is input from the input terminal 6. This input signal is branched to the phase error calculation circuit 1, the level determination circuit 3 and the pattern determination circuit 2.
[0037]
First, the level determination circuit 3 detects that the input signal level is higher than the threshold supplied from the threshold input terminal 7. Even if this threshold is too large or too small, it is a problem. Therefore, an optimum value is selected empirically according to the purpose. However, as shown in FIG. For example, “+ L0 / 2” and “−L0 / 2” which are values near 50% of the signal levels “+ L0” and “−L0” are preferable.
[0038]
In this embodiment, since the phase error is calculated using “4 samples” as will be described later, the level determination circuit 3 also confirms that “4 samples” consecutive in this level determination are simultaneously larger than the threshold value. Make a decision. The determination result is supplied to the validity determination circuit 4.
[0039]
Next, the pattern determination circuit 2 determines the code pattern of the “4 samples”. The determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for phase error calculation and also supplied to the validity determination circuit 4 to determine whether the pattern is effective for error calculation. Is done.
[0040]
The validity determination circuit 4 determines whether the pattern determination result and the level determination result are satisfied at the same time. That is, it is determined as “valid” when the code pattern of consecutive “4 samples” coincides with a pattern capable of performing phase error calculation and the signal amplitude is larger than a predetermined threshold value. If the above two determinations are not satisfied at the same time, it is determined as “invalid”, and the determination signal indicating “invalid” is supplied to the hold circuit 5 as a hold signal.
[0041]
On the other hand, the phase error calculation circuit 1 performs error calculation according to the sign pattern of the input signal, and supplies error data as the calculation result to the hold circuit 5. The hold circuit 5 outputs the error data supplied from the phase error calculation circuit 1 to the output terminal 8 as a clock phase error signal. However, when the hold signal is supplied from the validity determination circuit 4, the clock phase error signal immediately before is held, and it is determined that the error data supplied from the phase error calculation circuit 1 is “invalid”.
[0042]
Therefore, when the determination result of the validity determination circuit 4 is “valid”, the hold circuit 5 passes the error data output from the phase error calculation circuit 1 as it is, and outputs this to the output terminal 8 as a clock phase error signal. If the determination result of the validity determination circuit 4 is “invalid”, the error signal of the phase error calculation circuit 1 immediately before is held as a hold signal and is output to the output terminal 8 as a clock phase error signal.
<Configuration of phase error calculation circuit>
Next, a specific embodiment of the phase error calculation circuit 1 will be described with reference to FIG. As shown in FIG. 3, the phase error calculation circuit 1 includes serially connected delay elements 201, 202, 203, and 204, and a variable coefficient unit 205 that is supplied with delay outputs from these delay elements 201, 202, 203, and 204. , 206, 207, 208 and an adder 209 that adds the outputs of the variable coefficient units 205, 206, 207, 208.
[0043]
The sampling signal is supplied from the sampling signal input terminal 210. The sampling signal supplied from the sampling signal input terminal 210 is supplied in the order of the delay element 201, the delay element 202, the delay element 203, and the delay element 204. The delayed signals are amplified by the corresponding variable coefficient units 205, 206, 207, and 208 in accordance with the respective coefficients, and then added by the adder 209. Then, the error calculation is completed, and the error data is output from the output terminal 212 to the hold circuit 5.
[0044]
A coefficient switching signal is supplied to the input terminal 211 from the pattern determination circuit 2, and the coefficients C3, C2, C1, and C0 of the variable coefficient units 205, 206, 207, and 208 are controlled in accordance with the coefficient switching signal, and the filter characteristics. Switch.
[0045]
<Error calculation method>
The error calculation method will be described with reference to FIG. 4A shows a sampling signal supplied from the input terminal 210. FIG. The code patterns of the signals shown here are “A0” (= −L0), “A1” (= −L0), “B2” (= + L0) ”, and“ A3 ”(= + L0) in FIG. With respect to this code pattern, as shown in FIG. 4B, the coefficients of the variable coefficient unit (C0) 205, variable coefficient unit (C1) 206, variable coefficient unit (C2) 207, and variable coefficient unit (C3) 208 are calculated. When the FIR filter is configured by sequentially setting coefficients “−1”, “+2”, “0”, “−1”, respectively, the FIR filter output, that is, the error calculation result is when the clock delay is one clock. FIG. 4C shows “−3L0”, “0” when there is no clock delay, and “+ 3L0” when the clock advance is 1 clock.
[0046]
The coefficients in FIG. 4B indicate “C0 = −1”, “C1 = 2”, “C2 = 0”, “C3 = −1”, and the values shown in FIG. When the sample value is taken (sample value is “L0” or “−L0”), the phase error is “zero”, and the value at time t = 0 in FIG. 4C is the error calculation. It is a result.
[0047]
Here, consider a case where there is one clock phase error. Then, as can be seen from FIG. 4C, when the time is delayed by one clock, the time t is in the state of “t = −1”, and the filter output at this time is “−3L0”, which is advanced by one clock. In this case, since the time t is in the state of “t = + 1”, it can be seen that the filter output at this time is “+ 3L0”.
[0048]
The above is based on the value obtained by sampling the input signal. However, when a continuous signal with a band-limited pulse code is input, a continuous result as shown in FIG. 4D is obtained. This means that when a sampling timing deviation, that is, a sampling phase error occurs, the filter output changes in the vicinity of time t = 0 shown in FIG.
[0049]
As described above, in the phase error calculation circuit 1 in this embodiment, the filter output constituting the phase error calculation circuit 1 takes a positive value when the clock phase is delayed, and takes a negative value when the clock phase is delayed. Further, when there is no phase error, it becomes zero, so the filter output, that is, the output of the phase error calculation circuit 1 represents the phase error.
[0050]
FIG. 5 shows filter coefficients that allow error calculation in each input pattern. Although it differs depending on the symbol values before and after “4 symbols”, according to the phase error calculation circuit 1 configured by the filter of FIG. 3, all increase continuously from the phase delay time to the phase advance time as shown in FIG. Filter output can be obtained.
[0051]
Then, according to the phase error calculation circuit 1 configured by the filter of FIG. 3, among the “16 patterns” of the code pattern of “4 symbols”, as shown in FIG. 5, “16 patterns” can be calculated. It is.
[0052]
That is, when a phase error can be detected, the input pattern is [1] “A0”, “A1”, “B2”, When taking the arrangement of “B3”, [2] When taking the arrangement of “B0”, “B1”, “A2”, “A3”, [3] “A0”, “A1”, “B2”, “ When [4] “B0”, “B1”, “A2” and “B3” are arranged, [5] “A0”, “B1”, “A2” and “A3” are arranged. [6] “B0”, “A1”, “B2”, “B3”, [7] “A0”, “A1”, “A2”, “B3” [8] “B0”, “B1”, “B2”, “A3”, [9] “B0”, “A1”, “A2”, “A3” [1 ] When arranging “A0”, “B1”, “B2”, “B3”, [11] When arranging “A0”, “B1”, “B2”, “A3”, [12] “ [13] When taking the arrangement of “B0”, “A1”, “A2”, “B3”, [14] When taking the arrangement of “A0”, “B1”, “A2”, “B3”, [14] “B0” , “A1”, “B2”, “A3”, the phase error can be obtained in accordance with the phase shift of the sample points in the total 14 patterns.
[0053]
On the other hand, FIG. 7 shows an example in which a phase error could not be detected conventionally. In this example, when the input pattern is “B0”, “B1”, “B2”, “B3”, and , “A0”, “A1”, “A2”, “A3”, even if the sample points were shifted, the phase error was “O” and could not be obtained.
[0054]
However, this can also detect the phase error in the present invention.
[0055]
That is, the variation of the code pattern of “4 symbols” is [15] “B0”, “B1”, “B2”, “B3” as shown in FIG. “A1”, “A2”, “A3” are arranged, and there are a total of “16 patterns” including these, but such signs do not change “A0”, “A1”, “A2” , “A3” and two patterns including “B0”, “B1”, “B2”, and “B3” are calculated. This means that the phase error detection accuracy is higher than that of the conventional error calculation method.
[0056]
In order to prevent deterioration of the phase error detection accuracy due to a pattern judgment error at low C / N, if the amplitude of the sampling signal is smaller than a predetermined threshold value, the error calculation result is not used and immediately before The hold circuit 5 operates to hold the phase error signal.
[0057]
Then, using the phase error signal obtained via the hold circuit 5 as a phase control signal, the phase control of the clock recovery circuit is performed, and the phase shift of the recovered clock is corrected to correspond to the phase control signal.
[0058]
In this embodiment, if the sample points are shifted for a total of 16 patterns including 2 patterns in the case where the appearance of four consecutive symbols has no sign change, this phase error can be obtained in any case. Using the generated phase error signal as the phase control signal, the phase control of the clock recovery circuit can be performed, and the phase shift of the recovered clock can be corrected to correspond to the phase control signal. As a result, phase error signals can be obtained for all 16 patterns out of 16 patterns, which are all variations of the symbol arrangement, so that the phase error detection accuracy can be dramatically increased over the conventional error calculation method. When the phase shift occurs, the phase shift correction control can be performed promptly.
[0059]
Therefore, it is possible to detect the phase error with a high probability, and to obtain a clock phase error signal used for phase correction of the clock recovery circuit, so that the clock recovery performance at low C / N can be satisfied. A circuit is obtained.
[0060]
Next, another embodiment of the present invention will be described as a second embodiment.
[0061]
(Example 2)
FIG. 8 shows another embodiment of the present invention. In FIG. 8, 1 is a phase error calculation circuit, 502 is a pattern determination circuit, 3 is a level determination circuit, 4 is a validity determination circuit, 5 is a hold circuit, 6 is an input terminal, 7 is a threshold input terminal, and 8 is an output. A terminal 501 is an absolute value circuit for obtaining an absolute value of an input signal input from the input terminal 6.
[0062]
In this embodiment, an absolute value circuit 501 is provided in front of the phase error calculation circuit 1, and an input signal input to the input terminal 6 is supplied to the phase error calculation circuit 1 via the absolute value circuit 501, and The level determination circuit 3 is also different from the first embodiment in that the input signal input from the input terminal 6 is converted into an absolute value by the absolute value circuit 501 and the level is determined. Is basically the same as that of the first embodiment. However, in this embodiment, when the input signal sampled at the reproduction clock timing is input to the input terminal 6, the pattern determination circuit 502 determines the pattern for this.
[0063]
Further, the phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal by using the absolute value circuit 501 in which the code pattern of the input signal is converted into an absolute value as an input, and calculates error data as a calculation result. Is provided to the hold circuit 5.
[0064]
The level determination circuit 3 is used to determine the level of an input signal input from the input terminal 6 and converted to an absolute value by the absolute value circuit 501, and is supplied from the threshold input terminal 7. The validity determination circuit 4 detects whether the pattern determination result by the pattern determination circuit 502 and the level determination result by the level determination circuit 3 are satisfied at the same time. If it is satisfied if it is satisfied, it is determined to be “valid”, and if not satisfied, it is determined to be “invalid”. The hold circuit 5 determines that the determination result of the validity determination circuit 4 is “valid”. Passes the error data output from the phase error calculation circuit 1 as it is and outputs it as a clock phase error signal. If the determination result of the validity determination circuit 4 is “invalid”, this is hall Holds the error signal of the phase error calculation circuit 1 in the immediately preceding a signal, and outputs a clock phase error signal. A clock phase error signal from the hold circuit 5 is output to the output terminal 8.
[0065]
In this apparatus having such a configuration, an input signal sampled at the reproduction clock timing is input from the input terminal 6. This input signal is branched to the absolute value circuit 501 and the pattern determination circuit 502.
[0066]
Then, the absolute value circuit 501 performs absolute value conversion of the input signal and then supplies it to the phase error calculation circuit 1 and the level determination circuit 3. Accordingly, the phase error calculation circuit 1 and the level determination circuit 3 are given the absolute value of the sign pattern of the input signal.
[0067]
The level determination circuit 3 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using “4 samples”, it is determined in this level determination that consecutive “4 samples” are simultaneously larger than the threshold value. The determination result is supplied to the validity determination circuit 4.
[0068]
The pattern determination circuit 502 determines the code pattern of the “4 samples” for the input signal from the input terminal 6. The determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for phase error calculation, and is also supplied to the validity determination circuit 4 in order to determine whether the pattern is effective for error calculation. The
[0069]
The validity determination circuit 4 determines whether the pattern determination result and the level determination result are satisfied at the same time. That is, it is determined as “valid” when the code pattern of consecutive “4 samples” coincides with a pattern capable of performing phase error calculation and the signal amplitude is larger than a predetermined threshold value. If the above two determinations are not satisfied at the same time, it is determined as “invalid”, and the determination signal indicating “invalid” is supplied to the hold circuit 5 as a hold signal.
[0070]
On the other hand, the phase error calculation circuit 1 performs an error calculation according to the sign pattern of the input signal converted to an absolute value, and supplies error data as a calculation result to the hold circuit 5. The hold circuit 5 outputs the error data supplied from the phase error calculation circuit 1 to the output terminal 8 as a clock phase error signal. However, when the hold signal is supplied from the validity determination circuit 4, the clock phase error signal immediately before is held, and it is determined that the error data supplied from the phase error calculation circuit 1 is “invalid”.
[0071]
Therefore, when the determination result of the validity determination circuit 4 is “valid”, the hold circuit 5 passes the error data output from the phase error calculation circuit 1 as it is, and outputs this to the output terminal 8 as a clock phase error signal. If the determination result of the validity determination circuit 4 is “invalid”, the error signal of the phase error calculation circuit 1 immediately before is held as a hold signal and is output to the output terminal 8 as a clock phase error signal.
[0072]
Then, using this phase error signal as a clock phase error signal, the phase of the clock recovery circuit is controlled by the amount corresponding to this signal, and the phase shift of the recovered clock is corrected to correspond to the phase control signal.
[0073]
As described above, this embodiment is characterized in that the error calculation is performed on the input signal subjected to the absolute value conversion.
[0074]
That is, in this embodiment, the difference from the first embodiment will be described with reference to FIG. In order to obtain the same error calculation result as that of the above embodiment for an input signal subjected to absolute value conversion, a variable coefficient through which a symbol whose sign is converted by absolute value conversion, that is, a signal having a negative value, passes. What is necessary is just to change the code of the vessel. This can be easily determined from the configuration of the FIR filter.
[0075]
Therefore, when the filter coefficients having the 16 variations shown in FIG. 5 are subjected to code conversion when the corresponding input pattern is a negative value and the variations are reduced, the filter coefficients are changed as shown in FIG. Here, paying attention to variations of filter coefficients, there are seven types of filter coefficients: “A”, “A ′”, “B”, “B ′”, “C”, “C ′”, “D”. I understand.
[0076]
That is, the number of filter coefficients can be reduced by converting the input signal to an absolute value.
[0077]
This means that the circuit configuration is simplified, that is, the circuit scale is reduced and control is facilitated. It can also be seen that the filter coefficient variations “A” and “A ′”, “B” and “B ′”, and “C” and “C ′” only have the signs of the coefficients inverted. For example, when the filter coefficient of the variation “A ′” is required, an error calculation is performed using the filter coefficient of the variation “A”, and the sign of the calculation result is inverted, so that the filter coefficient of the variation “A ′” is used. The result is exactly the same as the error calculation.
[0078]
By doing so, only four types of filter coefficients are required, and it can be seen that error calculation is possible if these four types of filter coefficients are prepared.
[0079]
Then, using the phase error signal obtained via the hold circuit 5 as a phase control signal, phase control of the clock recovery circuit is performed, and the phase shift of the recovered clock is corrected to correspond to the phase control signal.
[0080]
In this example, if the sample point is shifted in all 16 patterns including 2 patterns when the appearance form of four consecutive symbols has no sign change, this phase error can be obtained in any case, By using the obtained phase error signal (clock phase error signal) as a clock phase control signal, clock phase control of the clock recovery circuit can be performed, and the phase shift of the recovered clock can be corrected in correspondence with the phase control signal. As a result, phase error signals can be obtained for all 16 patterns of 16 patterns, which are all variations of the symbol arrangement, so that the phase error detection accuracy can be dramatically increased over the conventional error calculation method. When the phase shift occurs, the phase shift correction control can be performed promptly.
[0081]
In addition, in this embodiment, the absolute value of the input signal is converted to an absolute value, and the number of filter coefficients used in the filter constituting the phase error calculation circuit is converted from the 16 patterns in the case where the absolute value is not converted, to 7 patterns which are half of them. Further, it can be reduced to 4 patterns. Therefore, the circuit configuration can be simplified, that is, the circuit scale can be reduced and control can be facilitated.
[0082]
Therefore, it is possible to detect the phase error with a high probability, and to obtain a clock phase error signal used for phase correction of the clock recovery circuit, so that the clock recovery performance at low C / N can be satisfied. A circuit is obtained.
[0083]
(Example 3)
FIG. 10 shows a case of a receiver that demodulates quadrature amplitude modulation, for example, a QPSK modulation signal, in an application example of the above embodiment.
[0084]
Since the QPSK modulation signal is composed of an I signal and a Q signal, an error calculation is performed for each of the I signal and the Q signal, and a phase error signal is output from each validity determination result. Basically, the configuration shown in FIG. 8 is prepared for two systems for the I signal and for the Q signal. For the I signal system, the absolute value circuit 501, the phase error calculation circuit 1, The pattern determination circuit 502, the level determination circuit 3, and the validity determination circuit 4 are configured. For the Q signal system, an absolute value circuit 706, a phase error calculation circuit 701, a pattern determination circuit 702, and a level determination circuit 703 are used. And a validity determination circuit 704.
[0085]
Here, the absolute value circuit 706 is the absolute circuit 501, the phase error calculation circuit 701 is the phase error calculation circuit 1, the pattern determination circuit 702 is the pattern determination circuit 502, the level determination circuit 703 is the level determination circuit 3, and the validity determination is performed. The circuit 704 is the same as the validity determination circuit 4.
[0086]
In addition to this configuration, an averaging circuit 707, a selector 708, a delay circuit 709, and an IQ determination circuit 710 are added. The averaging circuit 707 takes the average of the error data from the I signal and the error data from the Q signal. The average circuit 707 receives the outputs of the phase error calculation circuit 1 and the phase error calculation circuit 701 to obtain the average value of these. To the selector 708.
[0087]
The selector 708 receives the output of the phase error calculation circuit 1 and the output of the phase error calculation circuit 701, the output of the averaging circuit 707, and the output of the delay circuit 709, and either one of them corresponds to the selection signal of the IQ determination circuit 710. Select and output.
[0088]
Further, the IQ determination circuit 710 determines that both systems are “valid” based on the validity determination result of the I signal system output from the validity determination circuit 4 and the validity determination result from the Q signal system output from the validity determination circuit 704. In this case, the output of the averaging circuit 707 is output, and when only the validity determination result of the I signal system is “effective”, the output of the phase error arithmetic circuit 1 is output, and only the validity determination result of the Q signal system is “effective. The selection signal is generated so as to select the output of the phase error calculation circuit 701 in the case of "" and the output of the delay circuit 709 in the case where both the I signal system and the Q signal system are "invalid". This is given to the selector 708.
[0089]
The delay circuit 709 delays the output of the selector 708 by one clock and outputs it again to the selector 708, and obtains a phase error signal delayed by one clock. Therefore, although the hold circuit is not provided in the third embodiment, the delay circuit 709 and the selector 708 serve as the hold circuit in the second embodiment.
[0090]
In this apparatus having such a configuration, the I signal sampled at the reproduction clock timing is input from the input terminal 6, and the Q signal sampled at the reproduction clock timing is input from the input terminal 705.
[0091]
The input I signal is branched to the absolute value circuit 501 and the pattern determination circuit 502, and the input Q signal is branched to the absolute value circuit 706 and the pattern determination circuit 702.
[0092]
Then, the absolute value circuit 501 of the I signal system to which the I signal is input performs absolute value conversion of the input signal and then supplies it to the phase error calculation circuit 1 and the level determination circuit 3. Accordingly, the phase error calculation circuit 1 and the level determination circuit 3 are given the absolute value of the sign pattern of the input signal.
[0093]
The level determination circuit 3 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using “4 samples”, it is determined in this level determination that consecutive “4 samples” are simultaneously larger than the threshold value. The determination result is supplied to the validity determination circuit 4.
[0094]
The pattern determination circuit 502 determines the code pattern of the “4 samples” for the I signal that is a direct input signal from the input terminal 6. The determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for phase error calculation, and is also supplied to the validity determination circuit 4 in order to determine whether the pattern is effective for error calculation. The
[0095]
The validity determination circuit 4 determines whether the pattern determination result and the level determination result are satisfied at the same time. That is, it is determined as “valid” when the code pattern of consecutive “4 samples” coincides with a pattern capable of performing phase error calculation and the signal amplitude is larger than a predetermined threshold value. If the above two determinations are not satisfied at the same time, it is determined as “invalid”, and the determination signal “invalid” is supplied to the IQ determination circuit 710 as a hold signal.
[0096]
On the other hand, the phase error calculation circuit 1 performs an error calculation according to the sign pattern of the input signal converted into an absolute value, and calculates the I error data (error calculation result of the I signal system) as the calculation result as an average circuit 707 and a selector 708. To supply. The averaging circuit 707 outputs the averaged result of the Q error data (the Q signal system error calculation result) from the Q signal system phase error calculation circuit 701, and gives it to the selector 708.
[0097]
On the other hand, the absolute value circuit 706 of the Q signal system to which the Q signal is input performs absolute value conversion of the input signal and then supplies it to the phase error calculation circuit 701 and the level determination circuit 703. Therefore, the phase error calculation circuit 701 and the level determination circuit 703 are given the absolute value of the sign pattern of the input signal.
[0098]
The level determination circuit 703 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using “4 samples”, it is determined in this level determination that consecutive “4 samples” are simultaneously larger than the threshold value. The determination result is supplied to the validity determination circuit 4.
[0099]
The pattern determination circuit 702 determines the code pattern of the “4 samples” for the Q signal that is a direct input signal from the input terminal 705. The determination result is supplied to the phase error calculation circuit 701 as a coefficient switching signal for phase error calculation, and is also supplied to the validity determination circuit 704 to determine whether the pattern is effective for error calculation. The
[0100]
The validity determination circuit 704 determines whether the pattern determination result and the level determination result are satisfied at the same time. That is, it is determined as “valid” when the code pattern of consecutive “4 samples” coincides with a pattern capable of performing phase error calculation and the signal amplitude is larger than a predetermined threshold value. If the above two determinations are not satisfied at the same time, it is determined as “invalid”, and the determination signal “invalid” is supplied to the IQ determination circuit 710 as a hold signal.
[0101]
On the other hand, the phase error calculation circuit 701 performs an error calculation according to the sign pattern of the input signal that has been converted to an absolute value, and calculates Q error data (error calculation result of the Q signal system) as the calculation result as an average circuit 707 and a selector. 708. Then, the averaging circuit 707 outputs the averaged result of the I error data (error calculation result of the I signal system) from the phase error calculation circuit 1 for the I signal system, and gives it to the selector 708.
[0102]
The IQ determination circuit 710 to which the validity determination result of the I error data and the validity determination result of the Q error data are supplied performs the validity determination, and outputs a switching signal corresponding to the determination result to the selector 708.
[0103]
That is, when the determination of the IQ determination circuit 710 is “valid for only the I signal”, the I error data from the phase error calculation circuit 1 is selected so as to select error data from the I signal, and the determination of the IQ determination circuit 710 When Q is “valid only for Q signal”, the Q error data from the phase error calculation circuit 701 is selected so as to select error data from the Q signal, and the IQ determination circuit 710 determines that both the I signal and the Q signal are When “invalid”, the output of the delay circuit 709 is selected so as to select error data one clock before, and when the judgment of the IQ judgment circuit 710 is “both I signal and Q signal are valid”, the error from the I signal The output of the averaging circuit 707 is selected so as to select the average data of the error data from the data and the Q signal, and the output is output to the output terminal 711 as a clock phase error signal.
[0104]
That is, the system of the third embodiment is provided with error calculation and validity determination functions for the I signal system and the Q signal system, and the averaging circuit 707 averages the error data from the I signal and the error data from the Q signal. Is supplied to the selector 708, and the selector 708 is also supplied with error data from the I signal, error data from the Q signal, and a phase error signal obtained by delaying the output of the selector 708 by one clock. In 710, a switching signal is output to the selector 708 based on the validity judgment result from the I signal and the validity judgment result from the Q signal. When the validity judgment is only the I signal, error data from the I signal is selected. In addition, when the validity judgment is only the Q signal, error data from the Q signal is selected, and when both the I signal and the Q signal are “invalid”, one count is selected. The phase error signal delayed by the clock signal, and when both the I signal and the Q signal are “valid”, the average of the error data from the I signal and the error data from the Q signal is selected, and the clock phase Output as an error signal. Then, using this clock phase error signal as a phase control signal for correcting the phase shift of the recovered clock, the phase control of the clock recovery circuit is performed, and the phase shift of the recovered clock is corrected to correspond to the phase control signal. I did it. As a result, even in the QPSK system, it is possible to further improve the phase error detection accuracy.
[0105]
Note that the present invention is not limited to the QPSK system, and can of course be applied to a modulation system such as the BPSK system or the 8PSK system.
[0106]
【The invention's effect】
As described above, according to the present invention, it is possible to greatly increase the number of input patterns capable of calculating a phase error, so that the clock recovery performance can be greatly improved. Therefore, it is possible to detect the phase error with a high probability, and to obtain a clock phase error signal used for phase correction of the clock recovery circuit, so that the clock recovery performance at low C / N can be satisfied. A circuit and clock phase error detection method can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a clock phase error detection circuit as an embodiment of the present invention.
FIG. 2 is a diagram for explaining an example of setting a threshold value of a level determination circuit used in the device of the present invention;
FIG. 3 is a block diagram showing a configuration example of a phase error calculation circuit used in the device of the present invention.
FIG. 4 is a diagram for explaining an operation example of a clock phase error detection circuit according to the present invention;
FIG. 5 is a correspondence diagram between input signal patterns and filter coefficients of the phase error calculation circuit of the present invention.
FIG. 6 is a diagram for explaining a pattern of an input signal.
FIG. 7 is a diagram for explaining a pattern of an input signal that has not been able to detect a clock phase error at all in the past.
FIG. 8 is a block diagram illustrating another embodiment of the clock phase error detection circuit of the present invention.
FIG. 9 is a correspondence diagram between an input pattern and a filter coefficient of a phase error calculation circuit in another embodiment of the present invention.
FIG. 10 is a block diagram showing an example of a clock phase error detection circuit of the present invention when applied to quadrature detection output.
FIG. 11 is a diagram for explaining a conventional technique.
FIG. 12 is a diagram illustrating an example of an eye pattern.
FIG. 13 is a diagram for explaining a conventional technique.
FIG. 14 is a diagram schematically illustrating a conventional clock phase error detection method.
FIG. 15 is a diagram schematically illustrating a conventional clock phase error detection method for explaining a pattern of an input signal that cannot be detected by a clock phase error.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,701 ... Phase error calculating circuit 2,502,702 ... Pattern judgment circuit, 3,703 ... Level judgment circuit, 4,704 ... Valid judgment circuit, 5 ... Hold circuit, 501,706 ... Absolute value circuit, 707 ... Average circuit, 708... Selector, 709... Delay circuit, 710.

Claims (7)

In a clock phase error detection circuit that obtains a clock phase error signal for correction of a recovered clock phase used in a circuit that recovers a clock synchronized with a predetermined phase from a pulse code signal subjected to band limitation,
Determination means for determining a pattern by detecting a code pattern of a signal obtained by sampling the pulse code signal with the clock; and
Of the plurality of phase error calculations corresponding to each of the code patterns, the corresponding phase error calculation is selected based on the determination result of the determination unit, and the signal obtained by sampling by the phase error calculation is processed to A clock phase error detection circuit comprising phase error calculation means for obtaining a clock phase error signal. 2. The clock phase error detection circuit according to claim 1, wherein the phase error calculation in the phase error calculation means is calculated for four consecutive symbols. The phase error calculation means comprises the FIR ( Finite Impulse Response ) filter having a plurality of coefficients corresponding to each of the code patterns , and the plurality of phase error calculations. 2. The clock phase error detection circuit according to claim 1, wherein a coefficient of the FIR filter is switched according to a determination result of the pattern determination means . Furthermore, a level determination circuit for detecting that the pulse code signal subjected to the band limitation is larger than a predetermined amplitude,
Said phase error calculating means, the pulse code signal is pre-defined clock phase error detection circuit of claims 1 to 3 any one wherein the performing the phase error calculation when greater than the amplitude. Said phase error calculation was carried out in each of the I and Q signals, each phase error calculation results an average value of, characterized in that the phase error detection signal according to claim 1 to 4 set forth in any one clock phase Error detection circuit. In reproducing a clock synchronized with a predetermined phase from a pulse code signal subjected to band limitation,
A phase error corresponding to the determined code pattern among a plurality of phase error operations corresponding to each of the code patterns is detected by detecting a code pattern of a signal obtained by sampling the pulse code signal with the clock. A clock phase characterized by selecting a calculation and processing the signal obtained by sampling by the phase error calculation to obtain a phase error of the clock and using the obtained phase error for phase correction of clock recovery. Error detection method.   In a receiving apparatus of a system for transmitting a band-limited pulse code signal,
  A clock recovery circuit that receives the pulse code signal and recovers a clock synchronized with a predetermined phase from the signal;
  A clock phase error detection circuit for detecting a phase error of a clock recovered by the clock recovery circuit;
  A clock phase control means based on the clock phase error obtained by the clock phase error detection circuit;
  The clock phase error detection circuit is configured to determine a pattern by detecting a code pattern of a signal obtained by sampling the pulse code signal with the clock; and
  Of the plurality of phase error calculations corresponding to each of the code patterns, the determination unit determines And a phase error calculation unit that selects a corresponding phase error calculation based on the result and processes the signal obtained by sampling by the phase error calculation to obtain the clock phase error signal. .

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