JPH11261460A - Data demodulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce data errors without lengthening a processing time so much and to eliminate confusion after data demodulation by regarding data of many errors as zero level data. SOLUTION: This device is provided with a decision feedback equalization/decision part 4 and a maximum likelihood estimation part 5 of data errors fewer than the former. The device is provided with a decision data memory 6 for storing decision data of the decision feedback equalization/decision part 4 and an equalization difference detection part 8 for detecting an equalization difference. This device is also provided with an estimation data memory 7 for storing the estimation data of the maximum likelihood estimation part 5 and an estimation difference detection part 9 for detecting the estimation difference. Also, a zero interpolation memory 11 for storing zero level data is provided. Further, the device is provided with a difference amount decision/ switching control part 10 and a selection read circuit 12, which read storage data for the decision data memory 6 when the equalization difference does not exceed the first reference level, and which read the storage data of the estimation data memory 7 if the estimation difference does not exceed the second reference level when the equalization difference exceeds the reference level, and which read the storage data of the zero interpolation memory 11 area when the estimation defference exceeds the second reference level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data demodulator, and more particularly to a data demodulator having a function of reducing fluctuations in the level of a received signal in wireless data communication to reduce data errors.

[0002]

2. Description of the Related Art In wireless data communication, fading occurs due to the state of a data propagation path, and the level of a received signal and the like fluctuate greatly. In order to reduce the data error by suppressing such level fluctuation of the received signal, the data demodulator is usually provided with a data error reduction measure. Representative examples of data error reduction measures include a decision feedback equalization method and a maximum likelihood estimation method.

In the decision feedback equalization method, a function of removing interference between data due to a direct wave and a delayed wave in fading by feeding back a result of data decision to an equalizer is provided. The maximum likelihood estimation method calculates a likelihood relationship for a transmission data sequence including a response characteristic of a propagation path and a corresponding reception data sequence, and calculates a likelihood function having a maximum value of a likelihood function within a predetermined period. In this method, data is sequentially output as demodulated data, and the data receiving side selects a data sequence that is considered to be closest to the transmission data sequence.

[0004] In these methods, the data error during a predetermined period is smaller in the maximum likelihood estimation method, but the processing time is significantly longer in the maximum likelihood estimation method than in the decision feedback equalization method. , Processing time is too long,
Conventionally, a decision feedback equalization method has been used because real-time processing is difficult.

FIG. 4 shows an example of a conventional data demodulator using a decision feedback equalization system. This data demodulation device sequentially oversamples received data RD detected and detected by a receiver (not shown), stores the data, and sequentially reads the received data RD in accordance with a read timing signal TMa.
And the synchronization signal S included in the reception data RD from the receiver.
A synchronizing signal detector 2 for extracting YN, a timing signal TMa for reading and a timing signal TMb for equalizing processing based on the synchronizing signal SYN from the synchronizing signal detector 2
And a feedback signal (FBD) for the reception data RRD read from the reception memory 1x, and performs an equalization process by a predetermined operation in accordance with the timing signal generating unit 3x that generates the data and the feedback signal (FBD) read from the reception memory 1x. The equalizer 41 and the equalization processing data E of the equalizer 41
D, and outputs the demodulated data DMD as feedback data (FBD) to the equalizer 41 at the same time.
2 and a decision feedback equalization / determination unit 4x having the same.

The received data RD is sequentially transmitted in units of a frame FRM including a synchronizing signal portion (16 bits) Fsyn including a synchronizing signal SYN and a data portion (32 bits) Fdt as shown in FIG. come,
The synchronizing signal SYN is extracted by the synchronizing signal detector 2.

Further, by performing a predetermined operation between the received data RRD and the feedback data (FBD) in the equalizer 41, it is possible to remove interference between data due to fading.

[0008]

In this conventional data demodulator, a decision feedback equalization method (decision feedback equalization / judgment unit 4x) having a short processing time is employed as a data error reduction measure. Although real-time processing is possible, there is a problem that the data error is larger than the maximum likelihood estimation method.
Even if the number of data errors increases, the demodulated data DM
Since the data is output as D, there is a problem that confusion due to error data occurs on the side using the demodulated data DMD.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to further reduce data errors without prolonging the processing time and to prevent the output of erroneous data so that the demodulated data is not used. To provide a data demodulation device that eliminates confusion.

[0010]

A data demodulator according to the present invention is characterized by having the following components in order to achieve the above object. (A) Receive memory sequentially storing received data in units of frames including a synchronization signal and data, and sequentially read out from the earliest stored frame in accordance with a read timing signal. (B) From the receive memory A decision feedback equalization and data decision unit that performs decision feedback equalization processing and data decision processing on the read reception data according to a timing signal for equalization processing. (C) For the reception data read from the reception memory, A maximum likelihood estimating unit for performing a maximum likelihood estimation process in accordance with a timing signal for the estimation process; (d) a decision data memory for storing the decision data of the decision feedback equalization / data decision unit; Estimated data memory for storing (f) 0 interpolation memory for storing 0 level data (g) The decision feedback equalization / data decision unit An equalization error detection unit that detects an error in the equalization processing on a frame basis; (h) an estimation error detection unit that detects an error in the estimation processing of the maximum likelihood estimation unit on a frame basis; If the determined error does not exceed a predetermined first reference level, the determination data corresponding to the error is read from the determination data memory unit,
If the error is exceeded, the error detected by the estimated error detection unit does not exceed a predetermined second reference level, and the estimated data in the estimated data memory unit corresponding to the error is read. An error amount judging / selection reading section for reading out the 0 level data of the section.
If the reference level does not exceed the reference level, the readout timing signal and the equalization processing timing signal based on the synchronizing signal of the next frame so as to immediately start each process of the next frame after determining the error amount of this error. And generating a timing signal for the estimation process, and when the error detected by the equalization error detection unit exceeds the first reference level, immediately after the error detection process by the estimation error detection unit is completed, A timing signal generator for generating the readout timing signal, the equalization processing timing signal, and the estimation processing timing signal based on the synchronization signal of the next frame so as to enter each processing of the next frame;

Further, when a new frame arrives at the reception memory, and a frame preceding the new frame is not completely read and remains in the reception memory, a frame transmitted to the reception memory is not read. Reading data stored in the receiving memory at a speed higher than the transmission speed;
And the time interval between the timing signal for reading from the timing signal generator and the timing signal for the equalization process is short so that the equalization process and the judgment process by the decision feedback equalization / judgment unit are performed, and The reading speed of the determination data memory, the estimation data memory, and the 0 interpolation memory by the error amount determination / selection read unit is configured to match the timing signal.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiment of the present invention, first, reception data sequentially stored in a reception memory is sequentially read from a frame stored first according to a timing signal for reading, and a decision feedback equalization / determination section is provided. , The estimation process is performed by the maximum likelihood estimation unit at the same time as performing the equalization process and the data determination process, and the processed data is stored in the determination data memory and the estimation data memory. Further, a 0 interpolation memory for storing 0 level data is provided.

On the other hand, the equalization error in the decision feedback equalization / determination section is detected by the equalization error detection section, and the estimation error in the maximum likelihood estimation section is detected by the estimation error detection section. If the equalization error does not exceed the predetermined first reference level, the storage data in the determination data memory is read out. If the equalization error does not exceed the first reference level, the estimation error detected by the estimation error detection unit is equal to the predetermined second reference level. If it does not exceed the reference level of 2, the stored data of the above-mentioned estimated data memory is read, and if it exceeds, the stored data of the 0 interpolation memory is read.

If the equalization error does not exceed the first reference level by the timing signal generating section, immediately after the error amount determination / selection reading section finishes the equalization error amount determination processing, if the equalization error exceeds the first reference level, the maximum likelihood estimation is made. Immediately after the completion of each processing of one frame by the unit and the estimation error detection unit, a readout timing signal, a timing signal for equalization processing, and a timing signal for estimation processing for starting processing of the next frame are generated.

With this configuration, when the number of data errors by the decision feedback equalization / determination unit increases, the estimated data by the maximum likelihood estimation unit with a small data error is output. When the number of data errors increases, 0 data is output. Therefore, the period during which data is output from the maximum likelihood estimating unit having a long processing time is minimized to further reduce data errors without prolonging the entire processing time. In addition, since data having many errors is output as 0-level data, confusion caused by data having many errors on the demodulated data use side can be eliminated.

Further, when a frame which has not been read remains in the reception memory, the generation time intervals of the timing signal for reading and the timing signal for equalization processing are adjusted to the processing time of the decision feedback equalization / determination section. By shortening, the time required for the equalization processing and the determination processing is shorter than the transmission time of the transmitted frame, and the processing time lengthened by the maximum likelihood estimation unit and the estimation error detection unit is shortened and restored. be able to.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing waveform chart of signals of respective parts for explaining the operation of this embodiment. In this embodiment, a reception memory 1 for sequentially storing received data RD sequentially transmitted in frame units and sequentially reading out from a frame stored first in accordance with a timing signal TMa for readout, and a readout from this receive memory 1 A decision feedback equalization / determination unit 4 that performs decision feedback equalization processing on the received data RRD in accordance with a timing signal TMb for equalization processing and then performs data decision processing, and a reception read from the reception memory 1. A timing signal TMc for estimation processing is applied to the data RRD.
Maximum likelihood estimating unit 5 which performs maximum likelihood estimation processing according to
A decision data memory 6 for storing the decision data EJD from the decision feedback equalization / determination section 4, an estimation data memory 7 for storing the estimation data from the maximum likelihood estimation section 5, and a 0 interpolation for storing the 0 level data. Error memory 8, an equalization error detection unit 8 for detecting an equalization error in the decision feedback equalization / determination unit 4 for each frame, and an estimation error detection unit 9 for detecting an estimation error in the maximum likelihood estimation unit 5 for each frame. And the equalization error EQE detected by the equalization error detection unit 8 is compared with a predetermined first reference level Vr1, and at the same time, the estimation error ESE detected by the estimation error detection unit 9 is compared with a predetermined second reference level Vr1. And if the equalization error EQE does not exceed the first reference level Vr1, the first level, the equalization error EQE exceeds the first reference level Vr1, and
If the estimated error ESE does not exceed the second reference level Vr2, the readout selection signal RSL of the second level is output if the estimated error ESE exceeds the second reference level Vr2, and if the equalization error EQE does not exceed the first reference level Vr1. An error amount determination for outputting a switching signal SW of a first level, and a second level if exceeding
The switching control unit 10 reads the data stored in the determination data memory 6 when the read selection signal RSL is at the first level (DMDa), and reads the data stored in the estimation data memory 7 when the read selection signal RSL is at the second level (DMDb). In the case of the third level, the selection reading circuit 12 reads out the data stored in the 0 interpolation memory 11 and outputs it as demodulated data DMD, and the synchronization signal detection section 2 extracts the synchronization signal SYN of the received data RD sent. When the switching signal SW is at the first level, immediately after the error amount determination / switching control unit 10 completes the error amount determination processing of the equalization error EQE, when the switching signal SW is at the second level, the maximum likelihood estimation unit 5 Immediately after the estimation and detection processes by the error detection unit 9, the timing signal TMa for reading, the timing signal TMb for equalization, and the timing signal TMb for each process of the next frame are entered. Timing signal TM for the estimation process
c is stored in the receiving memory 1 without reading out a frame preceding the frame of the received data RD sent to the receiving memory 1.
And a timing signal generator 3 which is generated based on the synchronizing signal SYN from the synchronizing signal detector 2 if there is no remaining frame.

Next, the operation of this embodiment will be described.
As shown in FIG. 2, the received data RD is transmitted from the first frame of the frame number F1 to the frame numbers F2 and F3.
It is assumed that they are sequentially and sequentially transmitted. The frames of the received received data RD are sequentially oversampled from the frame number F1 (hereinafter, referred to as F1 frame, and the like) and stored in the reception memory 1. Further, the synchronization signal detecting section 2 determines the synchronization signal S of the F1 frame.
Extract YN. When the F1 frame has been sent, no unread frames remain in the reception memory 1, so the timing signal generator 3 reads the timing signal TMa for reading based on the synchronization signal SYN from the synchronization signal detector 2. , A timing signal TMb for the equalization process and a timing signal TMc for the estimation process.

The receiving memory 1 reads out the data (RRD) of the F1 frame stored in accordance with the timing signal for reading out, and the read-back data is subjected to equalization processing and data determination by the decision feedback equalization / determination section 4. The processing is performed according to the timing signal TMb for the equalization processing, and the maximum likelihood estimation unit 5 performs the estimation processing according to the timing signal TMc for the estimation processing. In parallel with this, the equalization error detection section 8 detects the equalization error by the decision feedback equalization / determination section 4 by detecting the difference between the equalization processing data and the decision feedback data. , The estimation error detection unit 9 and the maximum likelihood estimation unit 5
Is detected by determining the value of the likelihood function.

When the F1 frame equalization processing and data determination processing are completed, the equalization error detection processing is also completed. Therefore, the error amount determination and switching control unit 10 determines whether the equalization error EQE has exceeded the first reference level Vr1. Is determined. In the example of FIG. 2, the error amount determination / switch control unit 10
, And a readout selection signal RSL. The selection read circuit 12 outputs the read selection signal RS
According to L, the data stored in the determination data memory 6 is read and output as demodulated data DMD.

On the other hand, the estimating process of the maximum likelihood estimating unit 5 is interrupted by the switching signal SW to prepare for the estimating process of the next frame (F2). In addition, the timing signal generator 3 starts generating a read timing signal TMa, a timing signal TMb for equalization processing, and a timing signal TMc for estimation processing for starting each processing of the next frame (F2 frame). I do. At this time (at the time of detecting the synchronization signal of the transmitted F2 frame), no data of the unread frame remains in the reception memory 1, and therefore these timing signals are determined based on the synchronization signal SYN from the synchronization signal detection unit 2. (TM
a, TMb, TMc).

The same processing as that for the F1 frame is performed for the F2 frame. In FIG. 2, since the equalization error EQE has exceeded the first reference level Vr1, the error amount determination / switch control unit 10 outputs the second level switch signal SW, and the maximum likelihood estimation unit 5 performs the estimation process. It is determined whether or not the estimation error ESE has exceeded the second reference level Vr2 when the estimation process and the estimation error detection process for the F2 frame are completed. Since it does not exceed in FIG. 2, the error amount determination / switch control unit 10 outputs a second-level read selection signal RSL. The data stored in the estimation data memory 7 is read in accordance with the second level read selection signal RSL and output as demodulated data DMD.

As soon as each processing by the maximum likelihood estimating unit 5 and the estimation error detecting unit 9 is completed, the read timing signal TM for starting the processing of the next frame (F3 frame).
a, a timing signal TMb for the equalization process and a timing signal TMc for the estimation process are output from the timing signal generator 3, and each process of the F3 frame is started.
Whether or not each process of the maximum likelihood estimating unit 5 and the like has been completed can be detected by the timing signal TMc for the estimation process.

In the F3 frame, the equalization error EQE is equal to the first
And the estimated error ESE also exceeds the second reference level, the selective read circuit 12 reads the 0 level data 0D from the 0 interpolation memory 11 and outputs it as demodulated data DMD.

Thereafter, by the same operation, in the F4 frame, the equalization error EQE exceeds the first reference level Vr1, and the estimation error ESE does not exceed the second reference level Vr2. DMDb) is read out, and since the equalization error EQE and the estimation error ESE do not exceed the reference levels Vr1 and Vr2 in the F5 frame, the storage data (DMDa) in the determination data memory 6 is read out and output as demodulated data DMD. You.

That is, if the equalization error EQE exceeds the first reference level Vr2 due to an increase in data errors by the decision feedback equalizer / determiner 4, the maximum likelihood estimator 5 with less data errors.
Is output as the demodulated data DMD, and the maximum likelihood estimating unit 5 further increases data errors, and the estimation error ESE is reduced to the second reference level Vr2.
Is exceeded, 0 data 0D of the 0 interpolation memory 11 is output.

Accordingly, the period during which the maximum likelihood estimating unit 5 having a long processing time outputs the estimated data MLS can be minimized, and the data error can be further reduced without excessively increasing the entire processing time. In addition, since the 0-level data is output for data having many errors even in the maximum likelihood estimation, confusion caused by data having many errors can be eliminated on the demodulated data use side.

FIG. 3 is a diagram showing the generation time intervals of the read-out timing signal TMa and the equalization processing timing signal TMb from the timing signal generator 3 in FIG. 1, the judgment data memory 6, the estimation data memory 7, and the 0 interpolation. FIG. 7 is a timing waveform chart of another embodiment in which the reading speed of the memory for use 11 is changed. In this embodiment, when the synchronization signal SYN of the frame newly sent to the reception memory 1 is detected by the synchronization signal detection unit 2, the frame before the new frame is not completely read out to the reception memory 1 yet. If the frame remains, it is based on the synchronization signal of the unread frame, and is matched with the equalization process and the determination process of the decision feedback equalization / determination unit 4 (normally, much faster than the maximum likelihood estimation process, and the frame transmission rate Faster in many cases), the data stored in the reception memory 1 is read out at a speed higher than the transmission speed of the frame sent to the reception memory 1, and the decision feedback equalization / determination unit 4 performs the equalization process and the determination process. The timing signal TMa for reading and the timing signal TM for equalization processing
The time interval of occurrence of b is shortened, and at the same time,
The reading speed of the judgment data memory 6, the estimation data memory 7, and the 0 interpolation memory 11 is increased.

Therefore, if the switching signal SW does not exceed the first level, that is, the equalization error EQE does not exceed the first reference level Vr1 (F5 and subsequent frames), the decision feedback equalization / determination unit that is faster than the frame transmission speed. The data stored in the reception memory 1 and the data stored in the determination data memory 6 can be read out in synchronization with the processing time of No. 4 and the frames left unread in the reception memory 1 can be eliminated. The processing time lengthened by the estimation processing can be shortened and restored. That is, a newly transmitted frame (F8 frame and thereafter) can be immediately processed in real time.

In these embodiments, the synchronizing signal (SYN) to the timing signal generator 3 is received from the synchronizing signal detector 2 if no unread frame remains in the reception memory 1, and the synchronizing signal (SYN) if the frame remains. The synchronization signal of the frame remaining in the memory 1 is detected (read out) and supplied. However, the received reception data RD is temporarily stored in the reception memory 1 without providing the synchronization signal detection unit 2. After that, the readout timing signal TMa or the like may be newly generated based on the synchronization signal detected by reading out the synchronization signal.

The difference in processing time between the decision feedback equalization / determination unit 4 and the maximum likelihood estimation unit 5 is determined, for example, by providing the maximum likelihood estimation unit 5 with a buffer memory for temporarily holding the read data of the reception memory 1. For example, the reception memory 1 may be divided into one for processing such as decision feedback and one for maximum likelihood estimation, and the readout timing may be separately set.

[0032]

As described above, according to the present invention, when the equalization error by the decision feedback equalization / judgment section exceeds the reference level, the estimation data from the maximum likelihood estimation section having few data errors is output as demodulated data. Since the estimation error of the likelihood estimation unit also outputs the 0-level data when it exceeds the reference level, the output period of the estimation data by the longest likelihood estimation unit with a long processing time is minimized to reduce the entire processing time. Data errors can be further reduced without lengthening, and since data with errors is output as 0-level data, there is an effect that confusion caused by data with errors on the demodulated data use side can be eliminated.

When an unread frame remains in the reception memory, the transmission time of the transmitted frame is reduced by shortening the time interval between the generation of the read timing signal and the timing signal for the equalization processing. By shortening the time required for processing, etc., the time lengthened by the maximum likelihood estimation processing can be shortened and restored, and the data error can be reduced and the data with many errors can be reduced almost without increasing the overall processing time. Therefore, there is an effect that confusion on the demodulated data use side due to the above can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing waveform chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a timing waveform chart of signals of respective parts for explaining the operation of another embodiment of the present invention.

FIG. 4 is a block diagram illustrating an example of a conventional data demodulation device.

FIG. 5 is a diagram illustrating a frame configuration of received data that is demodulated by a data demodulation device.

[Explanation of symbols]

 1, 1x reception memory 2 synchronization signal detector 3, 3x timing signal generator 4, 4x decision feedback equalization / determination unit 5 maximum likelihood estimation unit 6 decision data memory 7 estimation data memory 8 equalization error detection unit 9 estimation error detection Unit 10 Error amount judgment / switch control unit 11 0 Interpolation memory 12 Selective readout circuit

Claims (2)

[Claims] 1. A data demodulation device having the following components. (A) Receive memory sequentially storing received data in units of frames including a synchronization signal and data, and sequentially read out from the earliest stored frame in accordance with a read timing signal. (B) From the receive memory A decision feedback equalization and data decision unit that performs decision feedback equalization processing and data decision processing on the read reception data according to a timing signal for equalization processing. (C) For the reception data read from the reception memory, A maximum likelihood estimating unit for performing a maximum likelihood estimation process in accordance with a timing signal for the estimation process; (d) a decision data memory for storing the decision data of the decision feedback equalization / data decision unit; Estimated data memory for storing (f) 0 interpolation memory for storing 0 level data (g) The decision feedback equalization / data decision unit An equalization error detection unit that detects an error in the equalization processing on a frame basis; (h) an estimation error detection unit that detects an error in the estimation processing of the maximum likelihood estimation unit on a frame basis; If the determined error does not exceed a predetermined first reference level, the determination data corresponding to the error is read from the determination data memory unit,
If the error is exceeded, the error detected by the estimated error detection unit does not exceed a predetermined second reference level, and the estimated data in the estimated data memory unit corresponding to the error is read. An error amount judging / selection reading section for reading out the 0 level data of the section.
If the reference level does not exceed the reference level, the readout timing signal and the equalization processing timing signal based on the synchronizing signal of the next frame so as to immediately start each process of the next frame after determining the error amount of this error. And generating a timing signal for the estimation process, and when the error detected by the equalization error detection unit exceeds the first reference level, immediately after the error detection process by the estimation error detection unit is completed, A timing signal generator for generating the readout timing signal, the equalization processing timing signal, and the estimation processing timing signal based on the synchronization signal of the next frame so as to enter each processing of the next frame; 2. When a new frame arrives at the reception memory, and a frame preceding the new frame is not read out and remains in the reception memory, a frame transmitted to the reception memory is read. A read timing signal and the like from the timing signal generation unit so as to read the data stored in the reception memory at a speed higher than the transmission speed, and perform the equalization process and the judgment process by the judgment feedback equalization / judgment unit. The generation time interval of the timing signal for the conversion process is short, and the determination data memory, the estimation data memory, and the 0
2. The data demodulation device according to claim 1, wherein a reading speed of the interpolation memory matches the timing signal.