JPH11261238A - Multi-layer printed wiring board and electronic device mounted there with - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce radiation noise of a multi-layer printed wiring board wherein a signal line crossing split power source patterns is formed. SOLUTION: At a first signal layer 12 a clock signal pattern 5' where high frequency current flows is formed. Under the first signal layer 12, a power source layer 13 where a 5V power source pattern 3a and a 3.3 V power source pattern 3b insulated by a non-pattern part 20 are formed is provided with a ground layer 14 provided under it. At a second signal layer 15 provided under the ground layer 14, power source-ground bypass capacitor lands 8a and 9a conducting to the 5 V power source pattern 3a and the 3.3 V power source pattern 3b of the power source layer 13, respectively, are formed, with the power source-ground bypass capacitor connecting them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board on which electronic components for complying with EMC (electromagnetic compatibility) are mounted, and to an electronic device equipped with the multilayer printed wiring board.

[0002]

2. Description of the Related Art As the speed of electronic equipment has increased, the clock frequency of digital circuits has been steadily increasing. However, in a digital circuit of a used printed wiring board, disturbance of a signal waveform due to reflection becomes a problem, causing a malfunction or the like. In addition, unnecessary radiation noise or the like generated therefrom may cause other electronic devices to malfunction. As one method for addressing these problems, a multilayer printed wiring board having a dedicated power supply layer and a ground layer is used to stabilize the power supply and the ground.

FIG. 6 is a plan view showing a multilayer printed wiring board having a general power supply pattern structure having a power supply voltage of 5 V for each layer.

This conventional example is a printed wiring board having a four-layer structure, in which (a) is a plan view of an uppermost first signal layer 112,
(B) is a plan view of a power supply layer 113 provided below the first signal layer 112, (c) is a plan view of a ground layer 114 provided below the power supply layer 113, and (d) is a lowermost layer. Second
3 is a plan view of the signal layer 115 of FIG. In the figure, (b) to (d) are shown in perspective to clarify the mutual positional relationship, and (b) to (b) to clarify the positional relationship with the LSI land 101 in (a). In (d), the position of the LSI land 101 is indicated by a broken line.

FIG. 6 shows a part of a multilayer printed wiring board composed of four layers in order to explain the present embodiment in an easily understandable manner. The actual substrate is larger and has many components mounted thereon. ing.

Hereinafter, the structure of each layer will be described in detail.

As shown in FIG. 1A, the first signal layer 112 has an LSI land 10 on which a QFP type LSI is mounted.
1. an IC land 102 on which an SOP type IC is mounted;
These LSI land 101 and IC land 102
5V power supply pattern 103 connected to the power supply land
a, a ground pattern 104, a signal pattern 105, a clock signal pattern 105 ′ for transmitting a clock signal, and a through-hole land 106 electrically connected to a through-hole for interlayer connection, which are connected to the ground land of the LSI and the IC. Have been.

[0008] As shown in FIG.
V power pattern 103a, through hole land 106,
A clearance hole 107 is formed. The 5V power supply pattern 103a is electrically connected to the land 106 for a through hole, and is further electrically connected to the 5V power supply pattern 103a of the first signal layer and a 5V power supply pattern 103a of a second signal layer 115 described later via the through hole. It is connected to the. The clearance hole 107 is provided in the power supply layer 11.
3 and the through hole and 5V
The outer peripheral portion electrically insulates the power supply pattern 103a.

As shown in FIG. 1C, the ground pattern 114 and the through-hole land 1 are formed on the ground layer 114.
06, a clearance hole 107 is formed. The ground pattern 104 is electrically connected to the land 106 for a through hole, and the clearance hole 107 is constituted by a through hole penetrating the ground layer 114 and an outer peripheral portion for electrically insulating the through hole from the ground pattern 104. .

The second signal layer 115 has a 5V power supply pattern 103a and a ground pattern 10 as shown in FIG.
4. Lands 106 for through holes, and lands 108a, 108b, 109a and 109b for power supply-ground bypass capacitors arranged between the power supply of the LSI and the IC and the ground are formed. 5V power supply pattern 103a
Are electrically connected to the 5V power supply pattern 103a of the power supply layer 113 through the through holes. Lands 108a and 108b for bypass capacitor between power supply and ground
Are connected to the power supply layer 113 via the through-hole land 106.
5V power supply pattern 103a and power supply-ground bypass capacitor lands 109a and 109b
Ground layer 114 via land 106 for through hole
Are electrically connected to the respective ground patterns 104.

In the case of the structure of the multilayer printed wiring board as described above, the power supply layer 113 immediately below the clock signal pattern 105 'mainly returns the high-frequency current flowing through the clock signal pattern 105'.

The flow path of the high-frequency current will be described below with reference to FIG. 7, which shows a circuit configuration in consideration of the cross-sectional structure of the four-layer printed wiring board shown in FIG.

The 5V power supply line 203a is electrically connected to a 5V power supply 205 for supplying power, and the ground line 204 is grounded to a ground 206. Also,
A power supply-ground bypass capacitor 208 is connected to the power supply terminals of the buffer circuit 201 and the IC circuit 200. 5V power line 203a and ground line 20
4, a stray capacitance 207 as shown by a broken line, which functions as a capacitor, is derived.

The buffer circuit 201 in the LSI includes an IC
A clock signal is output to the circuit 200, and the clock signal flows through the clock signal line 202 as a current 209. From the IC circuit 200 to the buffer circuit 201,
Return current 212 flows with the 5V power supply line 203a as the return path.

The main elements in FIGS. 6 and 7 are as follows. The clock signal line 202 to which the clock signal is transmitted is connected to the clock signal pattern 105 ′ of the first signal layer 112.
The 5V power supply line 203a is on the 5V power supply pattern 103a of the power supply layer 112, and the ground line 204 is on the ground layer 1
This corresponds to the fourteen ground patterns 104, respectively.

In general, when considering the radiation in the differential mode, the electric field strength in the direction of the maximum radiation is expressed by the following equation (1).
(“Practical noise reduction technique” p324, Jatec Publishing) E = 263 × 10 ⁻¹⁶ (f ² AI) (1 / r) (Equation 1) where E is the electric field strength [V / m], and f is the frequency [ H
z], A is the loop area [m ² ], I is the current [A], r
Represents the distance [m] to the receiving antenna. From the above equation 1, the electric field strength E is proportional to the loop area A.
That is, it is desirable that the loop area A of the high-frequency current I at which unnecessary radiation noise poses a problem is reduced as much as possible. In order to reduce the loop area, it is desirable that the digital signal line be as short as possible and that the ground or power supply pattern through which the return current flows be arranged as close to the signal line as possible. In addition, a loop area A of a clock signal line through which a high-frequency signal flows among digital circuits needs to be reduced.

The 5V power supply pattern 103a corresponding to the 5V power supply line 203a has a thin plate shape as shown in FIG. 6B, and exists immediately below the signal line 202. The current 209 and the return current 21
2, the loop area 214 formed is reduced, and unnecessary radiation noise is suppressed.

[0018]

However, in recent years, there has been a demand for low power consumption and the like. For example, in a digital circuit, a power supply is divided into 5 V and 3.3 V power supplies, or a power supply is divided even at the same voltage in accordance with a demand for power management. The case is getting more. In this case, the power supply layer is not a continuous single pattern but a discontinuous divided pattern.

Since the power supply layer also serves as a return path for the high-frequency current flowing through the signal line disposed near the power supply layer, when the signal line is disposed so as to cross the separated power supply pattern, the return current is It cannot flow near the signal current.

FIG. 8 requires two power supply voltages.
FIG. 3 is a plan view showing a multilayer printed wiring board having divided power supply patterns for each layer. This conventional example also has a four-layer structure similarly to the above-described conventional example. However, in the power supply layer 133 shown in FIG. 5B, a 5V power supply pattern 123a is electrically connected to a QFP type LSI requiring a 5V voltage. And 3.
A 3.3V power supply pattern 123b is electrically connected to an SOP type IC requiring a 3V voltage.
5V power supply pattern 123a and 3.3V power supply pattern 12
3b is insulated by being divided by the non-pattern part 120. The clock signal pattern 125 ′ of the first signal layer 132 in FIG. 11A is a power supply layer 133 that divides the 5 V power supply pattern 123 a and the 3.3 V power supply pattern 123 b.
Is formed so as to traverse the non-pattern portion 120.

FIG. 8 shows a part of a multilayer printed wiring board composed of four layers in order to explain the present embodiment in an easy-to-understand manner, and the actual substrate is larger and has many components mounted thereon. ing.

FIG. 9 is a circuit diagram showing a circuit configuration in consideration of the cross-sectional structure of the four-layer printed wiring board shown in FIG. The clock signal line 302 to which the clock signal is transmitted is connected to the clock signal pattern 125 ′ of the first signal layer 132.
The 5V power supply line 303a is a 5V power supply pattern 123a.
The 3.3V power line 303b corresponds to the 3.3V power pattern 123b, and the non-connection portion 311 corresponds to the non-pattern portion 120. Other configurations are the same as those in FIG.

Since the 5V power supply line 303a and the 3.3V power supply line 303b immediately below the clock signal line 302 are divided by the non-connection portion 311, the return current 312 indicated by the broken line can return to the buffer circuit 301 via the shortest path. The return is made via a path such as the stray capacitance 307, so that the loop area 314 formed by the current 309 and the return current 312 increases, and the unnecessary radiation noise also increases. Accordingly, the present invention provides a multilayer printed wiring board in which unnecessary radiation noise generated by a multilayer printed wiring board in which signal lines traversing between divided power supply patterns are formed, and the multilayer printed wiring board on which electronic components are mounted It is an object to provide an electronic device equipped with a board.

[0024]

In order to achieve the above object, a multilayer printed wiring board according to the present invention is provided with an electronic component for outputting a high-frequency signal, and at least a signal line through which the high-frequency signal output from the electronic component flows. A first signal layer provided; a power supply layer provided below the first signal layer for supplying power to the electronic component; and a ground provided below the power supply layer and provided with a reference potential. And a second signal layer provided in a lowermost layer below the ground layer, wherein the electronic component is electrically connected to the power supply layer, the ground layer, and the second signal layer. And the power supply layer has a conductive pattern divided by a discontinuous portion in a direction intersecting with the signal line at a position where the signal line is projected. Signal line Beside, that at least one capacitor is mounted in a position transverse to the discontinuous portion,
The divided conductive patterns are connected at a high frequency.

In the multilayer printed wiring board of the present invention configured as described above, since the divided conductive patterns of the power supply layer are connected by the capacitor, the return current does not use the stray capacitance as the return but connects the capacitor to the return path. Since the current flows through the return path, the loop area formed by the current flowing through the signal line and the return current is reduced, so that unnecessary radiation noise is reduced.

The power supply layer may be composed of a first conductive pattern and a second conductive pattern for supplying powers having different voltages to the electronic components. Alternatively, the power supply layer may include a first conductive pattern and a second conductive pattern. It may be composed of a conductive pattern and a third conductive pattern having the same voltage as the first conductive pattern, which is connected to a power supply that automatically stops power supply when not used for a long time.

The capacitor may be connected to the first conductive pattern and the second conductive pattern,
It may be composed of a first capacitor that connects the first conductive pattern and the third conductive pattern, and a second capacitor that connects the first conductive pattern and the third conductive pattern.

Further, the capacitor may be mounted on the first signal layer or may be mounted on the second signal layer.

An electronic device according to the present invention is provided with any one of the above-described multilayer printed wiring boards according to the present invention, thereby reducing unnecessary radiation noise generated from the electronic device.

[0030]

Next, embodiments of the present invention will be described with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing a multilayer printed wiring board of this embodiment for each layer.

(A) is a plan view of the uppermost first signal layer 12, (b) is a plan view of a power supply layer 13 provided below the first signal layer 12, and (c) is a power supply layer 13. FIG. 3D is a plan view of a ground layer 14 provided in a lower layer, and FIG. 4D is a plan view of a lowermost second signal layer 15. (B) to (d) are shown in a perspective view in order to clarify the mutual positional relationship, and in order to clarify the positional relationship with the LSI land 1 in (a),
(B) to (d) show the positions of the LSI lands 1 by broken lines.

FIG. 1 shows a part of a multilayer printed wiring board composed of four layers in order to explain the present embodiment in an easily understandable manner. The actual substrate is larger and has many components mounted thereon. ing.

Hereinafter, the structure of each layer will be described in detail.

As shown in FIG. 1A, the first signal layer 12 has an LSI land 1 on which a QFP type LSI is mounted,
IC land 2 on which SOP type IC is mounted, 5 connected to supply 5 V power to QFP type LSI.
3.3V for V power supply pattern 3a and SOP type IC
3.3 V power supply pattern 3 b connected to supply voltage power, ground pattern 4 connected to ground land of LSI and IC, signal pattern 5, clock signal pattern 5 ′ for transmitting a clock signal, interlayer connection Lands 6, 6a, and 6b that are electrically connected to through holes for the through holes are formed.

The power supply layer 13 has a voltage of 5 V as shown in FIG.
Power supply pattern 3a, 3.3V power supply pattern 3b, through hole lands 6, 6a, 6b, clearance hole 7
Are formed. The 5V power supply pattern 3a is electrically connected to the through-hole lands 6 and 6a, and the 3.3V power supply pattern 3b is electrically connected to the through-hole lands 6 and 6b. The 5V power supply pattern 3a is connected to the 5V power supply pattern 3a of the first signal layer 12 through the through-hole. 3.3V power supply pattern 3b and a second
Are connected to the 5V power supply pattern 3a and the 3.3V power supply pattern 3b of the signal layer 15, respectively. The clearance hole 7 includes a through hole penetrating the power supply layer 13 and an outer peripheral portion that insulates the through hole from the 5V power supply pattern 3a and the 3.3V power supply pattern 3b. In the case of the present embodiment, the power supply layer 13 includes the 5V power supply pattern 3a.
And a 3.3V power supply pattern 3b, both of which are insulated by the non-pattern portion 20. The clock signal pattern 5 ′ of the first signal layer 12 in FIG. 6A is formed so as to cross the non-pattern portion 20 that divides the 5 V power supply pattern 3 a and the 3.3 V power supply pattern 3 b of the power supply layer 13.

In the ground layer 14, as shown in FIG.
A ground pattern 4, lands 6 for through holes, and clearance holes 7, 7a, 7b are formed. The ground pattern 4 is electrically connected to the land 6 for a through hole, and the clearance holes 7, 7a, 7b are constituted by a through hole penetrating the ground layer 14, and an outer peripheral portion for insulating the through hole from the ground pattern 4. I have.

As shown in (d), the second signal layer 15 has the 5 V power supply pattern 3 a and the 3.3 V power supply pattern 3.
b, ground pattern 4, land 6 for through hole, L
Between the power supply-ground bypass capacitor lands 8a and 9a disposed between the 5V power supply of SI and the ground, and between the power supply-ground bypass capacitor lands 8b and 9b disposed between the 3.3V power supply and the ground of the IC, between the power supplies Lands 10 and 11 for a bypass capacitor are formed.
The 5V power supply pattern 3a and the 3.3V power supply pattern 3b are electrically connected to the 5V power supply pattern 3a and the 3.3V power supply pattern 3b of the power supply layer 13 through through holes, respectively. The land 10 for the bypass capacitor between power supplies is
And the 5V power supply pattern 3a of the power supply layer 13 is electrically connected to the 5V power supply pattern 3a of the signal layer 15 through the through hole. The land 11 for the bypass capacitor between power supplies is
3.3V power supply pattern 3b of power supply layer 13 via 3.3V power supply pattern 3b of second signal layer 15 and through hole
It is conducting. Land 1 for bypass capacitor between power supplies
A chip-type capacitor (not shown) for power supply bypass is mounted and connected between the lands 0 and 11. Land 8 for bypass capacitor between power supply and ground
a and 8b are power supply layers 13 via the through-hole lands 6.
The power supply pattern 3a and the power supply-ground bypass capacitor lands 9a and 9b are electrically connected to the ground pattern 4 of the ground layer 14 via the through-hole lands 6, respectively.

The above-described four-layer printed wiring board is composed of a QFP type LSI and an SOP disposed on the first signal layer 12.
The signal pattern 5 and the clock signal pattern 5 ′ connecting the ICs of the molds are arranged across the boundary between the 5 V power supply pattern 3 a and the 3.3 V power supply pattern 3 b formed on the power supply layer 13, that is, the non-pattern portion 20. I have. In particular, the clock signal pattern 5 'easily becomes an unnecessary radiation noise source because a high-frequency current flows.

FIG. 2 is a circuit diagram showing a circuit configuration in consideration of the sectional structure of the four-layer printed wiring board shown in FIG.
The clock signal line 402 to which the clock signal is transmitted is connected to the clock signal pattern 5 ′ of the first signal layer 12 by 5V.
The power supply line 403a is a 5V power supply pattern 3 of the power supply layer 13.
a, the 3.3V power supply line 403b is connected to the power supply layer 13 at 3.3V.
The ground line 404 corresponds to the ground pattern 4 of the ground layer 14, and the ground line 404 corresponds to the 3V power supply pattern 3b.
The connection portion 411 corresponds to the lands 10 and 11 for the bypass capacitor between power sources.

The power supply line 403a is connected to a 5V power supply 405 for supplying power, and the power supply line 403b is connected to 3.3V.
The power supply lines 403 a and 403 b are electrically connected to a V power supply 410, respectively, and are connected by an inter-power supply bypass capacitor 413. Ground line 40
4 is grounded to the ground 406. A power supply-ground bypass capacitor 408 is connected to the power supply terminals of the buffer circuit 401 and the IC circuit 400.
The stray capacitance 407 shown by the broken line is a 5V power supply line 403a.
Or 3.3V power line 403b and ground line 4
It was derived during 04.

The buffer circuit 401 in the LSI includes an IC
A clock signal is output to the circuit 400, and the signal flows through the clock signal line 402 as a high-frequency current 409. A return current 412 flows from the IC circuit 400 to the buffer circuit 401 with the 3.3 V power supply line 403 b, the inter-power supply bypass capacitor 413, and the 5 V power supply line 203 a as return paths.

With the above configuration, the loop area 414 formed by the current 409 and the return current 412 becomes
The loop area 314 is smaller than the loop area 314 formed by the return current 312 passing through the current 309 and the stray capacitance 307 shown in FIG. 9, so that unnecessary radiation noise can be reduced.

(Second Embodiment) FIG. 3 is a plan view showing the multilayer printed wiring board of this embodiment for each layer, as in the first embodiment.

The basic structure of each layer is the same as in the first embodiment. Hereinafter, features of the present embodiment that are different from the first embodiment will be described. As shown in (a), the first signal layer 32 is electrically connected to a second 5V power supply pattern 23c of a power supply layer 33 and lands 32, 33 for a bypass capacitor between power supplies of the second signal layer 35, which will be described later. In addition, through-hole lands 26c ₁ and 26c ₂ are newly provided.

FIG. 3 shows a part of a multilayer printed wiring board composed of four layers in order to explain the present embodiment in an easily understandable manner. The actual substrate is larger and has many components mounted thereon. ing.

The power supply layer 33 has a first
5V power supply pattern 23a and 3.3V power supply pattern 2
Three power supply patterns are formed, including a power supply pattern 3b and a second 5V power supply pattern 23c which is automatically turned off when not used for a long time. Also, the first 5V power supply pattern 23
a between the second 5V power supply pattern 23c and the second 5V power supply pattern 23c.
The non-pattern portions 40b are insulated from each other between the power supply patterns 23b.

The ground layer 34 is provided with new clearance holes 27c ₁ and 27c ₂ as shown in FIG.

[0048] The second signal layer 35 (d), the second 5V power supply pattern 23c ₁ and 23c _2, and the power supply between the bypass capacitor for the land 32 33 are newly provided. Second 5V power supply pattern 23c ₁ and 23c ₂ are respectively conducted through the through hole in the second 5V power supply pattern 23c of the power supply layer 33. The power supply between the bypass capacitor lands 32 and the second 5V power supply pattern 23c _1, the inter-power supply bypass capacitor for the land 33 is electrically connected respectively to the second 5V power supply pattern 23c _2.

Chip-type capacitors (not shown) for bypass between power supplies are mounted and connected between the lands 30 and 32 and between lands 31 and 33 for bypass capacitors between power supplies.

In the four-layer printed wiring board as described above, the QFP type LSI and the S
A signal pattern 25 and a clock signal pattern 25 ′ connecting the OP-type ICs are arranged across the non-pattern portions 40 a and 40 b formed on the power supply layer 33. In particular, the clock signal pattern 25 'tends to be a source of unnecessary radiation noise because a high-frequency current flows.

In this embodiment, the clock signal pattern 2
A path for the return current to flow in the vicinity of 5 'is connected to a bypass capacitor between power supplies by lands 30 and 3 for bypass between power supplies.
2 and between 31 and 33, a route is secured by connecting one each. Thereby, the loop area is reduced for the same reason as in the first embodiment, so that unnecessary radiation noise can be reduced.

(Third Embodiment) FIG. 4 is a plan view showing the multilayer printed wiring board of this embodiment for each layer, as in the first and second embodiments. The components constituting the first signal layer 52, the ground layer 54, and the second signal layer 55 of the present embodiment are the first signal layer 12, the ground layer 14, and the second signal layer 15 of the first embodiment. And respectively.
Although the elements constituting the power supply layer 53 are basically the same as the power supply layer 33 of the second embodiment, the second 5V power supply pattern 43c of the power supply layer 53 of the present embodiment is different from that of the second embodiment. that through-holes 26c ₁ and 26c ₂ which was present in the power supply layer 33 in the form is omitted is different.

FIG. 4 shows a part of a multilayer printed wiring board composed of four layers for easy understanding of the present embodiment. The actual substrate is larger and has many components mounted thereon. ing.

As described above, in the formed four-layer printed wiring board, the QFPs arranged on the first signal layer 52
A signal pattern 45 and a clock signal pattern 45 ′ connecting the type LSI and the SOP type IC are arranged across the non-pattern portions 60 a and 60 b formed in the power supply layer 53. In particular, the clock pattern 45 'tends to be a source of unnecessary radiation noise because a high-frequency current flows.

In this embodiment, the clock signal pattern 4
A path for the return current to flow near 5 'is ensured by connecting a chip capacitor (not shown) for power supply bypass between the power supply bypass lands 50 and 51 of the second signal layer 55. doing. This is arranged so as to cross the non-pattern portions 60a and 60b of the power supply layer 53 and the second 5V power supply pattern 3c. Thereby, also in the present embodiment, the loop area can be reduced, so that unnecessary radiation noise can be reduced.

As described above, the multilayer printed wiring board of the present invention has been described using three embodiments as examples. In the above-described three embodiments, the example in which the inter-power supply bypass capacitor is mounted on the second signal layer has been described. However, it is more preferable that the bypass capacitor is disposed on the first signal layer near the clock signal pattern. When a plurality of bypass capacitors between power supplies are mounted, they may be mounted separately on the first signal layer and the second signal layer.

(Fourth Embodiment) FIG. 5 is a schematic sectional view of a part of an electronic apparatus according to a fourth embodiment of the present invention.

Referring to FIG. 5, a four-layer printed wiring board 600
FIG. 2 is a cross-sectional view of the multilayer printed wiring board composed of four layers of (a) to (d) in FIG. 1 described in the first embodiment.
QF mounted on the upper surface of four-layer printed wiring board 600
The P-type LSI 601 is provided on the LSI land 1 of FIG.
The mold IC 602 is electrically connected to the IC land 2 by solder. Similarly, the power supply-ground bypass capacitor 608a of the chip type capacitor mounted on the lower surface is a bypass capacitor for the LSI 601. In FIG. 1, it is electrically connected to the power supply-ground bypass capacitor lands 8a and 9a by solder. The bypass capacitor 608b between the power supply and the ground is connected to the IC 602.
In FIG. 1, it is electrically connected to the bypass capacitor lands 8b and 9b between the power supply and the ground by soldering. The power supply-ground bypass capacitors 608a and 608b are connected to the power supply
They correspond to the inter-ground bypass capacitors 408a and 408b, respectively.

The power supply bypass capacitor 613 of the chip type capacitor is electrically connected to the power supply bypass capacitor lands 10 and 11 by solder in FIG. 1, and the 5 V power supply pattern of the power supply layer 13 shown in FIG. 3a and the 3.3V power supply pattern 3b are connected. The power supply bypass capacitor 613 corresponds to the power supply bypass capacitor 413 in FIG.

In addition to the components shown in FIG. 1, a connector 603 and a power cable 604 are shown on the four-layer printed wiring board 600 shown in FIG. Four-layer printed wiring board 600
Has many other components mounted on it.
Is omitted here.

The housing 607 constitutes a part of the frame of the electronic device. A support 606 for mounting the four-layer printed wiring board 600 is attached to the housing 607 by welding. The wiring board 600 is fixed to the support 606 with, for example, screws 605.

In general, electronic equipment is defined so that unnecessary radiation noise does not occur above a certain level in each country. Unnecessary radiation noise from electronic equipment is directly radiated from the four-layer printed wiring board 600, Alternatively, the signal is transmitted to the cable 604 via the connector 603, and the cable 60
Or radiated from 4.

As a countermeasure, for example, a noise source is surrounded by a metal casing 607 to prevent unnecessary radiation noise from leaking out of the electronic device. However, there are openings in the housing 607 for various reasons such as measures against temperature rise, and unnecessary radiation noise leaks from the openings, and it is actually difficult to take measures.

Electronic equipment incorporating the four-layer printed wiring board 600 of the present embodiment can realize low noise even if there is some defect in the electromagnetic wave shield. That is, by reducing the loop area 414 as shown in FIG. 2, not only unnecessary radiation noise directly generated from the four-layer printed wiring board 600 can be reduced, but also the power and ground of the printed wiring board can be stabilized, and the connector 603 can be used. The noise transmitted to the cable 604 via the cable 604 is also reduced, and the unnecessary radiation noise from the cable 604 is also reduced.

As a result, unnecessary radiation noise generated from the electronic device can be easily reduced.

In the first to fourth embodiments, a printed wiring board composed of four layers is used, but the number of layers is not limited. Further, the material of the housing 607 of the fourth embodiment is not limited, and may be made of metal or resin, and the method of attaching the four-layer printed wiring board 600 to the housing 607 is not limited to screwing.

[0067]

As described above, according to the present invention, the capacitor is mounted near the signal line of the first wiring layer and at a position crossing the discontinuous portion of the conductive pattern, and divided at the discontinuous portion. By connecting the conductive patterns thus formed, the loop area formed by the high-frequency current and the return current can be reduced. As a result, generation of unnecessary radiation noise in proportion to the loop area can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a multilayer printed wiring board according to a first embodiment of the present invention for each layer.

FIG. 2 is a circuit diagram showing a circuit configuration in consideration of the cross-sectional structure of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a multilayer printed wiring board according to a second embodiment of the present invention for each layer.

FIG. 4 is a plan view showing a multilayer printed wiring board according to a third embodiment of the present invention for each layer.

FIG. 5 is a schematic sectional view of an electronic device according to a fourth embodiment of the invention.

FIG. 6 is a plan view showing a conventional multilayer printed wiring board for each layer.

7 is a circuit diagram showing a circuit configuration in consideration of a cross-sectional structure of the multilayer printed wiring board of FIG.

FIG. 8 is a plan view showing a conventional multilayer printed wiring board having a divided power supply pattern for each layer.

9 is a circuit diagram showing a circuit configuration in consideration of a cross-sectional structure of the multilayer printed wiring board of FIG.

[Explanation of symbols]

1, 21, 41, 101, 121 Land for LSI 2, 22, 42, 102, 122 Land for IC 3a, 103a, 123a 5V power supply pattern 23a, 43a First 5V power supply pattern 3b, 23b, 43b, 123b 3V power supply pattern 23c, 43c Second 5V power supply pattern 4, 24, 44, 104, 124 Ground pattern 5, 25, 45, 105, 125 Signal pattern 5 ', 25', 45 ', 105', 125 'Clock signal pattern 6,6a, 6b, 26,26a, 26b, 26c 1, 2
6c ₂ , 46, 46a, 46b, 106, 126 Through-hole lands 7, 7a, 7b, 27, 27a, 27b, 27c ₁ , 2
7c ₂ , 47, 47a, 47b, 107, 127 Clearance holes 8a, 8b, 9a, 9b, 28a, 28b, 29a, 2
9b, 48a, 48b, 49a, 49b, 108a, 1
08b, 109a, 109b, 128a, 128b,
129a, 129b Lands for bypass capacitor between power supply and ground 10, 11, 30, 31, 32, 33, 50, 51,
Land for power supply bypass capacitor 12, 32, 52, 112, 132 First signal layer 13, 33, 53, 113, 133 Power supply layer 14, 34, 54, 114, 134 Ground layer 15, 35, 55, 115, 135 Second signal layer 20, 40a, 40b, 60a, 60b, 120 Non-pattern part 200, 300, 400 IC circuit 201, 301, 401 Buffer circuit 202, 302, 402 Clock signal line 203a, 303a, 403a 5V power supply line 204, 304, 404 Ground line 205, 305, 405 5V power supply 206, 306, 406 Ground 207, 307, 407 Stray capacitance 208, 308, 408a, 408b, 608a, 60
8b Power supply-ground bypass capacitor 209, 309, 409 Current 212, 312, 412 Return current 303b, 403b 3.3V power supply line 310, 410 3.3V power supply 311 Non-connection part 413, 613 Power supply bypass capacitor 214, 314, 414 Loop area 600 Four-layer printed wiring board 601 QFP type LSI 602 SOP type IC 603 Connector 604 Cable 605 Screw 606 Supporting tool 607 Housing

Claims (8)

[Claims] A first signal layer on which an electronic component for outputting a high-frequency signal is mounted, and at least a signal line on which a high-frequency signal output from the electronic component flows is provided;
A power supply layer provided below the signal layer for supplying power to the electronic component, a ground layer for providing a reference potential provided below the power supply layer, and a lowermost layer below the ground layer. A second signal layer provided, wherein the electronic component is electrically connected to the power supply layer, the ground layer, and the second signal layer, and the power supply layer is configured to project the signal line. A multilayer printed wiring board having a conductive pattern divided by a discontinuous portion in a direction intersecting the signal line at a position where the signal line crosses the discontinuous portion in the vicinity of the signal line of the first signal layer. A multilayer printed wiring board, wherein the divided conductive patterns are connected at a high frequency by mounting at least one capacitor at a position. 2. The power supply layer includes: a first conductive pattern that supplies power having different voltages to the electronic component;
The multilayer printed wiring board according to claim 1, comprising a second conductive pattern. 3. The first power supply pattern, wherein the power supply layer supplies a power supply having a different voltage to the electronic component.
2. The semiconductor device according to claim 1, further comprising a second conductive pattern, and a third conductive pattern having the same voltage as the first conductive pattern, the third conductive pattern being connected to a power supply that automatically stops power supply when not used for a long time. 2. The multilayer printed wiring board according to item 1. 4. The capacitor according to claim 2, wherein the capacitor is connected to the first conductive pattern and the second conductive pattern.
Or the multilayer printed wiring board according to 3. 5. The capacitor according to claim 1, wherein the capacitor connects the first conductive pattern to the third conductive pattern, and a capacitor connects the first conductive pattern to the third conductive pattern. 4. The multilayer printed wiring board according to claim 3, comprising a capacitor. 6. The multilayer printed wiring board according to claim 1, wherein the capacitor is mounted on the first signal layer. 7. The multilayer printed wiring board according to claim 1, wherein the capacitor is mounted on the second signal layer. 8. An electronic device equipped with the multilayer printed wiring board according to claim 1.